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From AHPL to VHDL: a course in hardware description languages

Article  in  IEEE Transactions on Education · December 2000

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IEEE TRANSACTIONS ON EDUCATION, VOL. 43, NO. 4, NOVEMBER 2000
From AHPL to VHDL: A Course in Hardware
Description Languages
Assim A. Sagahyroon
Abstract—As the size and complexity of digital systems increase,
more CAD tools are introduced in the hardware design process; a
recent addition to this process is the use of hardware description
languages (HDLs). Historically, HDL-based design courses have
been taught mostly at the graduate level. Undergraduate courses
have mainly emphasized the principles of digital systems design,
at both the logic and architectural levels. The laboratory compo-
nent of these courses often introduces the students to graphical de-
sign capture tools and their associated simulators. However, within
the past few years industry has been moving away from graphical
design captures and is more openly adopting HDL-based design
methodologies. Based on these industry shifts, one can easily con-
clude that HDLs are becoming an integral part of the design au-
tomation environments; this in turn requires the updating of the
curricula, either by incorporating new courses or by updating ex-
isting ones. Specifically, courses that introduce undergraduates to
HDLs in general and a standard language such as VHDL or Verilog
are becoming essential in preparing future engineers. This paper
discusses an HDL-based design course offered at Northern Arizona
University (NAU). The course is used as a vehicle to introduce NAU
students to the underlying concepts behind modeling, simulating,
and verifying digital systems design using hardware description
languages.
Index Terms—Hardware description languages (HDLs), VHDL.
I. INTRODUCTION
W ITHIN the past few years, industry has been moving
away from graphical design captures and is more openly
adopting hardware description language (HDL)-based design
methodologies. Based on these industry shifts, one can easily
conclude that HDLs are rapidly becoming an integral part of
design automation environments; this in turn requires updating
of curricula, either by incorporating new courses or by modi-
fying the contents of some of the existing courses to reflect the
advents in very large-scale integration (VLSI) design method-
ologies.
Compared to schematic-based design, HDLs provide de-
signers with the following advantages [1]:
• Designs can be transcribed at various levels of abstraction.
Designers can write their register transfer language (RTL)
descriptions without choosing a specific fabrication tech-
nology. Logic synthesis tools can automatically convert
the design to any fabrication technology.
• Describing designs in HDLs allows functional verification
of the design early in the design cycle. Because designers
work at the RTL level, they can optimize and modify the
Manuscript received July 22, 1998; revised July 19, 2000.
The author is with the Department of Mathematics and Computer Science,
California State University, Hayward, CA 94542 USA.
Publisher Item Identifier S 0018-9359(00)10082-2.
0018–9359/00$10.00 © 2000 IEEE
449
RTL description until it meets the desired functionality.
Most design bugs are eliminated at this point. This will
significantly cut down design cycle time.
• Designing with HDLs is analogous to computer program-
ming. A textual description with comments is an easier
way to develop and debug circuits. Gate-level schematics
can be very cumbersome for very complex digital design.
A recent survey [2], “VHDL University Education Report,”
was performed by Texas Instruments of Dallas, Toshiba of
Tokyo, and VHDL International (VI). Ninety-one university
electrical engineering departments were contacted in the United
States. Seventy-one responded. The survey was designed to
assess the following:
• The degree to which undergraduate students were exposed
to HDLs and a language-based design metholody.
• The amount of training available today, along with how
much is required.
• What source material is used to teach HDLs.
• Barriers to increasing undergraduate students’ knowledge
of HDLs.
The survey concluded that undergraduate students working
toward a B.S. degree in electrical engineering receive little
training in HDL, and at many institutions in the United States,
HDL training is not available. A statistical summary of the
findings of the survey is shown in Table I.
Clearly, there is an urgent need to add to or increase the
amount of HDL training available to undergraduates majoring
in electrical or computer engineering.
II. HDL-BASED COURSES
In a previous article [3], the different issues that are rele-
vant to the introduction of HDL-based courses into the cur-
riculum are addressed. Issues such as the level of preparation,
prerequisites, degree of complexity, and resources were pre-
sented and analyzed. It is concluded that an introductory course
in HDL-based logic design should emphasize breadth rather
than depth. It should provide the students with a working knowl-
edge of a broad variety of HDL-based design approaches and
hence give the student a global understanding of HDL-based
design.
An effective undergraduate design course based on HDLs can
be formulated by starting with a language, or a subset of notations
in a language, from which derivation of hardware is clear. That
is, HDLs should be introduced to the students using a simple
language whose constructs have a clear one-to-one hardware
correspondence. The CSE 420 course (Advanced Digital Design)
at Northern Arizona University (NAU) uses the AHPL [4]
450
TABLE I
TRAINING IN HDL IN THE USA
language with favorable results. This language introduces the
students to the concepts of register, transfer description, structural
modeling, and simple concurrency techniques. Moreover, with
a clear one-to-one mapping between the language constructs
and the hardware, the students learn how to describe finite
state machines in a procedural fashion and how to control
the flow of data among registers and buses. Based on this
introductory exposure, the course can then smoothly transit
to a more powerful language with complex and sophisticated
constructs such as the IEEE standard VHDL language. VHDL
is a broad language with a rich set of constructs that can be
used with different goals in mind. For example, it can be used
for synthesis of digital circuits, verification and validation of
digital designs, test vector generation, or simulation of digital
systems.
In the second phase of NAUs course, to introduce the VHDL
language and its underlying concepts, the simulation component
of the language is heavily emphasized. The ability to construct
simulation models using VHDL of a variety of building blocks
can be an invaluable teaching aid and a stepping-stone to a more
advanced application of the language, such as in synthesis and
testing.
A. A Hardware Programming Language (AHPL)
AHPL is a register transfer language developed at the Univer-
sity of Arizona to be used as an educational tool to teach digital
systems design. The language is simple and easy to learn, yet
powerful enough to model simple and complex digital systems.
However, AHPL lacks certain constructs and features that have
little pedagogical significance, but are necessary for efficient re-
alization and testing of digital systems [5].
The language uses an implicit clock for synchronizing as-
signment of data to registers and flip-flops, but does not provide
support for asynchronous circuits. Data types in AHPL are
fixed and restricted to bits, vectors of bits, and arrays of bits.
Procedures or functions are only allowed in the context of
combinational logic units. Assignment of values to buses and
registers occurs at the same time without delay, because they
are synchronized with an implicit clock. The utility of AHPL
is based on the fact that most digital systems can be parti-
tioned into a control section and a data section containing
IEEE TRANSACTIONS ON EDUCATION, VOL. 43, NO. 4, NOVEMBER 2000
data registers and logic. The control section will cause register
transfers to take place in the data section by sending signals
on a set of control lines. In some cases the sequencing of
control will be influenced by branching information fed back
from the data section [4].
The following is an example that illustrates modeling in
AHPL:
AHPLMODULE: SAMPLE
MEMORY: INREG[8]; OUTREG[8]; CNT[3].
EXINPUTS: X[8]; ready.
OUTPUTS: Z[8].
CLUNITS: INC[3].
1 /(I);
CNT
2 INREG X
CNT INC(CNT);
3 OUTREG INREG
ENDSEQUENCE
Z = OUTREG.
END.
The given AHPL sequence describes a simple system that re-
ceives an eight-bit vector X and makes it available as an output
after a delay determined by a three-bit counter, CNT[3]. As
shown in the given example, the AHPL description of a module
consists of a name, a list of declarations, a control sequence, a
list of individual connection statements, and a termination. The
control sequence consists of a series of action statements such
as register transfers or bus routes, followed by a branch. For ex-
ample, in the given description, at control step 3, the contents of
register INREG are copied into register OUTREG and an uncon-
ditional branch to step 1 ( (1)) will take place. AHPL main-
tains a small library of combinational logic units that are used
repeatedly in various digital systems. The INCREMENT (INC)
SAGAHYROON: FROM AHPL TO VHDL: A COURSE IN HARDWARE DESCRIPTION LANGUAGES
function used in step 2 of the AHPLMODULE shown above
is a good example. The transfer CNT INC(CNT) has the effect
of increasing the number stored in register CNT by 1 at the ar-
rival of a clock-triggering edge. The list of statements between
the keywords ENDSEQUENCE and END will be active every
clock period regardless of the control state or step.
Clock-level simulation of AHPL descriptions can be ac-
complished using the function-level simulator HPSIM2 [13].
HPSIM is a function-level simulator that interprets the AHPL
description and executes the connections, branches, and register
transfers. Users can verify the correctness of their design by
analyzing the results provided in an output file that shows
the contents of the various components at every clock period.
HPSIM will be discussed further in a later section. For a
thorough discussion of AHPL and its simulator, readers are
referred to references [4] and [13]. The complete package of
AHPL tools may be obtained by contacting the Department
of Electrical and Computer Engineering at the University of
Arizona.
B. The VHDL Language: An Overview
Currently, one of the most widely accepted and used HDLs
by the design community is VHDL. Partly in reaction to the
proliferation of HDLs and partly due to its own needs, in 1980
the Department of Defense (DoD) initiated the development
of VHDL [6]–[8] as part of its very high-speed integrated cir-
cuits (VHSIC) program; thus the name VHDL-VHSIC HDL.
The overall objective of this effort was to design a single lan-
guage that will allow the design, description, and simulation of
hardware at various levels ranging from behavioral to structural.
Moreover, the intent was to make VHDL the standard HDL in
all DoD hardware design projects and to use the language as
a means of communicating designs from one contractor to an-
other. The criteria used in designing VHDL included indepen-
dence of the language from any specific technology, design en-
vironment, or design methods. Consequently, it should be pos-
sible to integrate the language into any combination of environ-
ment, technology, and methodology.
In 1987, VHDL was approved by the IEEE as the standard
language for designing and modeling hardware. Subsequently,
many computer-aided engineering companies, as well as uni-
versities, channeled resources into developing tools based on
VHDL. Today, VHDL is supported by nearly all design automa-
tion tools and is widely used in the design cycle for simulation,
synthesis, and testing.
Due to the strong presence of VHDL in the IC design cycle
and design automation industry, an undergraduate design course
based on HDLs should place heavy emphasis on covering as
much of the VHDL language as possible. However, VHDL can
easily be classified as a complex language with a rich set of con-
current and sequential constructs, many of which do not have a
unique hardware correspondence. Furthermore, there are con-
structs in VHDL with no clear hardware mapping. As a result,
transition to a language such as VHDL from block diagrams and
schematics can easily be too large a step for many students. To
circumvent this problem, the students are introduced to AHPL
first and then progressed to the more powerful VHDL.
451
III. COURSE DESCRIPTION
All undergraduate students at Northern Arizona University
majoring in computer science and engineering (CSE) or elec-
trical engineering (EE) are required to take the following intro-
ductory computer hardware courses:
CSE 247 Introductory Digital Logic Design;
CSE 355 Microprocessors;
CSE 366 Computer Architecture.
Computer Architecture is a core course for CSE majors and a
technical elective for EE majors. Additional technical electives
in the computer systems design area are listed below:
CSE 410 Logic Design Theory;
CSE 420 Advanced Digital Design;
CSE 440 Embedded Control;
CSE 450 Parallel Computing;
EGR
482 Introduction to VLSI Design.
In the fall of 1997, the department became a participant of the
Mentor Graphics Higher Education Program. Mentor Graphics
offers an extremely attractive university program, where schools
can acquire their CAD tools for a discounted annual fee. The de-
partment laboratory facility consists of more than 30 Sun Sparc-
stations running Solaris operating systems on a UNIX platform.
An agreement with Mentor Graphics provided for a total of 10
licenses. The average enrollment in technical electives is about
20 students. Students work in pairs to model, simulate, and test
their designs.
In a digital system of design process, students learn how to
design systems, from requirements analysis, to specification of
the requirements, to functional design, to register level design,
to logic design, to circuit design, and then to physical design.
These design stages use hardware descriptions at various levels
of abstraction. A widely used representation that depicts the dif-
ferent levels of abstractions in a digital system is the Y-chart
[10], [11], shown in Fig. 1.
It is apparent from the chart that a system can be described
and the functionality verified at different levels of abstraction.
At most of these levels, the designer need not worry about the
physical implementation or target technology.
The advanced digital design course (CSE 420) discusses
modeling using HDLs at the behavioral and structural levels.
The topics covered in the course are summarized as follows:
• design Conventions;
• introduction to a Hardware Programming Language
(AHPL);
• modeling in AHPL;
• introduction to VHDL;
• VHDL Modeling Concepts;
• structural Modeling in VHDL;
• dataflow Modeling Using VHDL;
• behavioral Modeling in VHDL;
• subprograms; Packages and Libraries;
• modeling of Test Benches;
• basic Input–Output.
As pointed out earlier, VHDL is a broad language with a rich
set of constructs. For students with a hardware background, it
would be more natural to start with structural modeling. Such
452
Fig. 1. Y-Chart.
models are essentially textual equivalents of schematics and
cover the preliminaries of the language. Concepts such as design
configuration and use of packages can be postponed until later
in the course. Following structural models, dataflow (or register
transfer) models can be introduced. These models provide ex-
posure to a larger set of language constructs while maintaining
some level of correspondence with hardware. At this point in the
course, the majority of language constructs have been covered.
The next topic, behavioral modeling, makes use of the same
constructs as used in dataflow models plus a few more in a
less structured way. This effectively covers most of the VHDL
language in a way that builds on top of previous logic design
courses. Students are required to complete homework assign-
ments from the textbooks [4], [6] as well as performing simu-
lation-based exercises using the Mentor Graphics environment.
Initially (up to approximately a third of the semester), and until
the students have had adequate exposure to the languages, es-
pecially VHDL, they are instructed to solve the various assign-
ments manually. They are subsequently introduced to the design
automation platform and are permitted to use it to verify their
designs.
Students are assigned the following set of laboratory exer-
cises:
• design of a Magnitude Comparator (AHPL);
• multiplier (AHPL).
In these exercises, students make use of the HPSIM func-
tion-level simulator included in the AHPL package. Two input
files required by HPSIM are an AHPL description of the circuit
and a communication file. The communication file is used to
assign initial values to external lines, set the clock limit, and
specify what is to be included in the final output listing. In
essence, the output generated by HPSIM is a simulation report
that reflects the contents of the various hardware units at every
clock cycle. Students are required to analyze this output and
verify the functionality of their designs.
The rest of the exercises are all VHDL based. The class de-
signs, simulates, and tests the following circuits:
• multiplier;
• 16-bit Arithmetic and Logic Unit;
• 16-bit Comparator;
IEEE TRANSACTIONS ON EDUCATION, VOL. 43, NO. 4, NOVEMBER 2000
• sequence Detector;
• nine-bit UP/DOWN Counter.
The multiplier design is repeated intentionally to provide the
students with an opportunity to compare the two languages and
their constructs. Such an experience allows the students to ap-
preciate the power and sophistication built into the VHDL lan-
guage.
In general, the projects were chosen to cover all the funda-
mental topics concerned with the design, modeling, and ver-
ification of digital systems using HDLs. For example, in the
Comparator assignment, students learn hierarchical design tech-
niques and the use of VHDL higher level constructs to define
repetitive hardware structures. In the Sequence Detector project,
they use processes and wait statements to model sequential or
time-sensitive behavior. The UP–DOWN counter is a problem
that was given in a design contest [12] for designers who use
either VHDL or Verilog. The problem specifies the design of a
nine-bit up-by-three and down-by-five counter with even parity,
carry, borrow, and counter values as outputs where all output
signals are flip-flop outputs.
To simulate and test their VHDL designs, students use the
QuickHDL-VHDL simulator from Mentor Graphics. Fig. 2
shows a screen capture of a typical simulation run. QuickHDL
is a simulation tool for models written in either VHDL or
Verilog. It can be used to model and test a system quickly
at a high level of abstraction. This keeps the analysis of a
design manageable and allows the user to identify and correct
many design problems or errors before they propagate to the
lower gate-level implementations or the breadboard level. The
graphical user interface of QuickHDL consists of a startup
window, which appears after the simulator is invoked, and other
windows that may be used during the simulation (see Fig. 2).
These windows are as follows [14].
• The initial Startup Window lets the student set up the en-
vironment when invoke the application is invoked.
• The QuickHDL Main Window is that from which all sub-
sequent windows are available.
• The Source Window displays the VHDL or Verilog source
code for the design in read-only mode.
• The Structure Window displays the hierarchy of structural
VHDL elements such as component instances, packages,
blocks, and generated statements.
• The Dataflow Window displays a signal or process in the
center of the window and also shows the current process
when single-stepping or when QuickHDL encounters a
breakpoint.
• The List Window shows the simulation of selected signals.
• The Wave Window displays waveforms, names, and cur-
rent values for the signals selected.
• The Process Window displays a list of processes that are
scheduled to run during the current simulation cycle.
• The Variables Window shows the constants, generics, and
variables in the current process and their current values.
• The Signals Window shows the names and current values
of signals in the region currently selected in the structure
window.
• The Schematic Window displays a schematic that corre-
sponds to your design.
SAGAHYROON: FROM AHPL TO VHDL: A COURSE IN HARDWARE DESCRIPTION LANGUAGES
Fig. 2. QuickHDL Windows.
Clearly, the QuickHDL environment provides the students
with a powerful tool that allows an in-depth analysis and a clear
understanding of a particular design. Students react very pos-
itively to the graphical interface and no doubt it assists in en-
hancing and accelerating their understanding of the underlying
concepts in digital design.
In the last two laboratory assignments, rather than interac-
tively inputting the initial values of the different lines, students
are required to develop test benches. These benches are used to
verify the VHDL code without entering simulation commands
and variable values every time a change is made. In each of the
projects, students work in pairs and are required to submit a lab
report that includes the following items:
• a problem description;
• fully documented entity and architectural descriptions of
the design modules;
• trace demos (timing waveforms) showing inputs and cor-
responding outputs;
• simulation reports;
• analysis and discussion of the results.
453
IV. CONCLUSION
Today’s engineers are expected to utilize highly integrated
design environments that support HDL, standard cell, field pro-
grammable gate arrays, and mixed-signal VLSI designs. They
need to be able to model real designs, simulate them, and verify
their correctness in a relatively short period of time. To ac-
complish this, designers are replacing the traditional schematic-
based design entry tools with hardware description languages
such as VHDL and Verilog as the preferred design mediums.
Therefore, the need to train future engineers in HDL-based de-
sign techniques is considerable, and modern engineering cur-
ricula must reflect the advances made in VLSI design method-
ologies. To address this need and provide NAU’s undergradu-
ates with some of the required skills, the faculty have revised
one of the senior-elective courses at the Department of Electrical
Engineering and Computer Science. The modified contents of
the course expose the students to the concepts of digital design
modeling at various levels of abstractions using hardware de-
sign languages. Students learn how to use HDLs to write their
circuit description without choosing a specific fabrication tech-
454
nology, and they learn how logic synthesis tools can be used to
easily convert the designs to future technologies. Students un-
derstand the importance of functionally verifying their designs
early in the design cycle and hence achieving a significant time
reduction in the design flow.
In summary, the revised course, which makes use of the
Mentor Graphics suite of tools, has provided undergraduate
students with valuable hands-on design opportunities and
enhanced their knowledge and expertise in the domain of
ASIC’s design.
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[8] M. Shahdad, “An overview of VHDL language and technology,” in Proc.
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[9] M. T. O’Keefe, J. Lindenlaub, S. Ban, and T. Waheln, “Introducing
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[10] D. Gajski, Silicon Compilation. Reading, MA: Addison-Wesley, 1988.
[11] S. Yolamanchili, VHDL Starter’s Guide. Englewood Cliffs, NJ: Pren-
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Assim A. Sagahyroon received the B.S degree in electrical engineering from
the University of Khartoum, Sudan, in 1981, the M.S degree in electrical en-
gineering from Northwestern University, Evanston, IL, in 1984, and the Ph.D.
degree from University of Arizona, Tucson, in 1989.
From 1989 to 1992, he was with the Department of Electrical Engineering,
University of Khartoum. During the 1992 to 1993 academic year, he joined the
Department of Electrical and Computer Engineering, University of Arizona, as
a Visiting Faculty. In 1993, he joined the Department of Computer Science and
Engineering at Northern Arizona University, where he became an Associate Pro-
fessor in February 1999. He is currently with the Department of Mathematics
and Computer Science at California State University, Hayward. His interests in-
cludeVLSI design and testing, computer architecture, and design for low power.
Dr. Sagahyroon is a member of Etta Kappa Nu and the IEEE Computer So-
ciety.