Thyristor :

Thyristor is a four layer three junction pnpn semiconductor switching device. It has 3 terminals these are
anode, cathode and gate. SCRs are solid state device, so they are compact, possess high reliability and
have low loss. It is a unidirectional device.

SILICON CONTROLLED RECTIFIER (SCR) : The SCR is a four layer three terminal device with

junctions
J1 , J 2 , J 3 as shown. The construction of SCR shows that the gate terminal is kept nearer the
cathode.

When the anode is made positive with respect the

cathode junctions
J1 & J 3 are forward biased

and junction
J 2 is reverse biased. With anode to

cathode voltage
VAK being small, only leakage

current flows through the device. The SCR is

Fig.: Symbol
then said to be in the forward blocking state. If
VAK is

further increased to a large value, the reverse

biased junction
J 2 will

breakdown due to avalanche effect resulting in a large current through the device. The voltage at which
V
this phenomenon occurs is called the forward breakdown voltage BO resulting in a large forward anode
current. Once the SCR is switched on, the voltage drop across it is very small, typically 1 to 1.5V. the
V
forward voltage is maintained well below BO and the SCR is turned on by applying a positive voltage
between gate and cathode. With the application of positive gate voltage, the leakage current through the

junction
J 2 is increased. With increase in gate current breakdown occurs earlier.

Static Anode-Cathode characteristics of SCR :

 Fig.2 Static Anode cathode characteristics of SCR

The circuit diagram for obtaining static V-I characteristics is as shown Anode and cathode are connected
to main source voltage through the load. The gate and cathode are fed from source .

𝑉𝐵𝑂=Forward breakover voltage

𝑉𝐵𝑅=Reverse breakover voltage

𝐼𝑔=Gate current

𝑉𝑎=Anode voltage across the thyristor terminal A,K.

𝐼𝑎=Anode current It can be inferred from the static V-I characteristic of SCR.

A typical SCR V-I characteristic is as shown in fig.2

SCR have 3 modes of operation:

1. Reverse blocking mode

2. Forward blocking mode ( off state)
3. Forward conduction mode (on state)

1. Reverse Blocking Mode : When cathode of the thyristor is made positive with respect to anode with
switch open thyristor is reverse biased. Junctions 𝐽1 and 𝐽2 are reverse biased where junction 𝐽2 is
forward biased. The device behaves as if two diodes are connected in series with reverse voltage applied
across them. A small leakage current of the order of few mA only flows. As the thyristor is reverse
biased and in blocking mode. It is called as acting in reverse blocking mode of operation. Now if the
reverse voltage is increased, at a critical breakdown level called reverse breakdown voltage 𝑉𝐵𝑅, an
avalanche occurs at 𝐽1 and 𝐽3 and the reverse current increases rapidly. As a large current associated with
𝑉𝐵𝑅 and hence more losses to the SCR. This results in Thyristor damage as junction temperature may
exceed its maximum temperature rise.
2. Forward Blocking Mode : When anode is positive with respect to cathode, with gate circuit open,
thyristor is said to be forward biased. Thus junction 𝐽1 and 𝐽3 are forward biased and 𝐽2 is reverse biased.
As the forward voltage is increases junction 𝐽2 will have an avalanche breakdown at a voltage called
forward breakover voltage𝑉𝐵𝑂. When forward voltage is less then 𝑉𝐵𝑂thyristor offers high impedance.
Thus a thyristor acts as an open switch in forward blocking mode.

3. Forward Conduction Mode : Here thyristor conducts current from anode to cathode with a very small
voltage drop across it. So a thyristor can be brought from forward blocking mode to forward conducting
mode:

1. By exceeding the forward breakover voltage.

2. By applying a gate pulse between gate and cathode.

During forward conduction mode of operation thyristor is in on state and behave like a close switch.
Voltage drop is of the order of 1 to 2mV. This small voltage drop is due to ohmic drop across the four
layers of the device.

VBO : The anode to cathode voltage applied

between anode and cathode terminal of SCR at
which anode current increases and SCR starts to
conduct
HOLDING CURRENT (
IH )

After an SCR has been switched to the on state a

certain minimum value of anode current is
required to maintain the thyristor in this low
impedance state. If the anode current is reduced
below the critical holding current value, the
thyristor cannot maintain the current through it ,
it is associated with turn off the device.
LATCHING CURRENT ( L )
I
After the SCR has switched on, there is a minimum current required to sustain conduction. This current is
called the latching current.
I L associated with turn on and is usually greater than holding current.

THYRISTOR TURN OFF CHARACTERISTICS

 V A K
tC
tq

IA
d i
C o m m u t a t io n
A n o d e c u rre n t d t
b e g in s t o
d ecrea se R ecovery R e c o m b in a tio n

t1 t2 t3 t4 t5

tq= d e v ic e o f f t im e
trr tgr
tc= c ir c u it o f f t im e
tq
tc

When an SCR is turned on by the gate signal, the gate loses control over the device and the device can be
brought back to the blocking state only by reducing the forward current to a level below that of the
holding current. In AC circuits, however, the current goes through a natural zero value and the device will
automatically switch off. But in DC circuits, where no neutral zero value of current exists, the forward
current is reduced by applying a reverse voltage across anode and cathode and thus forcing the current
through the SCR to zero.

t
As in the case of diodes, the SCR has a reverse recovery time rr which is due to charge storage in the
junctions of the SCR. These excess carriers take some time for recombination resulting in the gate
t t
recovery time or reverse recombination time gr . Thus, the turn-off time q is the sum of the durations for
which reverse recovery current flows after the application of reverse voltage and the time required for the
recombination of all excess carriers present. At the end of the turn off time, a depletion layer develops

across
J 2 and the junction can now withstand the forward voltage. The turn off time is dependent on the
Vg
anode current, the magnitude of reverse applied ad the magnitude and rate of application of the
forward voltage. The turn off time for converter grade SCR’s is 50 to 100sec and that for inverter grade
SCR’s is 10 to 20sec.

To ensure that SCR has successfully turned off , it is required that the circuit off time
tc be greater than
tq
SCR turn off time .

SCR Turn OFF Methods

The turn OFF process of an SCR is called commutation. The term commutation means the transfer of
currents from one path to another. To turn OFF the conducting SCR the below conditions must be
satisfied.
 The anode or forward current of SCR must be reduced to zero or below the level of holding current and
then,
A sufficient reverse voltage must be applied across the SCR to regain its forward blocking state.
When the SCR is turned OFF by reducing forward current to zero. There exist excess charge carriers in
different layers. To regain the forward blocking state of an SCR, these excess carriers must be
recombined. Therefore, this recombination process is accelerated by applying a reverse voltage across the
SCR.
commutation methods are classified into two major types.

1) Forced commutation and 2) Natural commutation.

Natural commutation
This method of commutation is also called as source commutation, or line commutation, or class F
commutation. In natural commutation, the source of commutation voltage is the supply source itself. If
the SCR is connected to an AC supply, at every end of the positive half cycle the anode current goes
through the natural current zero and also immediately a reverse voltage is applied across the SCR. These
are the conditions to turn OFF the SCR.

Forced Commutation
In case of DC circuits, there is no natural current zero to turn OFF the SCR. In such circuits, forward
current must be forced to zero with an external circuit to commutate the SCR hence named as forced
commutation.
This commutating circuit consist of components like inductors and capacitors called as commutating
components. These commutating components cause to apply a reverse voltage across the SCR that
immediately bring the current in the SCR to zero.

Class A Commutation
This is also known as self commutation, or resonant commutation, or load commutation. In this
commutation, the source of commutation voltage is in the load. This load must be an under damped R-L-
C supplied with a DC supply so that natural zero is obtained.

The commutating components L and C are connected either parallel or series with the load resistance R as
shown below with waveforms of SCR current, voltage and capacitor voltage.
The value of load resistance and commutating components are so selected that they forms a under
damped resonant circuit to produce natural zero. When the thyristor or SCR is triggered, the forward
currents starts flowing through it and during this the capacitor is charged up to the value of E.

Once the capacitor is fully charged (more than the supply source voltage) the SCR becomes reverse
biased and hence the commutation of the device. The capacitor discharges through the load resistance to
make ready the circuit for the next cycle of operation. The time for switching OFF the SCR depends on
the resonant frequency which further depends on the L and C components.

This method is simple and reliable. For high frequency operation which is in the range above 1000 Hz,
this type of commutation circuits is preferred due to the high values of L and C components.

Class B Commutation
This is also a self commutation circuit in which commutation of SCR is achieved automatically by L and
C components, once the SCR is turned ON. In this, the LC resonant circuit is connected across the SCR
but not in series with load as in case of class A commutation and hence the L and C components do not
carry the load current.

When the DC supply is applied to the circuit, the capacitor charges with an upper plate positive and lower
plate negative up to the supply voltage E. When the SCR is triggered, the current flows in two directions,
one is through E+ – SCR – R – E- and another one is the commutating current through L and C
components.

Once the SCR is turned ON, the capacitor is starts discharging through C+ – L – T – C-. When the
capacitor is fully discharged, it starts charging with a reverse polarity. Hence a reverse voltage applied
across the SCR which causes the commutating current IC to oppose load current IL.

When the commutating current Ic is higher than the load current, the SCR will automatically turn OFF
and the capacitor charges with original polarity.
In the above process, the SCR is turned ON for some time and then automatically turned OFF for some
time. This is a continuous process and the desired frequency of ON/OFF depends on the values of L and
C. This type of commutation is mostly used in chopper circuits.

THYRISTOR TURN ON
1)Forward-voltage triggering : This is triggering without application of gate voltage with only
application of a large voltage across the anode-cathode such that it is greater than the forward breakdown
V
voltage BO . If the forward anode to cathode voltage is increased, the collector to emitter voltages of both
the transistors are also increased. As a result, the leakage current at the middle junction J2 of thyristor
increases, This leads to switching action of the device due to regenerative action. This type of turn on is
destructive and should be avoided.

2) Temperature triggering : At high temperature, the forward leakage current across junction J2 rises.
This leakage current serves as the collector junction current of the component transistors Q1 and Q2. This
 
would cause an increase in 1 & 2 and the thyristor may turn on. This type of turn on many cause
thermal run away and is usually avoided.
3) Light triggering : When light is allowed to fall on the junctions of a thyristor, charge carrier
concentration would increase the electron-hole pairs. As stated before, gate-triggering is the most
common method for turning-on a thyristor. Light triggered thyristors are used in HVDC applications.
LASCR: Light activated SCRs are turned on by allowing light to strike the silicon wafer.
4) dv/dt triggering : The reversed biased junction J2 behaves like a capacitor because of the space-
charge present there. Let the capacitance of this junction be Cj. For any capacitor, i = C dv/dt. In case it is
assumed that entire forward voltage va appears across reverse biased junction J2 then charging current
across the junction is given by

dv
i = Cj dt

dv
1
if dt is large, j2 will be large. A high value of charging current may damage the thyristor and the device
dv
must be protected against high dt .

4) Gate Triggering: Gate triggering is the method practically employed to turn-on the thyristor.

Now a sufficient gate-drive current between gate and cathode of the thyristor is applied.

a) DC gate triggering

b) AC gate triggering

c) Pulse gate triggering.

RESISTANCE TRIGGERING
A simple resistance triggering circuit is as shown. The resistor
R1 limits the current through the gate of
R
the SCR. 2 is the variable resistance added to the circuit to achieve control over the triggering angle of
SCR. Resistor ‘R’ is a stabilizing resistor. The diode D is required to ensure that no negative voltage
reaches the gate of the SCR.

vO
a b
LO AD

i R 1

R 2

v S = V m s in  t
D V T

R V g

Fig.: Resistance firing circuit

V S V S V S
V m s in  t

3 4 3 4 3 4
 2 t  2 t  2 t

Vg Vgt Vg Vg Vgp> Vgt

Vgp= Vgt

Vgp Vgp Vgt t t t

Vo Vo Vo

t t t
io io io

t 0 t t
270
VT VT VT

3 4
t  2 t t
 0 0
0 = 90 < 90
90

(a ) (b ) (c )

Fig.:
Resistance firing of an SCR in half wave circuit with dc load

(a) No triggering of SCR (b)  = 900 (c)  < 900

Design
Vm
 I gm
With
R2  0 , we need to ensure that
R1
I
, where gm is the maximum or peak gate current of the
Vm
R1 
I gm
SCR. Therefore .

Also with 2
R 0
, we need to ensure that the voltage drop across resistor ‘R’ does not exceed
Vgm
, the
maximum gate voltage

Vm R
Vgm 
R1  R
 Vgm R1  Vgm R  Vm R
 Vgm R1  R  Vm  Vgm 
Vgm R1
R
Vm  Vgm

OPERATION
Vgp  Vgt
Case 1:

Vgp Vgt R2 is very large. Therefore, current ‘I’ flowing through

, the peak gate voltage is less then since
v
the gate is very small. SCR will not turn on and therefore the load voltage is zero and scr is equal to
Vs .
This is because we are using only a resistive network. Therefore, output will be in phase with input.

Vgp  Vgt R2 
Case 2: , optimum value.

When
R2 is set to an optimum value such that Vgp  Vgt , we see that the SCR is triggered at 900 (since
Vgp 0 0
reaches its peak at 90 only). The waveforms shows that the load voltage is zero till 90 and the
0
voltage across the SCR is the same as input voltage till it is triggered at 90 .

Vgp  Vgt R2 
Case 3: , small value.

Vgt 0 V
The triggering value is reached much earlier than 90 . Hence the SCR turns on earlier than S

reaches its peak value. The waveforms as shown with respect to

Vs  Vm sin  t .
  t   ,VS  Vgt , Vm  Vgp  Vgt  Vgp sin  
At

V 
  sin 1  gt 
 Vgp 
Therefore  

Vm R
Vgp 
But
R1  R2  R

 V  R  R2  R  
  sin 1  gt 1 
 Vm R 
Therefore

Since
Vgt , R1 , R
are constants
 R2

RESISTANCE CAPACITANCE TRIGGERING

RC HALF WAVE

Capacitor ‘C’ in the circuit is connected to shift the phase of the gate voltage.
D1 is used to prevent
negative voltage from reaching the gate cathode of SCR.

In the negative half cycle, the capacitor charges to the peak negative voltage of the supply
 Vm 
through the diode
D2 . The capacitor maintains this voltage across it, till the supply voltage crosses zero.

As the supply becomes positive, the capacitor charges through resistor ‘R’ from initial voltage of
Vm , to
a positive value.

When the capacitor voltage is equal to the gate trigger voltage of the SCR, the SCR is fired and the
capacitor voltage is clamped to a small positive value.

vO

LO AD
+
R
D 2 V T

-
v S = V m s in  t
D 1
V C C
 Fig.: RC half-wave trigger circuit

V m s in  t V m s in  t
vs vs
V gt V gt

-/2 0 -/2 0
0 t 0 t
vc vc
vc vc
a a a a
vo   vo
Vm Vm
0
    t  t
vT vT

Vm
  0   t
-V m t  
 -V m
(2 +  )

(a ) (b )

Fig.: Waveforms for RC half-wave trigger circuit

(a) High value of R (b) Low value of R

Case 1: R  Large.

When the resistor ‘R’ is large, the time taken for the capacitance to charge from
Vm to Vgt is large,
resulting in larger firing angle and lower load voltage.

Case 2: R  Small

Vgt
When ‘R’ is set to a smaller value, the capacitor charges at a faster rate towards resulting in early
V
triggering of SCR and hence L is more. When the SCR triggers, the voltage drop across it falls to 1 –
1.5V. This in turn lowers, the voltage across R & C. Low voltage across the SCR during conduction period
keeps the capacitor discharge during the positive half cycle.

DESIGN EQUATION
VC  Vgt  Vd 1
From the circuit . Considering the source voltage and the gate circuit, we can write
vs  Vgt  Vd 1
R
vs  I gt R  VC v  I R V v  I R V V I
. SCR fires when s gt C
that is S g gt d1
. Therefore gt

. The RC time constant for zero output voltage that is maximum firing angle for power frequencies is
T 
RC  1.3  
empirically gives as  2.

RC FULL WAVE
A simple circuit giving full wave output is shown in figure below. In this circuit the initial voltage from
which the capacitor ‘C’ charges is essentially zero. The capacitor ‘C’ is reset to this voltage by the
clamping action of the thyristor gate. For this reason the charging time constant RC must be chosen
longer than for half wave RC circuit in order to delay the triggering. The RC value is empirically chosen as

50T v  Vgt
RC  R s
2 . Also I gt
.

vO

LOAD
+
+
D1 D3 R
V T

v d -

C
vS= V m s in  t
D4 D2
-
 Fig: RC full-wave trigger circuit

Fig:
vs V m s in  t vs V m s in  t

t t

vd
vd vd

vc vc vgt vc t vgt t
vo vo
  

t t
vT vT

t
(a ) (b )

Wave-forms for RC full-wave trigger circuit

(a) High value of R (b) Low value of R

PROBLEM

1. Design a suitable RC triggering circuit for a thyristorised network operation on a 220V, 50Hz
Vgt min  5V I gt max  30mA
supply. The specifications of SCR are , .
 vs  Vgt  VD
R  7143.3
Ig

Therefore RC  0.013

R  7.143k 

C  1.8199  F

UNI-JUNCTION TRANSISTOR (UJT)

B 2 B 2

E t a - p o in t +
B 2
R B2 E t a - p o in t
R B2
p -ty p e
E
E A A V BB
E +
R B1
n -ty p e R
V e Ie B1
V BB

- -
B 1 B 1 B 1

(a) (b ) (c)

Fig.: (a) Basic structure of UJT (b) Symbolic representation

(c) Equivalent circuit

UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals base1, base2 and

emitter ‘E’. Between

B1 and B2 UJT behaves like ordinary resistor and the internal resistances are given
R R
as B1 and B 2 with emitter open B B
R  RB1  RB 2 . Usually the p-region is heavily doped and n-region
V B B
is lightly doped. The equivalent circuit of UJT is as shown. When BB is applied across 1 and 2 , we
find that potential at A is
 VBB RB1  RB1 
VAB1   VBB   
RB1  RB 2  RB1  RB 2 

 is intrinsic stand off ratio of UJT and ranges between 0.51 and 0.82. Resistor RB 2 is between 5 to
10K.

OPERATION

When voltage
VBB is applied between emitter ‘E’ with base 1 B1 as reference and the emitter voltage

VE is less than  VD  VBE  the UJT does not conduct.  VD  VBB  is designated as VP which is the
V
value of voltage required to turn on the UJT. Once E is equal to P
V  VBE  VD , then UJT is forward
biased and it conducts.

I
The peak point is the point at which peak current P flows and the peak voltage P is across the UJT.
V
After peak point the current increases but voltage across device drops, this is due to the fact that
emitter starts to inject holes into the lower doped n-region. Since p-region is heavily doped compared to
n-region. Also holes have a longer life time, therefore number of carriers in the base region increases

rapidly. Thus potential at ‘A’ falls but current

I E increases rapidly. RB1 acts as a decreasing resistance.

The negative resistance region of UJT is between peak point and valley point. After valley point, the

device acts as a normal diode since the base region is saturated and
RB1 does not decrease again.

N e g a t iv e R e s i s t a n c e
R e g io n
Ve
C u to ff S a tu r a tio n
r e g io n r e g io n
VBB
R lo a d l in e
Vp
P e a k P o in t

V a ll e y P o i n t

Vv

0 Ip Iv Ie
 Fig.: V-I Characteristics of UJT

UJT RELAXATION OSCILLATOR

UJT is highly efficient switch. The switching times is in the range of nanoseconds. Since UJT exhibits
negative resistance characteristics it can be used as relaxation oscillator. The circuit diagram is as shown

with
R1 and R2 being small compared to RB1 and RB 2 of UJT.

Fig.: UJT
Ve C a p a c it o r C a p a c it o r oscillator
V BB+ V d is c h a r g in g
(a) c h a r g in g Connection
VBB T 2= R 1C
Vp diagram
R2 and (b)
R
B2 VP Voltage
E T 1= R C Vv
VV waveforms

T t
C B1
Ve R1 v
o Vo
1


t
(a ) (b )
OPERATION

When
VBB is applied, capacitor ‘C’ begins to charge through resistor ‘R’ exponentially towards VBB .
  RC . When this
During this charging emitter circuit of UJT is an open circuit. The rate of charging is 1
V
capacitor voltage which is nothing but emitter voltage E reaches the peak point P
V  V  V
BB D , the

emitter base junction is forward biased and UJT turns on. Capacitor ‘C’ rapidly discharges through load

resistance
R1 with time constant  2  R1C   2  1  . When emitter voltage decreases to valley point Vv ,
V
UJT turns off. Once again the capacitor will charge towards BB and the cycle continues. The rate of
charging of the capacitor will be determined by the resistor R in the circuit. If R is small the capacitor

charges faster towards

VBB and thus reaches VP faster and the SCR is triggered at a smaller firing angle.
V
If R is large the capacitor takes a longer time to charge towards P the firing angle is delayed. The
waveform for both cases is as shown below.

EXPRESSION FOR PERIOD OF OSCILLATION ‘T’

The period of oscillation of the UJT can be derived based on the voltage across the capacitor. Here we
assume that the period of charging of the capacitor is lot larger than than the discharging time.

Using initial and final value theorem for voltage across a capacitor, we get

VC  V final   Vinitial  V final  e

t
RC

t  T , VC  VP ,Vinitial  VV , V final  VBB

VP  VBB   VV  VBB  e T / RC
Therefore

 V V 
 T  RC log e  BB V 
 VBB  VP 

If
 VV  VBB ,
 VBB 
T  RC ln  
 VBB  VP 
 
 1 
 RC ln  
1  VP 
 VBB 

But
VP  VBB  VD

If
VD VBB VP  VBB

 1 
T  RC ln  
Therefore 1   

DESIGN OF UJT OSCILLATOR

Resistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms. The upper limit on ‘R’ is set by
V
the requirement that the load line formed by ‘R’ and BB intersects the device characteristics to the
right of the peak point but to the left of valley point. If the load line fails to pass to the right of the peak
VBB  VP
R
point the UJT will not turn on, this condition will be satisfied if
VBB  I P R  VP , therefore IP .

At the valley point

I E  IV and VE  VV , so the condition for the lower limit on ‘R’ to ensure turn-off is

VBB  VV
R
VBB  IV R  VV , therefore IV .

The recommended range of supply voltage is from 10 to 35V. the width of the triggering pulse
t g  RB1C
.

In general
RB1 is limited to a value of 100 ohm and RB 2 has a value of 100 ohm or greater and can be

104
RB 2 
approximately determined as
VBB .
PROBLEM

1. A UJT is used to trigger the thyristor whose minimum gate triggering voltage is 6.2V, The UJT
I  0.5mA I v  3mA RB1  RB 2  5k 
ratings are:   0.66 , p , , , leakage current = 3.2mA,
V p  14v Vv  1V . Oscillator frequency is 2kHz and capacitor C = 0.04F. Design the
and
complete circuit.

Solution

 1 
T  RC C ln  
1   

Here,

1 1
T 
f 2  103 , since f  2kHz and putting other values,

1  1 
 RC  0.04 106 ln    11.6k 
2 10 3
 1  0.66 

V p  VBB  VD
The peak voltage is given as,

Let
VD  0.8 , then putting other values,

14  0.66VBB  0.8

VBB  20V

The value of
R2 is given by

0.7  RB 2  RB1 
R2 
VBB

0.7  5 103 
R2 
0.66  20

 R2  265
 Value of
R1 can be calculated by the equation

VBB  I leakage  R1  R2  RB1  RB 2 

20  3.2 103  R1  265  5000 

R1  985

Rc max 
The value of is given by equation

VBB  V p
Rc max  
Ip

20  14
Rc max  
0.5  103

Rc max   12k 

Rc min 
Similarly the value of is given by equation

VBB  Vv
Rc min  
Iv

20  1
Rc min  
3 103

Rc min   6.33k 

2. Design the UJT triggering circuit for SCR. Given

VBB  20V ,   0.6 , I p  10 A , Vv  2V ,
I v  10mA . The frequency of oscillation is 100Hz. The triggering pulse width should be 50  s .

Solution

1 1
T 
The frequency f = 100Hz, Therefore f 100

 1 
T  Rc C ln  
From equation  1 
Putting values in above equation,

1  1 
 Rc C ln  
100  1  0.6 

 Rc C  0.0109135

Let us select C  1 F . Then c will be,

R

0.0109135
Rc min  
1 106

Rc min   10.91k 

.

The peak voltage is given as,

V p  VBB  VD

Let
VD  0.8 and putting other values,

V p  0.6  20  0.8  12.8V

The minimum value of

Rc can be calculated from

VBB  Vv
Rc min  
Iv

20  2
Rc min    1.8k 
10  103

Value of
R2 can be calculated from

104
R2 
VBB

104
R2   833.33
0.6  20

Here the pulse width is give, that is 50s.

 Hence, value of
R1 will be,

 2  R1C

The width
 2  50 sec and C  1 F , hence above equation becomes,

50 10 6  R1 1106

 R1  50

Thus we obtained the values of components in UJT triggering circuit as,

R1  50 , R2  833.33 , Rc  10.91k  , C  1 F .

SYNCHRONIZED UJT OSCILLATOR

A synchronized UJT triggering circuit is as shown in figure below. The diodes rectify the input ac to dc,

resistor
Rd lowers Vdc to a suitable value for the zener diode and UJT. The zener diode ‘Z’ functions to
V
clip the rectified voltage to a standard level Z which remains constant except near dc
V  0 . This
V
voltage Z is applied to the charging RC circuit. The capacitor ‘C’ charges at a rate determined by the RC
V
time constant. When the capacitor reaches the peak point P the UJT starts conducting and capacitor
discharges through the primary of the pulse transformer. As the current through the primary is in the
from of a pulse the secondary windings have pulse voltages at the output. The pulses at the two
V
secondaries feed SCRs in phase. As the zener voltage Z goes to zero at the end of each half cycle the
synchronization of the trigger circuit with the supply voltage across the SCRs is archived, small variations
in supply voltage and frequency are not going to effect the circuit operation. In case the resistor ‘R’ is
reduced so that the capacitor voltage reaches UJT threshold voltage twice in each half cycle there will be
two pulses in each half cycle with one pulse becoming redundant.
Fig.:
R 1

+ +

i1 R R 2
D1 D3
B 2
P u ls e T r a n s f
+ E
V dc Z V Z
B 1 G 1

C To S C R
v C 1
c G a te s
G 2
D4 D2
C 2
- - -
Synchronized UJT trigger circuit

Fig.:
Generation
of
vc, output
vdc VZ Vdc pulses for
the

VZ

vc vc vc t
P u ls e
V o lta g e
1 2 1 2 1 2

  t
 

synchronized UJT trigger circuit