 The term thyristor denotes a family of semiconductor devices used

for power control in ac and dc systems.

 These semiconductor devices are silicon controlled rectifier (SCR),
Gate turn off thyristor (GTO), DIAC, TRIAC, programmable
unijunction thyristor (PUT), Reverse conducting Thyristor (RCT) etc.
 Oldest member of this family called silicon controlled rectifier (SCR),
is the mostly used device.

 SCR is minority carrier device.

 SCR is semi controlled device i.e. controlled turn on and
uncontrolled turn off.
 These devices are used for high power and low frequency
applications. These devices are available with 8000V and 4000A
ratings
P+ layer
Doping density-1017cm-3
Thickness: 30-50μm

N- layer
Doping density-1013 – 5*1014cm-3
Thickness: 50-1000μm

P+ layer
Doping density-1017cm-3
Thickness: 30-100μm

N+ layer
Doping density-1019cm-3
Thickness: 10μm

A complete silicon wafer as large as 10cm in

diameter may be used to make a single high
power thyristor. It is minority carrier device.
Compare to BJT it have low on-state conduction
losses and high power handling capability.
 Due to low doping level, the depletion layer width become wider and
provides high forward current and high reverse blocking capability.

 The turn off time and on state devices losses are increased with the
width of N1 of the device. Hence switching speed of the device is
reduced with increasing the width of N1 of the SCR.

 For high speed SCR, the width of N1 layer is reduced and the impurity
density of N1 layer must be increased. But the reverse blocking
capability gets reduced.
 It is four layer PNPN switching
device, having three junction
J1, J2 and J3.
 It has three terminals Anode
(A), cathode(C) and Gate(G).
 Anode and cathode are
connected to the main power
circuit.
 Gate is used to turn on
thyristor and carry gate
current in direction of Gate to
cathode.
P1+, N1-,P2+, N2+

N2-Thin layer highly doped

P2-Slightly thicker, doping level is low
N1-thickest among all four layer, doping level
is minimum
P1-Same as P2
Reverse voltage blocked by junction J3 is very small
because of high doping level, almost all reverse
voltage is blocked by Junction J1.
VI Characteristic is divided into three parts
(1) Reverse blocking region:-

 When cathode (K) is made +ive wrt anode.

 J1 and J3 (outer junctions) are reversed biased and j2 is
forward biased. Therefore only a small leakage current
(mA) flows.

 If the reverse voltage is increased, then at a critical

breakdown level called reverse break down voltage (VBR),
an avalanche will occur at j1 and j3, increasing current
sharply.

 If this current is not limited to safe value, power

dissipation will increase to a dangerous level that may
destroy device.
(2) Forward blocking region

 Anode is made +ive wrt cathode.

 J1 and J3 are forward biased and j2 remains
reversed biased.
 Anode current is a small forward leakage
current.
 In VI characteristic OM region is known as the
forward blocking region, when device does
not conduct.
(3) Forward conduction region

 When forward voltage is increased with the gate circuit kept open,
avalanche breakdown occurs at the junction j2 at a critical forward
break over voltage (VBO) and the SCR switches into a low impedance
condition (high condition mode).

 The inner two regions of the SCR are lightly doped compared to the
outer layers.

 Hence, the thickness of the J2 depletion layer during the forward

biased conditions will be greater than the total thickness of the two
depletion layers at J1 and J3 when the device is reversed biased.

 Therefore the forward break over voltage VBO is generally higher

than the reverse break over voltage VBR.
When gate signal is applied:

 When gate signal is applied, the thyristor turn on before

VBO is reached.
 The forward voltage at which the device switches to ON
state depends upon the magnitude of gate current.
 Higher the gate current lower is the forward break over
voltage.
 The typical IG ->20 to 200mA.
Latching current: minimum value of anode current which
SCR must attain during turn on process to maintain
conduction when gate signal is removed.

Holding Current: Minimum value of anode current below

which it must fall for turning off thyristor. Typically it is
10mA.

Note: latching current is associated with turn-on process

and holding current with turn off process.

The holding current is usually lower than, but very close

to the latching current.
 The principle of Thyristor operation can be explained with the
use of its two-transistor model.
 In this model Junction J1-J2 and J2-J3 can be considered to
constitute pnp and npn transistor separately.
 In the off-state of a transistor, collector current Ic is related to
emitter current IE as,

 where α is the common-base current gain and ICBO is the

common-base leakage current of collector-base junction of a
transistor.
 For transistor Q1, emitter current IE=anode current Ia and
Ic=collector current Ic1
 Similarly for transistor Q2, the collector current Ic2 is given by,

 The sum of two collector currents given by Ic1 and Ic2 is equal
to the external circuit current Ia entering at anode terminal A
 When gate current is applied, then Ik=Ia+Ig. Therefore,

 For a silicon transistor, current gain α is very low at low

emitter current. With increase in emitter current, α build up
rapidly as shown in graph
 If by some means the emitter current of two
component transistor can be increased so that
α1+α2 approach unity. Then Ia tends to infinity
thereby turning on the device.

 Ia is limited by load current to power circuitry.

 The method of turning on a thyristor in fact are the

methods of making α1+α2->unity.
 If by some means the emitter current of two
component transistor can be increased so
that α1+α2 approach unity. Then Ia tends to
infinity thereby turning on the device.
 Ia is limited by load current to power circuitry.
 The method of turning on a thyristor in fact
are the methods of making α1+α2->unity.
1. Forward voltage triggering
2. Gate triggering
3. Temperature triggering
4. dv/dt triggering
5. Light triggering
 Forward voltage triggering:
• When anode and cathode forward voltage is increased with
gate circuit open, the reverse bias junction J2 will break.

• This is known as avalanche breakdown and the voltage at

which avalanche occurs is called forward break over
voltage(VBO).

• As junctions J1 and J3 are already forward biased, breakdown

of j2 allows free movement of charge carrier.

• This results turn on of SCR and large forward anode current,

which is limited by the load impedance.

• The forward voltage drop across the SCR during the ON state
is of the order of 1 to 1.5V and increase slightly with the load
current.
 Gate triggering:

• When +ive gate current is applied, gate P layer is

flooded with electrons from the cathode. This is
because cathode N layer is heavily doped as compared
to P layer.
• As the thyristor is forward biased some of these
electrons reach junction j2. As a result width of
depletion layer around junction is reduced.
• This causes the junction j2 breakdown at an applied
voltage lower than forward break over voltage (VBO).

•
Temperature triggering:

 If the temperature of a thyristor is high, there is an increase

in the number of electron-hole pairs, which increases the
leakage currents (ICBO).

 ICBO increase temp of J2 increase further ICBO increase and

temp increases.

 This increase in current causes α1 and α2 to increase . Due

to the regenerative action, (α1+ α2) may tend to be unity and
thyristor may be turned on.

 This type of turn on may cause thermal runway and is

normally avoided.
 Temperature triggering:

• During forward blocking most of the applied voltage appears

across reverse biased junction J2. This voltage across J2
associated with leakage current may rise the temperature of
the junction.
• ICBO increase temp of J2 increase further ICBO increase and
temp increases. This cumulative process may turn on the SCR
at some specified temperature.
High dv/dt triggering

 We know that with forward biased voltage across the

anode and cathode of a device, the junctions j1 and j2
are forward biased and j2 is reversed biased.
 This reversed biased junction j2 has the characteristics
of a capacitor due to charge existing across the
junction.
 If the voltage denoted by V, charge by Q and the
capacitance by Cj,
𝑑𝑄 𝑑 𝑑𝑉 𝑑𝐶𝑗
Charging current 𝑖𝑐 = = 𝐶𝑗𝑉 = 𝐶𝑗 +𝑉
𝑑𝑡 𝑑𝑡 𝑑𝑡 𝑑𝑡
 The rate of change in junction capacitance is negligible
as it is almost constant.
 Hence,
𝑑𝑉
𝑖𝑐 = 𝐶𝑗
𝑑𝑡

 Therefore, if the rate of change of voltage across the device is

large the charging current increase which flows through J2
just like the gate current is supplied from gate terminal.

 The device may get turn on even through the voltage

appearing across the device is small.
 Turn on time of SCR is subdivided into three distinct periods
(1) Delay time (td) (2) rise time (tr) (3) spread time (ts)
 When thyristor is forward biased and a positive gate pulse is
applied between the gate and cathode, it will be turned ON.
 But there is finite transition time to switch from forward OFF-
state to forward ON-state for a thyristor.
 This finite transition time is known as turn-ON time.

 The total turn on time (ton) is divided into three distinct

periods, called the delay time, rise time and spread time.
ton=td + tr + ts
Delay time:
 This is the time instant at which the gate current reaches 90%
of its final value and the instant at which the anode current
reaches 10% of its final value.
 It can also be defined as the time during which anode voltage
falls from Va to 0.9Va, where Va is the initial value of the
anode voltage.

Rise time :
 This is the time required for the anode current to rise from 10
to 90% of its final value.
 It can also be defined as the time required for the forward
blocking off-state voltage to fall from 0.9 to 0.1of its initial
value-OP.
 This can also be measured from the instant of the gate
current reaches 0.9Ig to the instant at which gate current Ig.
Where Ig is the final value of gate current.
 This time is inversely proportional to the magnitude of gate
current and its build up rate. Thus tr can be minimized if high
and steep current pulses are applied to the gate.
 The value of tr depends the nature of anode circuit (R-L and
R-C). In series R-L circuit, the rate of rise of anode current is
slow due to presence of inductance L and rise time is more. In
case of R-C rate of rise of anode current is high and rise time
is less.
 During rise time turn-on losses are the highest due to high
anode voltage Va and large anode current IT occuring
together in the SCR.
Spread time:
 Spread time is time required for the forward blocking voltage
to fall from 0.1 to its value to the on-state voltage drop (1 to
1.5V).
 After the spread time, anode current attains steady-state
values and the voltage drop across SCR is equal to the on-
state voltage drop of the order of 1 to 1.5V.

 Once SCR starts conducting an appreciable forward current, the
gate has no control over it and the device can be brought back to
the blocking state only by reducing the forward current to a level
below that of the holding current.

 The turn off process of thyristor is called commutation.

 The turn off time of a SCR tq can be defined as the time interval
between the instant at which anode current through the device
become zero and the instant at which SCR regain its forward
blocking capability.

 It the sum of the reverse recovery time trr and gate recovery time
tgr

toff=trr+tgr
 Reverse recovery time (trr)

 At time t1 the anode current become zero. After t1 anode current

start build up in the reverse direction due to presence of charge
carriers in the four layers of SCR.

 The reverse recovery current removes excess charge carriers from

junction j1 and j3 during t1 and t3. consequently holes are sweeping
out from top P layer and electron from bottom n-layer.

 At t2 about 60% of stored charge carriers are removed from outer

two layers. As a result carrier density in junctions J1 and j3
decreases and subsequently the reverse recovery current also
decreases.
Gate recovery time tgr

 At time t3 the reverse recovery current become very small and

thyristor is able to block the reverse voltage.
 During t1 to t3 all excess charge carriers are removed from J1
and J3.

 At t3 the middle junction j2 still consists of charge carriers

and it can not able to block forward voltage.

 Charge carriers at j2 are not able to flow to the external

circuit. These carriers can be removed by recombination only.

 The recombination is possible when a reverse voltage is

applied across SCR for specified time. The recombination of
charge carriers takes place between t3 to t4. this time is called
gate recovery time. At t4 SCR is in OFF state.
 In practical application, the turn off time required to the SCR
by the circuit, called the circuit turn off time tq, must be
greater than the device turn off time toff by suitable safe
margin, otherwise the device will turn on at an undesired
instant a process is known as commutation failure.
 Turn off time vary in the range 10 to 100μs.
 Thyristor having large turn off time (50-100 μs) are called
slow switching or phase control type thyristors (or converter
grade thyristor).
 Those having low turn off time (10-50μs) are called fast
switching or inverter grade thyristor, used for high frequency
applications.

 This is simplest and most economical.
 Suffers from a limited range of firing angle control (0 to 90
degree), great dependence on temperature and difference in
performance between individual SCRs.
 R2 is variable resistance, R is the stabilizing resistance.
 Relationship between vgp and vgt
 vgpsin α= vgt or 𝛼 = sin−1 vgt v
gp

𝑉𝑚×𝑅
 Since 𝑉𝑔𝑝 =
𝑅1+𝑅2+𝑅

𝑉𝑔𝑡×(𝑅1+𝑅2+𝑅)
 𝛼 = sin−1
𝑉𝑚×𝑅
 Anode voltage ratings
 Current ratings
 Power ratings
RC Half wave trigger circuit
 In the negative half cycle, capacitor charges through diode D2
with lower plate positive to the peak supply voltage –Vm.
 After -π/2, source voltage decrease from –Vm to zero at 0°.
During this time capacitor voltage Vc may fall from –Vm to
some lower value –oa.
 Now as the SCR anode voltage passes through zero and
become positive, capacitor C begins to charge through R from
initial voltage –Vm.
 When the capacitor charge to positive
voltage equal to gate trigger
voltage Vgt SCR is triggered and
after this the capacitor holds to
a small positive voltage.
 Diode D1 is used to prevent the breakdown of cathode to gate
junction during negative half cycle.
 In the range of power frequencies the RC for zero output
voltage is given by
RC≥1.3T/2=4/ω (1)
Where T=1/f=period of ac frequency in seconds.
 The SCR will trigger when vc=Vgt+vd where vd is the voltage
drop across diode D1.
 At the time of triggering (vs- source voltage at which thyristor
turns on)

(2)
 Approximate values of R and C can be obtained from eq (1)
and (2)
 RC Full Wave Trigger circuit
 A UJT is a three terminal semiconductor device (E, B1 and B2).
 It is formed from a lightly doped slab of n-type material which has
high resistance.
 The two base contacts are made at each end of one side of the slab
and aluminium rod is inserted on the other side to form a single p-n
junction.
 The aluminium rod is located ne to the base B2.
 Since the emitter is closer to B2, the value of RB1 is greater than RB2.
(typically RB1 4.2kΩ and RB2 2.8kΩ).
 Figure shows equivalent circuit of UJT. The diode represents the p-n
junction, RB1 is a variable resistance and RB2 is a fixed resistance.
 The value of RB1 decrease when emitter current increase.

 The inner base resistance between B1 and B2 is expressed as,

RBB=RB1+RB2
it is between 4kΩ to 10kΩ.
When IE=0, the voltage across RB1 is,

𝑹𝑩𝟏
𝑽𝑹𝑩𝟏 = 𝑽 = 𝜼𝑽𝑩𝑩
𝑹𝑩𝟏 + 𝑹𝑩𝟐 𝑩𝑩

Where is 𝜂 is intrinsic stand off ratio.

This is controlled by location
of aluminium rod.
The emitter threshold potential is
𝑽𝒑 = 𝜼𝑽𝑩𝑩 + 𝑽𝑫
 The V-I characteristics are shown in Figure represents, when VE
crosses the threshold potential Vp the emitter fires and holes are
injected into the n-type slab through the p type rod (or p-type
layer).
 At this moment holes content of n-type slab increases and the
number of free electron also increases. Hence conductivity
increases.
 Thus VE drop off while increasing IE and UJT operates in the negative
resistance region.
 The characteristics passes through valley point (IV, VV) and then
become saturate. (2-25Ω)
 The UJT relaxation oscillator is used as a triggered device for SCRs
and TRIACs.
 Let us consider initially that capacitor is at zero Voltas (Vc=0) and
the switch is suddenly closed at t=0 applying Edc to the circuit.
 Initially VE=Vc=0, UJT emitter diode is reverse biased and the UJT is
off. The amount of reverse bias is Vx Volt given as,

𝑅1 + 𝑅𝐵1 𝐸𝑑𝑐
𝑉𝑥 =
𝑅1 + 𝑅𝐵1 + 𝑅2 + 𝑅𝐵2

 In cases where R1 and R2 are much smaller than RB1 and RB2, and Vx
become equal to 𝜂Edc.
 in this condition the only emitter current flowing will be small
reverse leakage IE0. resistance RB1 will be at its OFF value (typically
4kΩ).
 As switch is closed at t=0, the capacitor begin to charge towards the
input voltage Edc through resistor R. the capacitor voltage increases
with time constant of RC, it will continue to increase until the voltage
at the emitter increase the peak point voltage Vp (= 𝜼𝑽𝑩𝑩 + 𝑽𝑫 ).

 At this time emitter diode become forward biased and UJT turn ON
with RB1 dropping to a very low value typically 10Ω.

 Since the diode is now forward biased, the capacitor will discharge
through the low-resistance path containing the diode, RB1 and R1.

 The discharge time of capacitor is very short as compared to charging

time.

 An analytical expression for the discharge time constant is difficult to

obtain since RB1 will continually change as the current IE decrease.
 The discharging capacitor provides the emitter current needed to
keep the UJT ON, it will remain ON until IE drops below the valley
point current Iv. At which UJT turn OFF.
 This occurs at time T2 when the capacitor voltage has dropped to
the valley voltage Vv (typically 2-3V).
 At this time RB1 returns to its high value, the diode is reverse biased
and IE=0.
 To calculate frequency of this waveform, first calculate the period of
one cycle. The length of one period , T1, is essentially the time it
takes for the capacitor to charge to Vp since the discharge time T2 is
usually relatively short. T=T1 and is given by,
 Varying the frequency
The frequency of oscillation is normally controlled by varying the charging
time constant RC. There are however, limit on R.
These limits are:

Rmin=(Edc-Vv)/Iv
Rmax=(Edc-Vp)/Ip
 For proper reliable operation, thyristor must be operating within the
specified voltage and current ratings.
 But in some applications, thyristors may be subject to over voltage
and over current.
 Due to over voltage and over current, the junction temperature my
exceed the maximum allowable temperature 150°C and device may
damaged permanently.
 For normal operation of thyristor in different converter circuits, the
following protections should be taken care:
1. di/dt protection
2. dv/dt protection
3. Over-voltage protection
4. Over-current protection
5. Gate protection
di/dt protection
 If rate of rise of anode current i.e. di/dt is large as compered to the
spread velocity of carriers, local hot spot will be formed near the
gate connection on account of high current density.
 This localized heat may destroy the thyristor.
 Therefore rate of rise of anode current at the time of turn on must
keep below the specified limiting value.
 The value of di/dt can be maintained below acceptable limit by
using a small inductor, called di/dt inductor, in series with the
anode circuit.
 Typical di/dt limit values of SCR are 20-500A/μs
dv/dt protection:
 With the forward voltage across the anode and cathode of a
thyristor, the two outer junctions (J1 and J3) are forward biased and
inner (J2) junction is reversed biased.
 J2 has the characteristic of capacitor due to charges existing across
tha junction.
 If rate of rise of forward voltage dV/dt is high, the charging current i
will be more. This charging current plays the role of gate current
and turns on the SCR even when gate signal is not applied.
 Such phenomena of turning on thyristor called dv/dt and it must be
avoided as it leads to false operation of thyristor circuit.
 For controllable operation of the thyristor, the rate of rise of forward
anode to cathode voltage dV/dt must be kept below the specified
rated limit.
 Typical values of dv/dt are 20-500V/μs.
 This can be avoided by placing R-C snubber circuit in parallel with
the device.

 Series Connected Thyristors
 If required voltage rating of the assembly or
equipment incorporating thyristors is more than
the voltage rating of a thyristor, then several
thyristors needs to be connected in series
connection.

 These thyristor must be of same class.

 Like any other semiconductor device characteristics
of two thyristors of the same make and rating are
never same and this leads to the following two
major problems:
1. Unequal distribution of voltage across devices.
2. Difference in reverse recovery characteristics.
Unequal distribution of voltage
 VBO1 and VBO2 are the forward
voltages of T1 and T2.
 For T2, leakage resistance=V2/I0
and for T1 leakage
resistance(=V1/I0) is low.
 For same leakage current T2
support rated voltage V2 and T1
Support leakage voltage V1 which is
less compared to V2.
 Hence thyristor having highest
leakage resistance will share a
larger portion of the applied
voltage. Cause unequal
distribution of voltage across T1
and T2 in steady state.
 The max voltage that two SCR
string can block is V1+V2 and the
rated blocking voltage 2V2.
 The string efficiency for series connected thyristor

𝑉1 + 𝑉2 1 𝑉2
= 1+
2𝑉1 2 𝑉1
 A uniform voltage distribution in steady state can be achieved by
connecting a suitable resistance across each SCR such that each
parallel combination has the same resistance. This require different
value of resistance, which is difficult proposition.

 A more practical way is to use same value of shunt resistance (R).

The shunt resistance R is called the static equalizing circuit.
 𝑅 = 𝑛𝑉𝑏𝑚 −𝑉𝑠 𝑛𝑠 −1 ∆𝐼𝑏
 n->no. of SCR connected in series
 Let SCR1 has minimum leakage current->Ibmn and remaining have
same leakage current Ibmx>Ibmn. SCR with lower leakage blocks more
voltage
 SCR data sheet contain only maximum blocking
current Ibmx and rarely have ΔIb. In such case it is
usual to assume ΔIb= Ibmx.

 Power rating PR=Vr2/R,

 Vr RMS voltage across R
 It is likely that SCRs do not have identical dynamic
characteristics.
 In such case, series connected SCRs will have unequal voltage
distribution during the transient conditions of turn on/off and
high frequency operation.
 The dynamic characteristics of two SCR during turn and turn
off is shown in figure, where it is considered that turn-on
time of SCR2 is more than that of SCR1 by Δtd.
 String voltage Vs is shared as Vs/2 by each thyristor.
 Now both SCRs are gated at same time. As SCR1 has less turn
on time, it gets turn on at time t1, whereas SCR2 is turn off
yet.
 Voltage across SCR2 drops from Vs/2 to almost zero. At the
same time instant t1, voltage across SCR2 will boost from
Vs/2 to almost full Vs. thus voltage share by two SCRs are
unequal.
 During turn on and off the
capacitance of the reversed biased
junction determines voltage
distribution across SCRs is a series
connected strings.
 Reversed biased junction have
different self capacitance values,
therefore voltage distribution will
be different.
 By employing shunt capacitance
voltage equalization can be
achieved. During turn on and off
resultant of shunt capacitance and
self capacitance of each SCR tends
to be same. This equalize the
voltage.
 When SCR is in forward blocking state the capacitor
connected across gets charged.

 When SCR is turned on, capacitor discharge heavy

current through it. For limiting this discharge current
spike a damping resistor RC is used in series with the
capacitor.
 Function of RC-C is to equalize voltage during
dynamic condition and to protect SCR against dv/dt.
Combination of Rc and C is called the dynamic
equalizing circuit.

 A diode D is also placed across Rc. This bypass Rc

when forward voltage appears during charging time
of C. This makes capacitor more effective in voltage
equalization and for limiting dv/dt.
 𝑛−1 ∆𝑄𝑚𝑎𝑥
 𝐶= 𝑛𝑉𝑏𝑚 −𝑉𝑠

 ∆𝑄𝑚𝑎𝑥 ->maximum permissible difference

between reverse recovery charge of SCRs
 Maximum difference in voltage
 Emax= ∆𝑄𝑚𝑎𝑥 /C
 The need of parallel connected thyristor arises when current
or over current is to be handled by the apparatus exceeds the
rating of a single thyristor.
 Thyristors can be connected in parallel if the have identical
forward V-I characteristics. Practically it is not possible.
 Total load current of parallel
Unit is I1+I2, instead of 2I2.
 The unequal distribution of current in parallel
connected thyristor may also lead to thermal
runway problem.
 Therefore all SCRs must operate at same
temperature when used in parallel. This is done by
common heat sink.
 In dc circuits a series resistor may be
added to each arm of the parallel
arrangement to improve the sharing of
current.
 R1 and R2 are chosen in such way that
voltage drop are equal
R1+RT1=R2+RT2
 RT1 and RT2 are corresponding dynamic
resistances of T1 and T2.
 In parallel R1=R2=R

VT1+IT1(R+RT1)=VT2+IT2(R+RT2)

For ac circuits reactors can be used.

 If current IT1 and IT2 are equal,
then the voltage drop in the
reactor will be zero because of
the mutual cancellation of flux
linkage in the coil.

 If IT1>IT2, a counter emf will be

induced proportional to the
unbalanced current and tend to
reduce current through SCR T1.

 At the same time, a boosting

voltage is induced in series with
the SCR T2, increasing the
current flow through the SCR T2.
 For reliable operation of a thyristor, it should be ensured that its current and
voltage ratings are not exceeded during its working.
 One of the major disadvantage with thyristor is that it has low thermal time
constant. If it handle voltage, current and power above specified limit, the
junction temperature may increase and thyristor may get damaged.

Voltage ratings
1. Peak working forward blocking (VDWM): it specifies the maximum forward
blocking voltage that a thyristor can withstand during its working.
2. Peak repetitive forward blocking voltage (VDRM): it refers peak transient
voltage that a thyristor can withstand repeatedly in its forward blocking
mode.
3. Peak surge (or non-repetitive) forward blocking voltage (VDSM)