B-PRO 8700 Function Logic Diagram

v3.1 sheet 1 of 1
50LS-1 I1a
50LS-1 I1b 100 Logic Gate Switch
50LS-1 I1c T
50LS-1 Input 1 HIGH
0

101

50LS-2 I1a
50LS-2 I1b 102 Logic Gate Switch
0
50LS-2 I1c T
50LS-2 Input 1 HIGH 100ms
0
0
103
100ms
50LS Input 1 Low Set Overcurrent 0
50 I1a (phase current supervision 4% of nominal CT rating) 100ms

50 I1b 104 0
50 I1c 100ms

0
T1
Input 1 50 Trip 50BF-1 Input 1 TRIP 100ms
0
Input 1 51 Trip

OUTPUT RELAY 1-14

0
Input 1 50N Trip
50BF Input 1 Enabled 106 100ms
Input 1 51N Trip
Input 1 46-50 Trip 0
Input 1 46-51 Trip
87B-1 Trip
87B-2 Trip
105 Breaker Failure Initiator
T2
0
50BF-2 Input 1 TRIP
0
100ms

100ms
87T Trip
ProLogic 1-15 0
External Input 1-9 100ms
50BF Input 1 Breaker Failure
0
50 Input 1 Directional Element T T = 10ms or setting, whichever is greater, if 50 is directional 100ms
107 50 Input 1 TRIP
0
I1a 0
Select Maximum Imax > 50 Pickup Level 10ms Timer on alarm pickup delay active only if 51 is directional.
Phase Current for 51 Input 1 ALARM 100ms
I1b 0
50 Element
Imax > 51 Pickup Level 0
I1c 51 Element
108 51 Input 1 TRIP 100ms
51 Input 1 Directional Element
50/51 Input 1 Over Current 0
100ms
50N Input 1 Directional Element T T = 10ms or setting, whichever is greater, if 50N is directional
0
109 50N Input 1 TRIP
0
I1a 100ms
Calculate 3I0 for 3I0 > 50N Pickup Level 10ms Timer on alarm pickup delay active only if 51N is directional.
I1b 50N Element 51N Input 1 ALARM
0
51N Element 3I0 > 51N Pickup Level
I1c
110 51N Input 1 TRIP
51N Input 1 Directional Element
50N/51N Input 1 Neutral Over Current
46-50 Input 1 Directional Element T T = 10ms or setting, whichever is greater, if 46-50 is directional
109 46-50 Input 1 TRIP
0
I1a
Calculate I2 for I2 > 46-50 Pickup Level 10ms Timer on alarm pickup delay active only if 46-51 is directional.
I1b 46-50 Element 46-51 Input 1 ALARM
0
46-51 Element I2 > 46-51 Pickup Level
I1c
110 46-51 Input 1 TRIP FAULT
46-51 Input 1 Directional Element RECORDER
46-50/46-51 Input 1 Negative Sequence Over Current User - Configurable
119 OUTPUT MATRIX
50 Non-Directional 50 Forward
113 131 50 Input 1 Directional Element
50 Reverse
120

121
51 Non-Directional 51 Forward SWING
114 132 51 Input 1 Directional Element RECORDER
51 Reverse
122
111
Output of Directional Element
is logical 1 when Forward and 123
logical 0 when Reverse 50N Non-Directional 50N Forward
115 133 50N Input 1 Directional Element
50N Reverse
Vpos Memory FORWARD 124
ILpos Input 1
Alpha
Beta REVERSE 125
51N Non-Directional 51N Forward
116 134 51N Input 1 Directional Element
51N Reverse
126
59 Vpos (2 volts RMS fixed) 112
50 ILpos Input 1 (4% Inominal RMS fixed) 127
46-50 Non-Directional 46-50 Forward
117 135 46-50 Input 1 Directional Element
46-50 Reverse
128

129
46-51 Non-Directional 46-51 Forward
118 136 46-51 Input 1 Directional Element
46-51 Reverse
130
Input 1 Directional Element
50LS-1 Inputs 2-6 HIGH
Function Block for Inputs 2-6 50LS-2 Inputs 2-6 HIGH
Same functions as Input 1
50BF-1 Inputs 2-6 TRIP
Va
50BF-2 Inputs 2-6 TRIP
Vb (1) 50LS-1 O/C
50 Inputs 2-6 TRIP
Vc (2) 50LS-2 O/C
51 Inputs 2-6 ALARM
(3) 50BF 51 Inputs 2-6 TRIP

I2a - I6a (4) 50/51 50N Inputs 2-6 TRIP

(5) 50N/51N 51N Inputs 2-6 ALARM

I2b - I6b
51N Inputs 2-6 TRIP
I2c - I6c (6) 46-50/46-51
46-50 Inputs 2-6 TRIP
(7) Directional Element
46-51 Inputs 2-6 ALARM

Input Functions (2 to 6) 46-51 Inputs 2-6 TRIP

IOA = I 5 a + I 6 a
IOB = I 5 b + I 6 b
IOC = I 5 c + I 6 c

I5a Wye / Delta

CT Ratio Mismatch
IOA IOB IOC
I5b Correction Input 5 &
3I0 Elimination
I5c
2nd Harmonic Restraint IO 2nd and 5th Harmonic Restraint
Trip A

87T Trip B 137 87T TRIP

Trip C

5th Harmonic Restraint IR

I6a
Wye / Delta
I6b CT Ratio Mismatch
Correction Input 6 &
I6c 3I0 Elimination IRA IRB IRC
Delta Phase and
IRA = (I 5 a + I 6 a ) 2 ROCOD Supervision
IRB = (I 5 b + I 6 b ) 2
IRC = (I 5 c + I 6 c ) 2
87T Transformer Differential

IOA = ∑ I ia

I1a CT Ratio Mismatch IOB = ∑ I ib

Correction Input 1 IOC = ∑ I ic

I1b Vector sum of all inputs

I1c
Set input for Bus1, connected to Bus1 IOA IOB IOC
Bus2 or NC (rec.)

IO External Fault CT Saturation Detector

I2a CT Ratio Mismatch

87B-1 Trip A
Correction Input 2
I2b (Bus1) Trip B 138 87B-1 TRIP
Set input for Bus1,
I2c Bus2 or NC (rec.) Note: Any current input
can be used in either Trip C
87B-1 or 87B-2
IR

I3a CT Ratio Mismatch

Correction Input 3 Magnitude sum / 2 of
all inputs connected
I3b to Bus1 IRA IRB IRC CT Saturation Delta Phase and
Set input for Bus1, and Harmonic ROCOD Supervision
I3c Bus2 or NC (rec.) IRA = ∑ I ia 2 Restraint
IRB = ∑ I ib 2

IRC = ∑ I ic 2

IOA = ∑ I ia
IOB = ∑ I ib

CT Ratio Mismatch
IOC = ∑ I ic
I4a
Correction Input 4 Vector sum of all inputs
connected to Bus2
I4b IOA IOB IOC
Set input for Bus1,
I4c Bus2 or NC (rec.)

IO External Fault CT Saturation Detector

87B-2 Trip A

I5a CT Ratio Mismatch

Correction Input 5 (Bus2) Trip B 139 87B-2 TRIP
I5b Note: Any current input
Set input for Bus1, can be used in either
I5c Bus2 or NC (rec.) 87B-1 or 87B-2 Trip C
IR

Magnitude sum / 2 of
I6a CT Ratio Mismatch all inputs connected Note: 87B1 and 87B2 bus protections also include the summation of zero sequence currents from the inputs in the similar fasion to the phase current shown in here
Correction Input 6 to Bus2 IRA IRB IRC CT Saturation Delta Phase and
I6b and Harmonic ROCOD Supervision
IRA = ∑ I ia 2 Restraint These functions are supervised by the zero sequence delta phase measurement
Set input for Bus1,
I6c Bus2 or NC (rec.) IRB = ∑ I ib 2

IRC = ∑ I ic 2
87B-1 and 87B-2 Bus Differential
59-1 Va
59-1 Vb 140 Logic Gate Switch
59-1 Vc T
59-1 TRIP
0

141

59-2 Va
59-2 Vb 142 Logic Gate Switch
59-2 Vc T
59-2 TRIP
0

143

59 Over Voltage
27-1 Va
27-1 Vb 144 Logic Gate Switch
27-1 Vc T
27-1 TRIP
0

145

27-2 Va
27-2 Vb 146 Logic Gate Switch
27-2 Vc T
27-2 TRIP
0

147

27 Under Voltage
59VA (fixed 0.5 pu)
59VB (fixed 0.5 pu) 148
59VC (fixed 0.5 pu)
10s
150 60 LOP ALARM
0

149
60 Loss of Potential Alarm
81O-1 Frequency
T
200ms 151 81O-1 TRIP
0
Vpos > 0.25 pu (or 5V) 0

81O-2 Frequency
T
200ms 152 81O-2 TRIP
0
Vpos > 0.25 pu (or 5V) 0
81 Over Frequency
81U-1 Frequency
T
200ms 153 81U-1 TRIP
0
Vpos > 0.25 pu (or 5V) 0

81U-2 Frequency
T
200ms 154 81U-2 TRIP
0
81 Under Frequency Vpos > 0.25 pu (or 5V) 0

Self Check Fail

Prologic 1 to 15

External Input 1 to 9

Alarms, ProLogic, Virtual Inputs

Virtual Input 1 to 30
and External Inputs
NOTE: All functions use the extracted fundamental component of the analog inputs.

Revision Date Description of Revision By TITLE:

7 - - -
6 - - B-PRO 8700 FUNCTION LOGIC DIAGRAM
-
5
4
2011/05/11
2010/07/20
Updated for B-PRO 8700 v3.1 Firmware
Updated for B-PRO 8700 v2.3 Firmware
SP
NZ ERL PHASE
Power Technologies Ltd.
Document Identifier Document Revision Page Identifier drawing has

1
3
2
2009/11/24
2008/06/27
Updated for B-PRO 8700 v2.2 Firmware
Modified title block
SP
SP
DSN BY: D. Fedirchuk
M. Poole DATE: 2011-05-01 D02242 R03.10 P1 sheet(s)
1 2004/07/15 Updated for B-PRO 8700 v2.0 Firmware PAG INPUT FILENAME: D02242R03.10.SKF Firmware Version: v3.1
DWN BY: S. Phat DATE: 2011-05-01 PRODUCT NUMBER: 109476 Rev 1.00
0 2002/07/18 Initial Version DSO AUTOSKETCH V8