See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/320436216

New Modified Current Starved Ring Voltage Controlled Oscillator and

Frequency to Voltage Rectifier for Noise Suppression from 1 – 6 GHz in 180 nm
Technology

Article  in  Procedia Computer Science · October 2017

DOI: 10.1016/j.procs.2017.09.170

CITATIONS READS

2 165

2 authors:

Suhas Dinesh Sippee Bharadwaj

Tezpur University 9 PUBLICATIONS   2 CITATIONS   
16 PUBLICATIONS   6 CITATIONS   
SEE PROFILE
SEE PROFILE

Some of the authors of this publication are also working on these related projects:

DDoS attack View project

NEUROPATHY AND DIABETES View project

All content following this page was uploaded by Suhas Dinesh on 17 October 2017.

The user has requested enhancement of the downloaded file.

 Available online at www.sciencedirect.com

ScienceDirect
Available online at www.sciencedirect.com
Procedia Computer Science 00 (2017) 000–000
www.elsevier.com/locate/procedia
ScienceDirect
Procedia Computer Science 115 (2017) 756–763

7th International Conference on Advances in Computing & Communications, ICACC-2017, 22-

24 August 2017, Cochin, India

New Modified Current Starved Ring Voltage Controlled Oscillator

and Frequency to Voltage Rectifier for Noise Suppression from 1 –
6 GHz in 180 nm Technology
Suhas Da*, Sippee Bharadwajb
a
Department of Electronics and Communication Engineering, Tezpur University, Tezpur-784001, Assam, India
b
School of Engineering and Technology, Kaziranga University, Jorhat-785006, Assam, India

Abstract

This paper proposes a new and simple combined effort of a NMOS sink current starved ring voltage controlled oscillator (NS-
CSRVCO) fed-back with a manual frequency to voltage rectifier (FVR) for noise suppression in mixed signal applications. The
VCO and FVR operate from 1-6 GHz, with the VCO providing a tuning range of 176.4% with excellent linearity in oscillation
frequencies from 0.3444 GHz – 5.679 GHz with a center frequency of 3.024 GHz, within a control voltage (VDD) of 0.6 V to 2.5
V. The properties of both the VCO and FVR makes it suitable for Military, Satellite applications in the microwave range.

© 2017 The Authors. Published by Elsevier B.V.

Peer-review under responsibility of the scientific committee of the 7th International Conference on Advances in Computing &
Communications.

Keywords: NS-CSRVCO; FVR; linearity; wide tuning range; ultra-low power; low die area; low ac ripples; noise suppression

1. Introduction

Voltage Controlled Oscillators (VCOs) and Frequency to Voltage Rectifiers (FVRs) form important parts of a
Phase Locked Loop (PLL), ring oscillators et al. An ideal VCO/FVR is one whose output frequency/voltage is a

* Corresponding author. Tel.: +91-7577089226

E-mail address: suhasd90@gmail.com

1877-0509 © 2017 The Authors. Published by Elsevier B.V.

Peer-review under responsibility of the scientific committee of the 7th International Conference on Advances in Computing &
Communications.

1877-0509 © 2017 The Authors. Published by Elsevier B.V.

Peer-review under responsibility of the scientific committee of the 7th International Conference on Advances in Computing &
Communications
10.1016/j.procs.2017.09.170
 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763 757
2 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000

linear function of the applied input voltage/frequency. In addition to this the VCO and FVR must be: operating over
a wide frequency range, consume ultra-low power and be compact in size. For the jitter to not move around in PLL
design, a VCO with linear gain must be used, the FVR used must be fast with low ac output ripples.
With an explosive growth in wireless communication technologies; the demand for low power, compact size, wide
tuning range VCOs and FVRs have increased over the years [1-6]. CMOS technologies with low feature size have
become attractive for realizing compact, ultra-low power, high frequency ICs [7]. VCOs are realized by LC resonant
circuits or ring oscillators. LC oscillators have better phase noise and provide high output frequency, but with a low
tuning range. On the other hand, CMOS ring oscillators provide: wide tuning range, low power consumption, and
require low die area but require higher number of stages [8-11].
FVRs are designed by low-pass filtering of fixed time period pulses over time, counting number of pulses, and
integration of fixed width pulses. Approaches such as parallel path signal division [12, 13] and capacitance charge
redistribution [14, 15] have been published for FVR design. A low-pass filter is usually connected for the reduction
of ac ripples in the output of the FVR. Although, CMOS Ring Oscillators have the above said advantages, they
require increased number of stages for higher frequency of operation. This leads to higher power consumption,
larger die area requirement, high design complexity and narrow operating bandwidth. CMOS Ring Oscillators are
pushed towards high level of integration/density by Current Starved Ring (CSR) VCOs which exhibit wide tuning
range and achieve a practical balance among area, power and phase noise [16, 17]. Past works on CMOS or non-
CMOS ring oscillators using 180nm technology shows wide tuning range with high power consumed, or low tuning
range with high power consumed, high phase noise and large number of stages [16-26]. Similarly, FVRs designed
use complex circuitry, consume high power and use large die area for CMOS integrated applications. These increase
the design complexity and cost of the circuit designed.
In this work, we propose a new and simple three stage NMOS Sink Current Starved Ring Voltage Controlled
Oscillator (NS-CSRVCO) using NMOS sinks instead of sources and current mirrors for inverter starving. The FVR
is a simple rectifier with a NMOS switch fed with square waves of appropriate frequency and amplitude, a diode
using a NMOS transistor and attached to a suitable capacitor. The VCO and FVR are both designed using TSMC
180nm parameters and simulated using AWR v.12. The rest of the paper is structured as follows: Section 2 describes
the circuit design procedure and operation of the proposed NS-CSRVCO and FVR while section 3 discusses about
the simulation results, section 4 discusses about noise suppression using the proposed FVR and section 5 details the
conclusions and future work.

2. Operation and Circuit Architecture of the NS-CSRVCO and FVR

This section explains in detail both the operation and design procedure of the NS-CSRVCO and FVR. Both of
them are designed and implemented using MOSIS 180 nm parameters. The ring oscillator works by charging and
discharging the gate capacitance of the MOSFETS of each inverter. Increasing the peak current takes less time for
the capacitor to charge to the peak point. Consequently, the frequency of operation is increased. The manual FVR
operates by charging three capacitances namely: the gate oxide, the drain source and the 1 pF capacitors. It is to be
kept in mind that the NMOS switch used for the FVR must always operate in the linear region to be used as a
resistor. Hence, the amplitude at the drain is manually controlled for linear (Ohm’s region) operation of the NMOS
and the FVR acts as a simple RDC (Resistor Diode Capacitor) rectifier.

2.1. Design of New NMOS Sink – Current Starved Ring Voltage Controlled Oscillator (NS-CSRVCO)

A normal ring oscillator works by feeding the output of the nth stage (odd) inverter to its input. Ring oscillators
can generate very high frequencies upto 10 GHz and can withstand process and temperature variations. A control
voltage is used to control the current and thus the delay of each inverter of the ring oscillator. An assumption that a
propagation delay (Tpd) with each inverter and a logic level propagating around the loop in the absence of a stable
D.C. point is made, which results in one inversion around the loop. Each delay element provides a phase shift of π/n
and the remaining phase shift of (2π-(π/n)) is provided by the D.C. inversion. A detailed delay analysis of a basic
current starved ring oscillator is done here [27]. The oscillation period is thus twice of the propagation delay (T pd)
around the loop. Hence, the oscillation frequency can be expressed as (1).
 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000 3
758 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763

fosc = 1/2nTpd (1)

To adjust the propagation delay, current to the inverters is varied. This can be done in two ways. By varying the
control voltage or the supply voltage. These are the most accomplished manners to stabilize the oscillation
frequencies. The schematic of basic Current Starved (CS) VCO is shown in Fig. 1, where M2 and M3 MOSFETs
operate as inverters, whereas MOSFETs M1 and M4 operate as current source and current sink. The current source
and sink limit the amount of current to the CMOS Ring VCO and thus, the inverter is starved for current.

Fig.1: Schematic of basic CS VCO.

The design of NS-CSRVCO starts with removing the PMOS current sources and using only the NMOS sinks. To
increase the frequency range, linearity and reducing the phase noise, the current mirrors are removed and the process
technology is reduced to 180 nm. To maintain linear current, the aspect ratios are adjusted which changes the small
signal output resistance [27]. The schematic for NS-CSRVCO is shown in Fig. 2. It consists of a 3-stage ring
oscillator connected to a common - drain buffer or source follower and load. The source follower helps in matching
the broadband frequencies from 0.344 – 5.679 GHz to a 50 Ohm load. It is designed in 0.18µm technology using
MOSIS parameters without using current mirrors and PMOS current sources. With this architectural renovation, the
existing CS VCO topologies are simplified to achieve wide and linear tuning range while consequently reducing
power consumption and die area.
In this work, we introduce a new method of varying the output frequency by tuning VDD. As the Gate-Source
capacitance is larger than the Drain-Source capacitance, the Drain-Source capacitance takes less time to charge. This
leads to a more linear frequency curve at different drain voltages. The control voltage is maintained at 2.5 V, while
the drain voltage is varied from 0.6 V to 2.5 V in steps of 0.1 V.

2.2. Design of New NMOS Frequency to voltage Rectifier (FVR)

The FVR is designed as a simple Resistor-Diode-Capacitor (RDC) rectifier. It is used to convert an AC wave to DC
output with low ripples. Its circuit architecture is presented in Fig. 3. The circuit consists of two square wave inputs
connected to the gate and drain of the NMOS switch. The voltage given to the gate and drain ensure that the
MOSFET S15 (V_SQR) is working in the linear region as a resistor. The output of the NMOS switch S15 (V_SQR)
is connected to a NMOS diode S14 whose anode is its body terminal and cathode is its source terminal. The diode is
connected in the circuit, so that the capacitor does not discharge back through the MOSFET S15 (V_SQR). The
output of the NMOS diode is connected to a 1 pF capacitor. The capacitor can be implemented at high frequencies
using Stepped Impedance method. The amplitude of voltage to the diode is maintained such that it is above the
diode’s knee voltage. The whole circuit thus works as a simple Resistor-Diode-Capacitor (RDC) rectifier where
V_SQR 2 is rectified and a DC output voltage is produced. To ensure linearity, the voltage of V_SQR 2 is manually
 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763 759
4 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000

tuned. V_SQR amplitude is made constant in such a way that the MOSFET S15 (V_SQR) operates in the linear
region. The rectified output is available at the voltage probe VP 1.

VDD Vcontrol VSS

0.6 V 2.5 V 0V
6.59e-5 mA 0 mA 6.59e-5 mA

DC_V
DCVS DCVS
ID=V4
ID=V1 ID=V2
Sweep=Linear
V=2.5 V V=0 V
OSCAPROBE VStart=0.6 V
ID=X1 VStop=2.5 V
Fstart=0.05 GHz VStep=0.1 V
Fend=10 GHz 0.0017 mW
Fsteps=200 0V
Vsteps=40

Buffer and Load

0.248 V
VDD
A Ring Oscillator
3 2.19e-5 mA 3 2.19e-5 mA 3 2.19e-5 mA
S S S
SUBCKT SUBCKT SUBCKT
ID=S7 ID=S2 ID=S4
G SS W=8.1e-7 G SS W=8.1e-7 G SS W=8.1e-7
L=1.8e-7 L=1.8e-7 SUBCKT
2 2 2 L=1.8e-7
0 mA 4 0 mA 0.000257 mW 0 mA 4 0 mA 0.000262 mW 0 mA 4 0 mA 0.000284 mW ID=S10
W=2.7e-7 1 D0 mA
L=1.8e-7
1 D 1 D 1 D 3.52e-6 mW 4
2
2.19e-5 mA 0GmA SS CAP PORT
1 D 1 D0.248
2.19e-5
V mA
1 D 2.19e-5 mA 0 mA
ID=C1
2.19e-5 mA P=1
C=1 mF Z=50 Ohm
4
SUBCKT
4
SUBCKT
4
SUBCKT 3 S
2 ID=S6 2 ID=S1 2 ID=S3
0GmA SS 0 mA W=2.7e-7 G V
0.248 SS 0 mA W=2.7e-7 0GmA SS 0 mA W=2.7e-7 0 mA 0.185 V 0 mA
V
OSCNOISE L=1.8e-7 L=1.8e-7 L=1.8e-7 SUBCKT
0 mA ID=S11 0 mA
ID=NS1 0.000265 mW 0.000273 mW 0.00029 mW
W=2.7e-7
OFstart=1e-6 GHz 3 S 3 S 3 S L=9e-7
OFend=0.001 GHz
OFsteps=20 4.89e-6 mW
SwpType=LOG 1 D3.16e-5
2.19e-5
V mA
1 D3.16e-5
2.19e-5
V mA
1 D3.16e-5
2.19e-5
V mA
1 D0 mA
2.19e-5 mA 2.19e-5 mA 2.19e-5 mA
Harm={1,2}
SUBCKT SUBCKT SUBCKT
2 4 2 4 2 4 2 4
ID=S5 ID=S8 ID=S9
Vcontrol W=2.7e-7 W=2.7e-7 W=2.7e-7
0GmA SS 0 mA 0GmA SS 0 mA 0GmA SS 0 mA 0GmA SS 0 mA
L=1.8e-7 L=1.8e-7 L=1.8e-7
6e-6 mW 6.47e-6 mW 7.86e-6 mW
3 S 3 S 3 S 3 S

2.19e-5 mA 2.19e-5 mA 2.19e-5 mA 0 mA

VSS
NMOS Sinks

Fig. 2: Modified architecture of CS Ring VCO.

3. Simulation Results and Discussions

This section deals with the results of the designed and simulated circuits of Section II. First the results of CMOS
VCO characteristics like frequency tuning and linearity, output voltage swing, phase noise, total power consumed
and the Figure of Merit (FOM) are discussed. Afterwards, discussion on FVR characteristics like ac ripples, power
consumption, rectification speed, linearity, die area occupied are carried out.

3.1. Simulation Results of NS-CSRVCO

The proposed NS-CSRVCO is designed using MOSIS 180nm parameters and simulated using AWR v.12. For
the three stage NS-CSRVCO, the maximum output voltage swing with this architecture at 2.5 V is shown in Fig. 4.
The output swing as observed is triangular in nature and its frequency is 5.679 GHz. As said before, a good linearity
while tuning from 0.3444 GHz to 5.679 GHz is observed with tuning voltage from 0.6 V to 2.5 V with a center
frequency of 3.024 GHz. Thus, a tuning range of about 176.4 % is obtained. The maximum power consumed by the
oscillator at 2.5 V is 0.5988 mW. These are shown in Fig. 5.
760 Suhas. D. etDal./
Suhas et Procedia Computer
al. / Procedia Science
Computer 00 (2017)
Science 000–000
115 (2017) 756–763 5

V_SQR
ID=V2
AMP=6 V
TR=0 us
TF=0 us
TD=0 us
WINDOW=DEFAULT
Offset=0 V
DCVal=0 V VTIME
0.561 uW 0.9
M_PROBE
Vtime(M_PROBE.VP1,1)[*,20] (V)
0.52 ns 0.7 ns
ID=VP2 0.7 0.584 V final cs vco.AP_TR
2 1 SUBCKT 0.571 V
D

G
M_PROBE ID=S14
ID=VP4 W=2.7e-7 0.5
V_SQR2 1 4 2 L=1.8e-7
3
ID=V5

Voltage (V)
SS G 0.3
AMP=2.38 V D

SS

S
4
F=5.679 GHz
TR=0 us S
TF=0 us
3 0.1
SUBCKT M_PROBE
TD=0 us ID=S1 ID=VP1
WINDOW=DEFAULT W=2.7e-7
Offset=0 V
-0.1
L=1.8e-7
DCVal=0 V 1.83 uW CAP
1.27 uW ID=C2 -0.3
C=1 pF

-0.5
0 1 2 3
Time (ns)

Fig. 3: Circuit architecture of proposed FVR. Fig. 4: Triangular output voltage at a control voltage of 2.5 V

Phase noise is a measurement at a specified frequency away from the carrier whose time equivalent is called
Jitter. It is the noise in 1 Hz bandwidth away from the carrier at a particular offset frequency. Thus, a phase noise of
-117 dBc/Hz shown in Fig. 6 is obtained at an offset of 1 MHz from the 3.024 GHz carrier.
Fig. 8 shows the graph of FVR input frequency vs. its rectified output voltage. The obtained curve is highly linear,
where the input amplitude of the FVR is manually tuned to obtain the output frequencies that are matched to the NS-
CSRVCO. This can help in stabilizing/suppressing noise of the NS-CSRVCO output frequencies which is explained
in the next section.

TUNING FREQUENCY AND TOTAL POWER CONSUMED PHASE NOISE

6 2 -20
OSC_FREQ()[*,X] (L, GHz)
2.5 V DB(L_LSB(PORT_1,1,1))[*,20,X]
final cs vco.AP_HB final cs vco.AP_HB
5.679 GHz
Total Power Consumed (mW)

PT(DC_V.V4)[*,X] (R, mW) -40

Oscillation Frequency (GHz)

final cs vco.AP_HB 2.5 V

1e-006 GHz
Phase Noise (dBc/Hz)

1.25 V 0.5988 mW
4 0.6 V -29.45 dB
0.06979 mW
0.001701 mW -60
0
1.25 V -80
2 3.024 GHz 0.001 GHz
-117 dB
-100
0.6 V
0.3444 GHz

0 -2 -120
0.6 0.85 1.1 1.35 1.6 1.85 2.1 2.35 2.5 1e-006 1e-005 .0001 .001
Control Voltage (VDD) (V) Frequency (GHz)

Fig. 5: Oscillation Frequencies and Total Power Fig. 6: Phase Noise vs. Offset Frequency.
consumed with tuning in Supply Voltage (VDD).

3.2. Simulation Results of Resistor Diode Capacitor (RDC) Rectifier

The transient and steady state output response at 1 pF capacitor of FVR (Frequency to Voltage Rectifier)/RDC
rectifier is shown in Fig. 7. From the figure, a steady state voltage of 2.502 V is obtained for 5.679 GHz input
waveform with 2.38 V FVR input voltage. The FVR designed is fast, with low ripples and consumes ultra-low die
area with ultra-low power consumption. The maximum power consumed by the FVR is 1.83 µW.
 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763 761
6 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000

Table 1. Comparison with previous works

CMOS Power Tuning Phase Offset
References Process Stages Consumed Range Noise Frequency
Tech. Fosc Fmin Fmax (mW) (%) (dBc/Hz) (MHz)
(GHz) (GHz) (GHz)
This Work 180nm 3 3.024 0.344 5.679 0.598 176.4 -117 1
Eken [10, 11] 180nm 3 5.79 5.16 5.93 - 14 -99.5 1
Tao [19] 180nm 5 10.6 8.4 10.6 43 23 -85 1
Hajimiri [20] 180nm 4 5.43 4.22 5.43 80 25 -98.5 1
Tao [21] 180nm 5 5 4.3 6.1 65 35 -85 1
Park [22] 180nm 4 0.9 0.75 1.2 35 46.2 -117 0.6
Jeong [23] 180nm 4 1.69 0.25 1.69 96 148.5 -79 0.6
A. Baishya [24] 350nm 4 1.5 0.7 1.75 0.07 75 -88 1
Hsieh [25] 180nm - 1.12 5.1 5.2 0.69 8.9 -97 1
Takeshi [26] 180nm 4 1 - - 0.71 - -68 0.1

4. Noise Suppression using the proposed FVR

This section depicts how to suppress the noise created by the input to NS-CSRVCO and the oscillator itself, using
the FVR designed above. The output of the NS-CSRVCO can be corrupted by noise. Hence, a feedback through an
FVR is given, where the input amplitude of the frequency source (V_SQR2) is manually set by the user to output a
noise suppressed frequency through the NS-CSRVCO [28]. This should improve the phase noise/jitter performance.

TRANSIENT AND STEADY STATE RESPONSE

3

149.9 us
4.426 us
83.94 us 2.502 V
2.408 V
2.494 V
Voltage (V)

Vtime(M_PROBE.VP1,1)[*] (V)
Schematic 1.AP_TR

0
0 25 50 75 100 125 150
Time (us)

Fig. 7: Transient and Steady State response at 5.679 GHz. Fig. 8: FVR input frequency and rectified voltage.

Table 2 shows the FVR input amplitude with the noisy AC VCO frequency required to produce the DC voltage
required to suppress the noise and produce a noise free frequency. From the table one can observe, when both VCO
control voltage and FVR output voltage are equal, FVR input frequency and VCO output frequency are equal. For
this to happen, FVR manual amplitude as per Table 2 has to be inputted to the FVR, as the VCO amplitude is
corrupted by noise. From Table 2, the amplitude to the FVR or the VCO output is not enough as it is corrupted by
noise. To improve the VCO amplitude, which is corrupted by noise, the feedback through the FVR and manual
tuning is given. This can stabilize the VCO amplitude and produce a noise free output frequency.
 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000 7
762 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763

Table 2. VCO and FVR amplitudes and frequencies.

VCO Output VCO Output VCO Control FVR FVR Input FVR
Amplitude Frequency Voltage Output Frequency Input
Voltage Manual
Amplitude
0.1885 0.3444 0.6 0.6002 0.3444 0.41
0.2763 1.623 0.9 0.9012 1.623 0.75
0.3577 2.846 1.2 1.2 2.846 1.04
0.48 3.848 1.5 1.5 3.848 1.35
0.644 4.609 1.8 1.805 4.609 1.63
0.818 5.167 2.1 2.101 5.167 1.9
1.048 5.679 2.5 2.502 5.679 2.38

5. Conclusions and Future Work

This work focusses on the design and simulation of a new NMOS Sink – Current Starved Ring Voltage
Controlled Oscillator (NS-CSRVCO), and Frequency to voltage rectifier/Resistor Diode Capacitor rectifier
(FVR/RDC) for converting ac waves into dc voltages for mixed signal (analog/digital) applications. The FVR is
used as a feedback to the NS-CSRVCO to suppress the noise produced by the NS-CSRVCO and its input. In this
way, a pure oscillation frequency is obtained that is uncorrupted by noise. The VCO and FVR are designed using
MOSIS 180 nm parameters and simulated using AWR V.12 software. The VCO provides an excellent linearity with
wide tuning range, low phase noise, high Q factor and occupy low die area, while the FVR possesses the properties
of good linearity, wide tuning range and very fast operation with low ac ripples and occupy ultra-low die area. The
VCO and FVR operate from 1-6 GHz, with the VCO providing a tuning range of 176.4% with excellent linearity in
oscillation frequencies from 0.3444 GHz – 5.679 GHz with a center frequency of 3.024 GHz, within a control
voltage of 0.6 V to 2.5 V. The oscillator consumes a maximum power of 0.5988 mW with a phase noise of -117
dBc/Hz at 1 MHz offset from the center frequency when connected to a 50 Ohm port, which corresponds to an
FOM/Q of 188.84 dBc/Hz/mW. The FVR consumes a maximum power of 1.83 µW. The properties of both the
VCO and FVR with the additional property of noise suppression by the FVR makes the circuit to be appropriate for
applications in the microwave range. The future work will concentrate on the design and analysis of an Automatic
FVR tuned to the VCO to obtain an uncorrupted frequency to improve the oscillator’s phase noise.

References

[1] Va Lizhong Sun and T. A. Kwasniewski. A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. IEEE Journal of
Solid-State Circuits 2001; 36 (6): 910-916.
[2] J. Savoj and B. Razavi. A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector. IEEE Journal of Solid-State
Circuits 2001; 36 (5): 761-768.
[3] Chih-Kong Ken Yang, Ramin Farjad-Rad and M. A. Horowitz. A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using
oversampling. IEEE Journal of Solid-State Circuits 1998; 33 (5): 713-722.
[4] M. Alioto and G. Palumbo. Oscillation frequency in CML and ESCL ring oscillators. IEEE Transactions on Circuits and Systems I
Fundamental Theory and Applications 2001; 48 (2): 210-214.
[5] B. Razavi. A 2-GHz 1.6-mW phase-locked loop. IEEE Journal of Solid-State Circuits 1997; 32 (5): 730-735.
[6] H. R. Rategh, H. Samavati and T. H. Lee. A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless
LAN receiver. IEEE Journal of Solid-State Circuits 2000; 35 (5): 780-787.
[7] R. Tao and M. Berroth. The design of 5 GHz voltage controlled ring oscillator using source capacitively coupled current amplifier. IEEE
Radio Frequency Integrated Circuits (RFIC) Symposium 2003; 623-626.
 Suhas D et al. / Procedia Computer Science 115 (2017) 756–763 763
8 Suhas. D. et al./ Procedia Computer Science 00 (2017) 000–000

[8] R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation (3rd ed.). Wiley-IEEE Press 2010.
[9] Rui Tao and M. Berroth. 5 GHz voltage controlled ring oscillator using source capacitively coupled current amplifier. Topical Meeting on
Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers, Grainau, Germany 2003: 45-48.
[10] Y. A. Eken and J. P. Uyemura. The design of a 14 GHz I/Q ring oscillator in 0.18 μm CMOS. IEEE International Symposium on Circuits
and Systems (IEEE Cat. No.04CH37512) 2004; 4: IV-133-6.
[11] Y. A. Eken and J. P. Uyemura. A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS. IEEE Journal of Solid-State Circuits Jan.
2004; 39 (1): 230-233.
[12] W. Surakampontorn, Y. Chonbodeechalermroong and S. Bunjongjit. An analog sinusoidal frequency-to-voltage converter. IEEE
Transactions on Instrumentation and Measurement Dec 1991; 40 (6): 925-929.
[13] T. Y. Lin, E. M. Drakakis and A. J. Payne. Architecture for frequency-to-current conversion. Electronics Letters. Nov 2001; 37 (24): 1427-
1428, 22.
[14] A. Djemouai, M. A. Sawan and M. Slamani. New frequency-locked loop based on CMOS frequency-to-voltage converter: design and
implementation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing May 2001; 48 (5): 441-449.
[15] H. T. Bui and Y. Savaria. Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-
Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers April 2008; 55 (3): 766-774.
[16] Ming-Ta Hsieh, Jim Welch, and Gerald E. Sobelman. PLL performance comparison with application to spread spectrum clock generator
design, Analog Integr. Circuits Signal Process May 2010; 63 (2).
[17] T. Miyazaki, M. Hashimoto and H. Onodera. A performance comparison of PLLs for clock generation using ring oscillator VCO and LC
oscillator in a digital CMOS process. Asia and South Pacific Design Automation Conference (IEEE Cat. No.04EX753), Yohohama, Japan,
2004: 545-546.
[18] GS Jovanovic and MK Stojcev. Current starved delay element with symmetric load. International journal of electronics, Taylor and Francis,
2006; 93(03):167-175.
[19] R. Tao and M. Berroth. Low power 10 GHz ring VCO using source capacitively coupled current amplifier in 0.12 μm CMOS technology.
Electronics Letters, 11 Nov. 2004; 40 (23): 1484-1486.
[20] A. Hajimiri, S. Limotyrakis and T. H. Lee. Jitter and phase noise in ring oscillators. IEEE Journal of Solid-State Circuits, Jun 1999; 34 (6):
790-804.
[21] R. Tao and M. Berroth. The design of 5 GHz voltage controlled ring oscillator using source capacitively coupled current amplifier. IEEE
Radio Frequency Integrated Circuits (RFIC) Symposium 2003: 623-626.
[22] Chan-Hong Park and Beomsup Kim. A low-noise 900 MHz VCO in 0.6 /spl mu/m CMOS, 1998 Symposium on VLSI Circuits. Digest of
Technical Papers (Cat. No.98CH36215) 1998, Honolulu, HI, USA: 28-29.
[23] Dong-Youl Jeong, Sang-Hoon Chai, Won-Chul Song and Gyu-Hyeong Cho. CMOS current-controlled oscillators using multiple-feedback-
loop ring architectures. IEEE International Solids-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, USA, 1997:
386-387.
[24] A Baishya, Trupa Sarkar, MK Naskar, and PP Sahu. A new cmos voltage controlled ring oscillator for low power radio transceiver
applications. International Conference on Communication and Electronics System Design, International Society for Optics and Photonics
2013: 87601B-1-87601B-7.
[25] Hsieh-Hung Hsieh, Kuo-Sheng Chung and Liang-Hung Lu. Ultra-low-voltage mixer and VCO in 0.18-μm CMOS. IEEE Radio Frequency
Integrated Circuits (RFIC) Symposium - Digest of Papers 2005: 167-170.
[26] Takeshi Yoshida, Naoya Ishida, Mamoru Sasaki, and Atsushi Iwata. Low-voltage, low-phase-noise ring voltage-controlled oscillator using
1/f-noise reduction techniques. Japanese journal of applied physics 2007; 46(4S): 22-57.
[27] S. Suman, K. G. Sharma and P. K. Ghosh. Analysis and design of current starved ring VCO. International Conference on Electrical,
Electronics, and Optimization Techniques (ICEEOT), Chennai 2016: 3222-3227.
[28] https://www.google.ch/patents/US8547150

View publication stats