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Datasheet HY27UF082G2B PDF
Datasheet HY27UF082G2B PDF
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.2 / Jan. 2008 1
1
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
Document Title
2Gbit (256Mx8bit) NAND Flash Memory
Revision History
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
FEATURES SUMMARY
CACHE READ
- Internal (2048 + 64) Byte buffer to improve the read
throughtput.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
1.SUMMARY DESCRIPTION
Hynix NAND HY27UF(08/16)2G2B Series have 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most cost-effective solution for the solid state
mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typi-
cal 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block.
Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data
input/output as well as command input.
This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The
on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where
required, and internal verification and margining of data. The modify operations can be locked using the WP input. The
output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple mem-
ories the R/B pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management. When a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error
every 528byte (x8) or 1bit error out of every 264-word (x16) can be detected. Due to this feature, it is no more nor neces-
sary nor recommended to use external 2-bit ECC to detect copy back operation errors. Data read out after copy back read
(both for single and multiplane cases) is allowed.
Even the write-intensive systems can take advantage of the HY27UF(08/16)2G2B Series extended reliability of 100K pro-
gram/erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE
don’t care function. This function allows the direct download of the code from the NAND Flash memory device by a micro-
controller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The HY27UF(08/16)2G2B Series are available in 48-TSOP1 12 x 20 mm, 63-FBGA 9 x 11mm, 52-ULGA 12 x 17 mm.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
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HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
NOTE:
1. L must be set to Low.
I/O8-
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7
IO15
1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1)
2nd Cycle A8 A9 A10 L(1) L(1) L(1) L(1) L(1) L(1)
3rd Cycle A11 A12 A13 A14 A15 A16 A17 A18 L(1)
4th Cycle A19 A20 A21 A22 A23 A24 A25 A26 L(1)
5th Cycle A27 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1)
Table 4: Address Cycle Map(x16)
NOTE:
1. L must be set to Low.
Acceptable command
FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE 4th CYCLE
during busy
READ1 00h 30h - -
READ FOR COPY-BACK 00h 35h - -
READ ID 90h - - -
RESET FFh - - - Yes
PAGE PROGRAM 80h 10h - -
COPY BACK PGM 85h 10h - -
MULTI PLANE PROGRAM 80h 11h 81h 10h
MULTI PLANE COPYBACK 85h 11h 81h 10h
PROGRAM
BLOCK ERASE 60h D0h - -
MULTI PLANE 60h 60h D0h -
BLOCK ERASE
READ STATUS REGISTER 70h - - - Yes
RANDOM DATA INPUT 85h - - -
RANDOM DATA OUTPUT 05h E0h - -
READ CACHE (RANDOM) 00h 31h - -
READ CACHE (SEQUENTIAL) 31h - - -
READ CACHE END 3Fh - - -
READ EDC STATUS REGISTER 7Bh - - -
Note:
1. READ EDC STATUS REGISTER is only available on Copy Back operation.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
NOTE:
1. With the CE high during latency time does not stop the read operation
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.6 Standby
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
3. DEVICE OPERATION
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
The operation for performing a copy-back program is a sequential execution of page-read without serial access and
copying-program with the address of destination page. A read operation with "35h" command and the address of the
source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready
state, optional data read-out is allowed by toggling RE (See Figure 23), or Copy Back command (85h) with the
address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin
the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is
allowed as shown in Figure 23.
Most NAND devices require 2 bit external ECC only due to copy back operation while 1 bit ECC can be enough for all
other operation. Reason is that during read for copy back + copy back program sequence a bit error due to charge
loss is not checked by external error detection/correction scheme. On the contrary, 2Gbit NAND includes automatic
Error Detection Code during copy back operation: thanks to this, 2 bit external ECC is no more required, with signifi-
cant advantage for customers that can always use single bit ECC. More details on EDC operation are available in sec-
tion 3.8.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
EDC result can be checked only during copy back program through 7Bh (specific Read EDC register command, Table 22)
3.12 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table
14 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure
27.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
4. OTHER FEATURES
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a
reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied.
Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be
obtained with the following reference chart (Fig 28). Its value can be determined by the following guidance.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
NOTE:
1. The 1st block is guaranteed to be a valid block at the time of shipment.
NOTE:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of
the device at these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Refer also to the Hynix SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
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2Gbit (256Mx8bit) NAND Flash
3.3Volt
Parameter Symbol Test Conditions Unit
Min Typ Max
Sequential tRC=25ns
ICC1 - 15 30 mA
Read CE=VIL, IOUT=0mA
Operating
Current Program ICC2 - - 15 30 mA
Erase ICC3 - - 15 30 mA
CE=VIH,
Stand-by Current (TTL) ICC4 - 1 mA
WP=0V/Vcc
CE=Vcc-0.2,
Stand-by Current (CMOS) ICC5 - 10 50 uA
WP=0V/Vcc
Input Leakage Current ILI VIN=0 to Vcc (max) - - ± 10 uA
Output Leakage Current ILO VOUT =0 to Vcc (max) - - ± 10 uA
Input High Voltage VIH - 0.8xVcc - Vcc+0.3 V
Input Low Voltage VIL - -0.3 - 0.2xVcc V
Output High Voltage Level VOH IOH=-400uA 2.4 - - V
Output Low Voltage Level VOL IOL=2.1mA - - 0.4 V
IOL
Output Low Current (R/B) VOL=0.4V 8 10 - mA
(R/B)
Table 9: DC and Operating Characteristics
Value
Parameter
3.3Volt
Input Pulse Levels 0V to VCC
Input Rise and Fall Times 5ns
Input and Output Timing Levels VCC/2
Output Load (2.7V - 3.6V) 1 TTL GATE and CL=50pF
Table 10: AC Conditions
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
3.3V
Parameter Symbol Unit
Min Max
CLE Setup time tCLS 12 ns
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
1 NA NA NA NA -
2 NA NA NA NA -
3 NA NA NA NA -
4 NA NA NA NA -
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
3 NA -
4 NA -
HY27UF(08/16)2G2B Series
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HY27UF(08/16)2G2B Series
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HY27UF(08/16)2G2B Series
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NOTE :
1. An error occurs on nth page of the Block A during program or erase operation.
2. Data in Block A is copied to same location in Block B which is valid block.
3. Nth data of block A which is in controller buffer memory is copied into nth page of Block B
4. Bad block table should be updated to prevent from eraseing or programming Block A
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations
are enabled and disabled as follows (Figure 33~36)
:(
W ::
:3
5%
:(
W ::
:3
5%
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
:(
W ::
:3
5%
:(
W ::
:3
5%
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
H $ $
' %
$ Į /
',(
( &
(
&3
Figure 37: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
millimeters
Symbol
Min Typ Max
A 1.200
A1 0.050 0.150
A2 0.980 1.030
B 0.170 0.250
C 0.100 0.200
CP 0.100
e 0.500
L 0.500 0.680
alpha 0 5
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
'
'
'
)'
6'
)'
H
( ( ( 6(
)(
)(
%$//³FS´
H E
$ $
$
Figure 38: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline
NOTE: Drawing is not to scale.
Millimeters
Symbol
Min Typ Max
A 0.80 0.90 1.00
A1 0.25 0.30 0.35
A2 0.55 0.60 0.65
b 0.40 0.45 0.50
D 8.90 9.00 9.10
D1 4.00
D2 7.20
E 10.90 11.00 11.10
E1 5.60
E2 8.80
e 0.80
FD 2.50
FD1 0.90
FE 2.70
FE1 1.10
SD 0.40
SE 0.40
Table 25: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
%
%
%
' '
&
&
&
$ $ $
FS
0 & $% FS
0 & $%
millimeters
Symbol
Min Typ Max
A 16.90 17.00 17.10
A1 13.00
A2 12.00
B 11.90 12.00 12.10
B1 10.00
B2 6.00
C 1.00
C1 1.50
C2 2.00
D 1.00
D1 1.00
E 0.65
CP1 0.65 0.70 0.75
CP2 0.95 1.00 1.05
HY27UF(08/16)2G2B Series
2Gbit (256Mx8bit) NAND Flash
P a ck a g M a rk in g E x a m p le
TSO P1 K O R
/
FBG A H Y 2 7 U F x x 2 G 2 B
/
ULGA x x x x Y W W x x
- h y n ix : H yn ix S ym bo l
- KOR : O rig in C ou n try
- H Y27UFxx2G 2B xxxx : P a rt N u m b er
H Y : H yn ix
2 7 : N A N D Fla sh
U : P o w e r S u p p ly : U (2 .7 V ~ 3 .6 V )
F : C la ssifica tion : S in g le Leve l C e ll+ S in g le D ie + Larg e B lo ck
x x : B it O rga n izatio n : 0 8 (x8 ), 1 6 (x1 6 )
2 G : D e n sity : 2 G b it
2 : M o de : 2 (1 n C E & 1 R /n B ; S e q u e n tia l R o w R e a d D isa ble )
B : V e rsion : 3 rd G e n era tion
- Y : Y e ar (ex: 5 = ye ar 2 0 0 5 , 6= ye a r 2 0 0 6 )
- w w : W o rk W eek (e x: 12 = w ork w eek 12 )
- x x : P roce ss C o d e
N o te
- C a p ita l L e tte r : Fixe d Ite m
- S m a ll L e tte r : N on -fixe d Ite m