Pwwha: Delhi 10R

A B C D E
1 1
PWWHA
2 Delhi 10R 2
LA-7202P REV 1.0 Schematic

3
Intel Processor(Sandy Bridge) / PCH(Cougar Point) 3
2011-02-08 Rev 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWHA LA-7202P M/B
Date: Friday, February 25, 2011 Sheet 1 of 43
A B C D E
A B C D E
Intel CPU
Sandy Bridge
1
rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12
page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s
CRT FDI X8 DMI X4

page 14
2.7GT/s 5GT/s
USB/B Left 2IN1 RTS5137 Int. Camera

USB port 0,1 USB port 10 USB port 11
USB page 24 page 27 page 13
5V 480MHz
LVDS Conn.
page 13
PCIeMini Card
2
USB WiMax USB port 9 2
5V 480MHz page 25
PCIe 1x PCIeMini Card
1.5V 5GT/s
WLAN PCIe port 2
Intel PCH page 25
Cougar Point - M
RTL8105E 10/100M SATA port 0 SATA HDD
RJ45 PCIe 1x 5V 6GHz(600MB/s) SATA port 1
page 26 1.5V 5GT/s page 24
PCIe port 1
page 26
FCBGA-989
25mm*25mm SATA port 2 SATA ODD
5V 3GHz(300MB/s) SATA port 4
page 24
page 15,16,17,18,19,20,21,22,23
3 3
LPC BUS HD Audio 3.3V 24MHz

3.3V 33 MHz
HDA Codec
ALC259
SPI ROM Debug Port ENE KB930 page 28
page 31 page 30
(4MB)
page 15
RTC CKT.
page 16
Touch Pad Int.KBD EC ROM Int. SPK Conn HP & MIC
page 32 page 32 MIC Conn
DC/DC Interface CKT. (128KB)
page 31
page 29 page 29 page 29
page 33
4 4
Power Circuit DC/DC

page 34,35,36,37,38,39
,40,41
2010/09/03 2012/12/31 Title
Power/B Issued Date Deciphered Date
Block Diagram
DA40000XR10 page 32
1.0
PWWHA LA-7202P M/B
Date: W ednesday, March 02, 2011 Sheet 2 of 43
A B C D E
5 4 3 2 1
DESIGN CURRENT 0.1A +3VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A DESIGN CURRENT 5A +5VALW
SUSP#
DESIGN CURRENT 2A +1.8VS

SY8033BDBC
SUSP
D D
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
ODD_EN#
P-CHANNEL DESIGN CURRENT 1.8A +5VS_ODD

AO-3413
TPS51125ARGER
Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW

WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413
C C
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3413
VR_ON
Ipeak=94A, Imax=52A, Iocp min=122A DESIGN CURRENT 94A +CPU_CORE

ISL95831HRTZ-T DESIGN CURRENT 33A
Ipeak=33A, Imax=21.5A, Iocp min=40A +GFX_CORE
SUSP#
Ipeak=17A, Imax=11.9A, Iocp min=19.23A DESIGN CURRENT 15A +1.05VS_VCCP

TPS51117RGYR
B B
VCCPPWRGD
Ipeak=6A, Imax=4.2A, Iocp min=7A DESIGN CURRENT 6A +VCCSA

TPS51117RGYR
SYSON
Ipeak=9A, Imax=6.3A, Iocp min=9.92A DESIGN CURRENT 10A +1.5V
TPS51117RGYR SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
SUSP
N-CHANNEL DESIGN CURRENT 2A +1.5VS

SI4800
+3V
DESIGN CURRENT 1A +1.05V

APL5930KAI-TRG
0.75VR_EN#
A A
DESIGN CURRENT 1.5A +0.75VS

UP7711U8

Power Tree
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
A B C D E
( O MEANS ON X MEANS OFF )

Voltage Rails
+5VS
+RTCVCC B+ +3VL +5VALW +1.5V
+3VS
+3VALW
+1.8VS
+VSB
power +1.5VS
1 plane +1.05VS
1
+0.75VS
+CPU_CORE
+GFX_CORE
State
BTO Option Table

Function MINI PCI-E SLOT LAN Camera & Mic FAN S3 Power Saving Load Power Switch
S0 description SLOT1 LAN Camera & Mic FAN S3 Power Saving Load Power Switch
O O O O O O
explain WIMAX 10/100M Giga Camera & Mic PWM RPM 1.5V 1.5VS Old Sch. New Sch.
S1
O O O O O O
BTO WIMAX@ 8105E@ 8111E@ CAM@ PWM@ RPM@ WPS3@ PS3@ OLS@ NLS@
2 2
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X
PCH SM Bus Address
Power Device HEX Address

+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3
+3VS Clock Generator D2 H 1101 0010 b

+3VS WLAN/WIMAX
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
S4 (Suspend to Disk) LOW LOW HIGH
S5 (Soft OFF) LOW LOW LOW

4 4
G3 LOW LOW LOW

Notes List
Custom 1.0
PWWHA LA-7202P M/B
A B C D E
5 4 3 2 1
JCPUB
100 MHz
@ PROC_SELECT# A28 CLK_CPU_DMI Stuff R41 and R42 if do not support eDP
BCLK CLK_CPU_DMI <16>
MISC
CLOCKS
1000P_0402_50V7K 2 1 C487 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#
<19> H_SNB_IVB# SNB_IVB# BCLK# CLK_CPU_DMI# <16>
@ 120 MHz +1.05VS_VCCP
1000P_0402_50V7K 2 1 C488 H_PWRGOOD T1 PAD TP_SKTOCC# AN34
SKTOCC# CLK_CPU_DPLL
DPLL_REF_SSCLK A16
A15 CLK_CPU_DPLL# CLK_CPU_DPLL# R42 1 2 1K_0402_5%
DPLL_REF_SSCLK#
D CLK_CPU_DPLL R41 1 D
2 1K_0402_5%
T2 PAD H_CATERR# AL33 CATERR#
THERMAL
H_PECI AN33 R8 H_DRAMRST#
<30> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
DDR3
MISC
+1.05VS_VCCP R450
<30,35> H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 R1437 2 1 140_0402_1% DDR3 Compensation Signals
56_0402_5% PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R1438 2
SM_RCOMP[1] A5 1 25.5_0402_1% Layout Note:Place these
R47 2 1 62_0402_5% H_PROCHOT# A4 SM_RCOMP_2 R1439 2 1 200_0402_1% resistors near Processor
SM_RCOMP[2]
H_THERMTRIP# AN32
<20> H_THERMTRIP# THERMTRIP#
R51 2 1 10K_0402_5% H_PWRGOOD
Remove R14(o ohm) for HW Review demand AP29 XDP_PRDY#_R R1 1 @ 2 0_0402_5% XDP_PRDY#
PRDY# XDP_PREQ#_R R2 1 @ XDP_PREQ#
AP27 2 0_0402_5%
PREQ#
AR26 XDP_TCK_R R4 1 @ 2 0_0402_5% XDP_TCK
TCK
PWR MANAGEMENT
AR27 XDP_TMS_R R6 1 @ 2 0_0402_5% XDP_TMS
JTAG & BPM

H_PM_SYNC TMS XDP_TRST#_R XDP_TRST#
<17> H_PM_SYNC AM34 AP30 R7 1 @ 2 0_0402_5% Routed as a single daisy chain
PM_SYNC TRST#
AR28 XDP_TDI_R R8 1 @ 2 0_0402_5% XDP_TDI
TDI XDP_TDO_R R10 1 @ XDP_TDO
AP26 2 0_0402_5%
H_PWRGOOD TDO R36
<20> H_PWRGOOD AP33
UNCOREPWRGOOD
1 2 +3VS
1K_0402_5%
AL35 XDP_DBRESET#_R R11 1 @ 2 0_0402_5% XDP_DBRESET#
PM_SYS_PWRGD_BUF 1 DBR# XDP_DBRESET# <17>
2 PM_DRAM_PWRGD_R V8
C R454 130_0402_5% SM_DRAMPWROK C
AT28 XDP_BPM#0_R R12 1 @ 2 0_0402_5% XDP_BPM#0
BPM#[0] XDP_BPM#1_R R13 1 @ 0_0402_5% XDP_BPM#1
AR29 2
BPM#[1] XDP_BPM#2_R R15 1 @ 0_0402_5% XDP_BPM#2
BPM#[2] AR30 2
BUF_CPU_RST# AR33 AT30 XDP_BPM#3_R R18 1 @ 2 0_0402_5% XDP_BPM#3 PU/PD for JTAG signals
RESET# BPM#[3] +1.05VS_VCCP
AP32
BPM#[4]
BPM#[5] AR31 Close to CPU side
AT31 XDP_TMS_R R28 2 1 51_0402_5%
+3VALW BPM#[6]
BPM#[7] AR32
XDP_TDI_R R29 2 1 51_0402_5%
+1.5V_CPU XDP_TDO R30 2 1 51_0402_5%
1
C93
0.1U_0402_16V4Z Sandy Bridge_rPGA_Rev0p61 @ XDP_TCK_R R31 2 1 51_0402_5%
1
PS3@
2 XDP_TRST#_R R32 2 1 51_0402_5%
U10 R339
R312 74AHC1G09GW_TSSOP5 200_0402_5%
5
0_0402_5% PS3@
2
1 2 1
P
<17,30> PM_PWROK
<17> DRAMPWROK
PS3@
2
B
O
4 PM_SYS_PWRGD_BUF FAN Control Circuit (RPM and PWM)
A
G
+5VS
1
1A 01/24 pin define change by Thermal

3
R340
39_0402_5% 2 JFAN2 @
@ C12 +FAN2 1
R384 1 1
2 0_0402_5% 10U_0805_10V6K 2
1 2
WPS3@ RPM@ 2
2 3
D Q5 U1 1 C14 3
SUSP 2 2N7002_SOT23 1 8 1000P_0402_50V7K 4
<9,25,33,40> SUSP EN GND GND
G @ 2 7 @ 5
B +FAN2 VIN GND 1 GND B
S 3 6
3
VOUT GND
<30> EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
10mil 1
APL5607KI-TRG_SO8 R14 10K_0402_5% RPM@
C15 RPM@ 2 1 +3VS
JXDP @ 10U_0805_10V6K
XDP Connector XDP_PREQ# 1
2 RPM@
1
FAN_SPEED1
XDP_PRDY# 2 C13
3 0.01U_0402_25V7K
XDP_BPM#0 4 @
XDP_BPM#1 +3VS 2
5
6
Buffered Reset to CPU XDP_BPM#2 7
1
XDP_BPM#3 8
9 R3
H_PWRGOOD R35 1 @ 2 1K_0402_5%XDP_CPU_HOOK0 10 10K_0402_5%
+3VS PBTN_OUT# R152 1 @ 2 0_0402_5% XDP_CPU_HOOK1 11 PWM@ JFAN
<17,30> PBTN_OUT#
CFG0 R37 1 @ 2 1K_0402_5%XDP_CPU_HOOK2 12 1
<10> CFG0
2
VGATE R451 @ 0_0402_5% XDP_CPU_HOOK3 FANPWM 1
<17,30,41> VGATE 1 2 13 <30> FANPWM 2
CLK_CPU_ITP 2
<16> CLK_CPU_ITP 14 <30> FAN_SPEED1 3
CLK_CPU_ITP# +FAN1 3
1 0.1U_0402_16V4Z <16> CLK_CPU_ITP# 15 1 4 4
C84 +1.05VS_VCCP 16 C6
+1.05VS_VCCP PLT_RST# 1 @ 2 XDP_CPU_HOOK6 17 0.01U_0402_25V7K ACES_85204-0400N
PLT_RST# <19,25,26,30,31>
R40 1K_0402_5% XDP_DBRESET# 18 @ @
2 19 +5VS 2
1
U3 XDP_TDO 20 PWM@
PLT_RST# R69 XDP_TRST# +5VS D57 1SS355_SOD323-2
1
OE# 75_0402_5% XDP_TDI
21
1A R154
40 mil 1000P_0402_50V7K
5 1 22 1 2
VCC
1
C8 XDP_TMS 23 1 2 +FAN1 2 1
2 R155 0.1U_0402_10V6K 24 2 0_0603_5%
2
IN 43_0402_1% @ PWM@ D86 C4 C379

25
A
4 BUFO_CPU_RST# 1 2 BUF_CPU_RST# 2 XDP_TCK 26 C3 BAS16_SOT23-3 PWM@ PWM@ A
OUT 10U_0805_10V6K PWM@ 1 2
3 27
2
GND
1
28 PWM@ 1 10U_0805_10V6K
74AHC1G125GW_SOT353-5 R209
0_0402_5%
@ MOLEX 52435-2671 Close to Connector
2

Sandy Bridge_JTAG/XDP/FAN
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
PEG_ICOMPI and RCOMPO signals should be

+1.05VS_VCCP shorted and routed
with - max length = 500 mils - typical
1
impedance = 43 m ohm (4 mils)
R34
24.9_0402_1% PEG_ICOMPO signals should be routed with -
max length = 500 mils
JCPUA
- typical impedance = 14.5 m ohm (12 mils)
2
D J22 PEG_COMP D
PEG_ICOMPI
J21
DMI_PTX_CRX_N0 PEG_ICOMPO
<17> DMI_PTX_CRX_N0 B27 H22
DMI_PTX_CRX_N1 DMI_RX#[0] PEG_RCOMPO
<17> DMI_PTX_CRX_N1 B25
DMI_PTX_CRX_N2 DMI_RX#[1]
<17> DMI_PTX_CRX_N2 A25
DMI_PTX_CRX_N3 DMI_RX#[2]
<17> DMI_PTX_CRX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
PEG_RX#[1] M35
DMI_PTX_CRX_P0 B28 L34
<17> DMI_PTX_CRX_P0 DMI_RX[0] PEG_RX#[2]
DMI_PTX_CRX_P1 B26 J35
DMI
DMI_PTX_CRX_P2 A24 J32
DMI_PTX_CRX_P3 B23 H34
PEG_RX#[6] H31
DMI_CTX_PRX_N0 G21 G33
<17> DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7]
DMI_CTX_PRX_N1 E22 G30
DMI_CTX_PRX_N2 F21 F35
DMI_CTX_PRX_N3 D21 E34
E32
DMI_CTX_PRX_P0 PEG_RX#[11]
<17> DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33
DMI_CTX_PRX_P1 D22 D31
<17> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13]
DMI_CTX_PRX_P2 F20 B33
PCI EXPRESS* - GRAPHICS

DMI_CTX_PRX_P3 C21 C32
PEG_RX[0] J33
PEG_RX[1] L35
K34
FDI_CTX_PRX_N0 PEG_RX[2]
<17> FDI_CTX_PRX_N0 A21 H35
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3]
<17> FDI_CTX_PRX_N1 H19 H32
<17> FDI_CTX_PRX_N2 E19 G34
Intel(R) FDI
<17> FDI_CTX_PRX_N3 F18 G31
C FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] C
<17> FDI_CTX_PRX_N4 B21 F33
<17> FDI_CTX_PRX_N5 C20 F30
<17> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35
FDI_CTX_PRX_N7 E17 E33
<17> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11] F32
PEG_RX[12] D34
FDI_CTX_PRX_P0 A22 E31
<17> FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
FDI_CTX_PRX_P1 G19 C33
FDI_CTX_PRX_P2 E20 B32
FDI_CTX_PRX_P3 G18
<17> FDI_CTX_PRX_P3 FDI0_TX[3]
FDI_CTX_PRX_P4 B20 M29
<17> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
FDI_CTX_PRX_P5 C19 M32
FDI_CTX_PRX_P6 D19 M31
FDI_CTX_PRX_P7 F17 L32
L29
FDI_FSYNC0 PEG_TX#[4]
<17> FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31
<17> FDI_FSYNC1 FDI_FSYNC1 J17 K28
FDI1_FSYNC PEG_TX#[6]
J30
FDI_INT PEG_TX#[7]
<17> FDI_INT H20 J28
FDI_INT PEG_TX#[8]
H29
FDI_LSYNC0 PEG_TX#[9]
<17> FDI_LSYNC0 J19 G27
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10]
<17> FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29
PEG_TX#[12] F27
D28
PEG_TX#[13]
F26
PEG_TX#[14]
PEG_TX#[15] E25
+1.05VS_VCCP R9 1 2 24.9_0402_1% EDP_COMP A18 eDP_COMPIO
A17 eDP_ICOMPO PEG_TX[0] M28
+1.05VS_VCCP R33 2 1 10K_0402_5% B16 M33
B eDP_HPD PEG_TX[1] B
M30
PEG_TX[2]
L31
PEG_TX[3]
C15 L28
eDP_AUX PEG_TX[4]
Reserve R33 for HW Review demand D15
eDP_AUX# PEG_TX[5]
K30
eDP
K27
PEG_TX[6]
eDP_COMP signals should be PEG_TX[7]
J29
C17 J27
shorted near balls and F16
eDP_TX[0] PEG_TX[8]
H28
eDP_TX[1] PEG_TX[9]
routed with typical C16
eDP_TX[2] PEG_TX[10]
G28
G15 E28
impedance <25m ohm eDP_TX[3] PEG_TX[11]
F28
PEG_TX[12]
C18 D27
eDP_TX#[0] PEG_TX[13]
E16 E26
D16 D25
F15 eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61 @
A A

Sandy Bridge_DMI/PEG/FDI
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
JCPUC JCPUD
<11> DDR_A_D[0..63]
<12> DDR_B_D[0..63]
AB6 DDRA_CLK0 AE2 DDRB_CLK0

SA_CLK[0] DDRA_CLK0 <11> SB_CLK[0] DDRB_CLK0 <12>
AA6 DDRA_CLK0# AD2 DDRB_CLK0#
SA_CLK#[0] DDRA_CLK0# <11> SB_CLK#[0] DDRB_CLK0# <12>
DDR_A_D0 C5 V9 DDRA_CKE0 DDR_B_D0 C9 R9 DDRB_CKE0
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDRA_CKE0 <11> DDR_B_D1 SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
D5 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDRA_CLK1 DDR_B_D4 SB_DQ[3] DDRB_CLK1
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 <11> A9 SB_DQ[4] SB_CLK[1] AE1 DDRB_CLK1 <12>
D DDR_A_D5 DDRA_CLK1# DDR_B_D5 DDRB_CLK1# D
C6 SA_DQ[5] SA_CLK#[1] AB5 DDRA_CLK1# <11> A8 SB_DQ[5] SB_CLK#[1] AD1 DDRB_CLK1# <12>
DDR_A_D6 C2 V10 DDRA_CKE1 DDR_B_D6 D9 R10 DDRB_CKE1
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDRA_CKE1 <11> DDR_B_D7 SB_DQ[6] SB_CKE[1] DDRB_CKE1 <12>
C3 SA_DQ[7] D8 SB_DQ[7]
DDR_A_D8 F10 DDR_B_D8 G4
F8 F4
G10 SA_DQ[10] SA_CLK[2] AB4 F1 SB_DQ[10] SB_CLK[2] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] SA_CLK#[2] DDR_B_D12 SB_DQ[11] SB_CLK#[2]
F9 SA_DQ[12] SA_CKE[2] W9 G5 SB_DQ[12] SB_CKE[2] T9
DDR_A_D13 F7 DDR_B_D13 F5
G8 F2
G7 SA_DQ[15] G2 SB_DQ[15]
DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
DDR_A_D17 SA_DQ[16] SA_CLK[3] DDR_B_D17 SB_DQ[16] SB_CLK[3]
K5 SA_DQ[17] SA_CLK#[3] AA3 J8 SB_DQ[17] SB_CLK#[3] AB1
DDR_A_D18 K1 W10 DDR_B_D18 K10 T10
DDR_A_D19 SA_DQ[18] SA_CKE[3] DDR_B_D19 SB_DQ[18] SB_CKE[3]
J1 K9
J5 J9
J4 SA_DQ[21] J10 SB_DQ[21]
DDR_A_D22 J2 AK3 DDRA_SCS0# DDR_B_D22 K8 AD3 DDRB_SCS0#
SA_DQ[22] SA_CS#[0] DDRA_SCS0# <11> SB_DQ[22] SB_CS#[0] DDRB_SCS0# <12>
DDR_A_D23 K2 AL3 DDRA_SCS1# DDR_B_D23 K7 AE3 DDRB_SCS1#
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDRA_SCS1# <11> DDR_B_D24 SB_DQ[23] SB_CS#[1] DDRB_SCS1# <12>
M8 AG1 M5 AD6
DDR_A_D25 SA_DQ[24] SA_CS#[2] DDR_B_D25 SB_DQ[24] SB_CS#[2]
N10 AH1 N4 AE6
DDR_A_D26 SA_DQ[25] SA_CS#[3] DDR_B_D26 SB_DQ[25] SB_CS#[3]
N8 N2
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDRA_ODT0 DDR_B_D29 SB_DQ[28] DDRB_ODT0
M9 AH3 DDRA_ODT0 <11> N5 AE4 DDRB_ODT0 <12>
SA_DQ[29] SA_ODT[0] SB_DQ[29] SB_ODT[0]
DDR SYSTEM MEMORY B

DDR_A_D30 N9 AG3 DDRA_ODT1 DDR_B_D30 M2 AD4 DDRB_ODT1
DDR SYSTEM MEMORY A

DDR_A_D31 SA_DQ[30] SA_ODT[1] DDRA_ODT1 <11> DDR_B_D31 SB_DQ[30] SB_ODT[1] DDRB_ODT1 <12>
M7 AG2 M1 AD5
DDR_A_D32 SA_DQ[31] SA_ODT[2] DDR_B_D32 SB_DQ[31] SB_ODT[2]
AG6 AH2 AM5 AE5
DDR_A_D33 SA_DQ[32] SA_ODT[3] DDR_B_D33 SB_DQ[32] SB_ODT[3]
AG5 SA_DQ[33] AM6 SB_DQ[33]
DDR_A_D34 AK6 DDR_B_D34 AR3
AK5 AP3
AH5 DDR_A_DQS#[0..7] <11> AN3 DDR_B_DQS#[0..7] <12>
C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 J3 AP2 K6
DDR_A_D40 SA_DQ[39] SA_DQS#[2] SB_DQ[39] SB_DQS#[2]
AJ8 SA_DQ[40] SA_DQS#[3] M6 DDR_A_DQS#3 DDR_B_D40 AP5 SB_DQ[40] SB_DQS#[3] N3 DDR_B_DQS#3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
AJ9 AM8 DDR_A_DQS#5 DDR_B_D42 AT5 AP9 DDR_B_DQS#5
AK9 SA_DQ[43] SA_DQS#[6] AR12 DDR_A_DQS#6 DDR_B_D43 AT6 SB_DQ[43] SB_DQS#[6] AK12 DDR_B_DQS#6
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] <11> SB_DQ[48] DDR_B_DQS[0..7] <12>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
AM12 K3 AT9 J6
AM11 N6 AH11 M3
AL11 AL5 AR8 AN6
AP12 AM9 AJ12 AP8
AN12 AR11 AH12 AK11
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
AL15 AR14
AK15 DDR_A_MA[0..15] <11> AT14
AL14 AT12 DDR_B_MA[0..15] <12>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 SA_DQ[63] SA_MA[2] W2 AT15 SB_DQ[63] SB_MA[2] R7
W7 DDR_A_MA3 T6 DDR_B_MA3
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
V2 T4
W3 T3
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS0 SB_MA[6] DDR_B_MA7
<11> DDR_A_BS0 AE10 W6 <12> DDR_B_BS0 AA9 R2
B DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8 B
<11> DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 <12> DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
DDR_A_BS2 V6 W5 DDR_A_MA9 DDR_B_BS2 R6 R3 DDR_B_MA9
<11> DDR_A_BS2 SA_BS[2] SA_MA[9] DDR_A_MA10 <12> DDR_B_BS2 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_CAS# SB_MA[12] DDR_B_MA13
<11> DDR_A_CAS# AE8 AF8 <12> DDR_B_CAS# AA10 AB10
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
<11> DDR_A_RAS# AD9 V5 <12> DDR_B_RAS# AB8 R5
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
<11> DDR_A_WE# AF9 V7 <12> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]
Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @
+1.5V
R466
1
0_0402_5%
1 2 R465
WPS3@ 1K_0402_5%
PS3@
R467
2
1K_0402_5%
S
H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2
<5> H_DRAMRST# SM_DRAMRST# <11,12>
Q14
2
BSS138_NL_SOT23-3
R464 PS3@
G
2
4.99K_0402_1%
A A
1
<16> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

R463 0_0402_5%
PS3@ 1
C140 Security Classification Compal Secret Data Compal Electronics, Inc.
0.047U_0402_25V6K Issued Date 2010/09/03 2012/12/31 Title
PS3@
Deciphered Date
2
Sandy Bridge_DDR3
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+CPU_CORE
JCPUF POWER +1.05VS_VCCP Decoupling:

2X 330U (6m ohm), 12X 22U
94A (Quad Core 45W) +1.05VS_VCCP
53A (SV 35W) 8.5A TOP Socket Cavity x 7
D D
AG35
VCC1 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AG34 AH13
VCC2 VCCIO1
AG33 AH10 1 1 1 1 1 1 1 1 1 1
VCC3 VCCIO2 C146 C144 C143 C141 C137 C136 C135 C134 C133 C142
AG32 AG10
VCC4 VCCIO3
AG31
AG30
VCC5 VCCIO4
AC10
Y10
+CPU_CORE Decoupling:
VCC6 VCCIO5 2 2 2 2 2 2 2 2 2 2
AG29
VCC7 VCCIO6
U10 4X 470U (4m ohm), 16X 22U, 10X 10U
AG28 P10
VCC8 VCCIO7 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10 22U_0805_6.3V6M
AF34
AF33
VCC12 VCCIO11
J12
J11 1 1
Bottom Socket Cavity
VCC13 VCCIO12 C147 C145
AF32 H14
VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14 +CPU_CORE
AF30 H11
VCC16 VCCIO15 2 2
AF29 G14
VCC17 VCCIO16
AF28 G13
PEG AND DDR
VCC18 VCCIO17 22U_0805_6.3V6M 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K

AF27 G12
VCC19 VCCIO18
AF26 F14
VCC20 VCCIO19
AD35 F13 1 1 1 1 1 1 1 1 1 1 1
VCC21 VCCIO20 C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111
AD34 F12
VCC22 VCCIO21 330U_D2_2V_Y
AD33 F11
VCC23 VCCIO22 @
AD32 E14
VCC24 VCCIO23 ESR 9mohm 2 2 2 2 2 2 2 2 2 2 2
AD31 E12 1 1
VCC25 VCCIO24
AD30
AD29
VCC26
E11
Bottom Socket Cavity x 5 C10 + C11 + 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
VCC27 VCCIO25
AD28 D14
VCC28 VCCIO26 330U_D2_2V_Y
AD27 D13
VCC29 VCCIO27 2 2
AD26 D12
VCC30 VCCIO28
AC35 D11
C VCC31 VCCIO29 C
AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 C12
VCC34 VCCIO32
AC31 C11
VCC35 VCCIO33
AC30 B14
VCC36 VCCIO34
AC29 B12
VCC37 VCCIO35
AC28 A14
VCC38 VCCIO36
AC27
AC26
VCC39 VCCIO37
A13
A12
Top Socket Edge
VCC40 VCCIO38 +CPU_CORE
AA35 A11
VCC41 VCCIO39
AA34
VCC42
AA33 J23
VCC43 VCCIO40 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA32
VCC44
AA31
VCC45
AA30 1 1 1 1 1 1 1 1 1
VCC46 C159 C151 C130 C129 C124 C123 C122 C121 C125
AA29
VCC47
AA28
VCC48 @
AA27
VCC49 2 2 2 2 2 2 2 2 2
AA26
CORE SUPPLY
VCC50
Y35
VCC51 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y34
VCC52
Y33
VCC53 +1.05VS_VCCP +1.05VS_VCCP
Y32
VCC54
Y31
VCC55
Y30
VCC56
1
Y29
VCC57 R70 R68
Y28
VCC58 130_0402_5% 75_0402_5%
Y27
VCC59
Y26
V35
VCC60 Top Socket Cavity
SVID
VCC61 H_CPU_SVIDALRT#
V34 AJ29 1 2 VR_SVID_ALRT# <41>
VCC62 VIDALERT# H_CPU_SVIDCLK R67 1 +CPU_CORE
V33 AJ30 2 43_0402_1% VR_SVID_CLK <41>
VCC63 VIDSCLK H_CPU_SVIDDAT R63 1
B V32 AJ28 2 0_0402_5% VR_SVID_DAT <41>
B
VCC64 VIDSOUT R66 0_0402_5%
V31
VCC65 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
V30
VCC66 Pull high resistor on VR side
V29
VCC67
V28 1 1 1 1 1 1 1 1
VCC68 C158 C150 C128 C127 C120 C118 C119 C117
V27
VCC69
V26
VCC70
U35
VCC71 2 2 2 2 2 2 2 2
U34
VCC72
U33
VCC73 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78 +CPU_CORE
U27
VCC79
U26
R35
VCC80 Bottom Socket Edge
VCC81
R34
VCC82
2
R33
VCC83 R64 +CPU_CORE
R32
VCC84 Close to CPU
R31 100_0402_1%
VCC85 330U_D2_2V_Y 330U_D2_2V_Y
R30
VCC86
R29
1
SENSE LINES
VCC87
R28 1 1 1 1 1
VCC88
R27 AJ35 VCCSENSE_R R65 1 2 0_0402_5% VCCSENSE <41>
VCC89 VCC_SENSE + + + + +
R26 AJ34 VSSSENSE_R R52 1 2 0_0402_5% VSSSENSE <41>
C2 C5 C7 C9 C1
VCC90 VSS_SENSE
P35
VCC91 330U_D2_2V_Y
P34
VCC92
1
P33 2 2 2 2 2
VCC93 VCCIO_SENSE R62
P32 B10 VCCIO_SENSE <40>
VCC94 VCCIO_SENSE 100_0402_1% 330U_D2_2V_Y 330U_D2_2V_Y
P31 A10
VCC95 VSSIO_SENSE
P30
VCC96
2
A A
P29 VSS_SENSE_VCCIO
2
VCC97 R102 R105

P28
VCC98 100_0402_1%
P27 0_0402_5%
VCC99 @
P26
VCC100
1
+1.05VS_VCCP
Close to CPU Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title
Sandy Bridge_POWER-1
Sandy Bridge_rPGA_Rev0p61 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+GFX_CORE Decoupling: +GFX_CORE

1X 560U (10m ohm), 12X 22U
2
+GFX_CORE
Change C873 from 330uF to 560uF for power issue

JCPUG
POWER R74
100_0402_1%
Close to CPU
Bottom Socket Edge
1
SENSE
LINES
AT24 AK35 VCC_AXG_SENSE
VAXG1 VAXG_SENSE VSS_AXG_SENSE VCC_AXG_SENSE <41>
D
ESR 10mohm AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE <41> D
1 AT21 VAXG3
AT20 VAXG4
1
C873 + AT18 IF PS3@, short PJ32.
560U_2.5V_M_R17 VAXG5 R75
AT17 VAXG6 33A +V_SM_VREF should PJ32
AR24 100_0402_1%
2 VAXG7 have 20 mil trace width
AR23 VAXG8 1 1 2 2 +1.5VS
AR21 R111 @
2
VAXG9 0_0402_5%
AR20 VAXG10 JUMP_43X118
VREF
AR18 VAXG11 2 1
AR17 VAXG12
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AP24 AL1 +V_SM_VREF_CNT 2 3 +V_SM_VREF 1 2
VAXG13 SM_VREF +1.5V_CPU
AP23 VAXG14
1
1 1 1 1 1 1 AP21 1 Q2 1K_0402_5%
C266 C267 C271 C338 C341 C342 VAXG15 R486 C148 @ R252 R122
AP20 VAXG16
AP18 @ AP2302GN-HF_SOT23-3 1K_0402_5%
VAXG17 1
100K_0402_5%
0.1U_0402_16V4Z
2 2 2 2 2 2
AP17
AN24
VAXG18 2 +1.5V_CPU Decoupling:
2
VAXG19
Bottom Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AN23 VAXG20
RUN_ON_CPU1.5VS3 1X 330U (17m ohm), 6X 10U
AN21 VAXG21
Cavity AN20 VAXG22
+1.5V_CPU
DDR3 -1.5V RAILS

Bottom Socket Edge AN18 VAXG23
AN17 VAXG24 5A
GRAPHICS
AM24 AF7 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M VAXG25 VDDQ1
AM23 VAXG26 VDDQ2 AF4 1
AM21 VAXG27 VDDQ3 AF1 1 1 1 1 1 1
AM20 AC7 C114 C115 C116 C149 C154 C155 + C875
1 1 1 1 1 1 VAXG28 VDDQ4
C343 C344 C345 C346 C347 C348 AM18 AC4 330U_2.5V_M_R17
VAXG29 VDDQ5 ESR 17mohm
AM17 VAXG30 VDDQ6 AC1
AL24 Y7 2 2 2 2 2 2 2
2 2 2 2 2 2 VAXG31 VDDQ7
AL23 VAXG32 VDDQ8 Y4
10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K
C Top Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AL21
AL20
VAXG33 VDDQ9 Y1
U7 C
VAXG34 VDDQ10
Cavity AL18 VAXG35 VDDQ11 U4
Top Socket Edge AL17
AK24
VAXG36 VDDQ12 U1
P7
VAXG37 VDDQ13
AK23 VAXG38 VDDQ14 P4
22U_0805_6.3V6M 22U_0805_6.3V6M AK21 P1
VAXG39 VDDQ15
AK20 VAXG40
1 1 1 1 AK18 VAXG41
C349 C350 C351 C391 AK17 VAXG42
@ @ @ @
AJ24
AJ23
VAXG43 +VCCSA Decoupling:
2 2 2 2 VAXG44
AJ21 VAXG45 1X 330U (17m ohm), 4X 10U
AJ20 VAXG46
22U_0805_6.3V6M 22U_0805_6.3V6M AJ18 VAXG47 +VCCSA
VCCSA_VID0 VCCSA_VID1 +VCCSA
AJ17 VAXG48 Bottom Socket Cavity
AH24 6A
SA RAIL
VAXG49
AH23 VAXG50 0 0 0.90 V For Sandy Bridge
AH21 VAXG51 VCCSA1 M27 10U_0805_10V6K 10U_0805_10V6K 1 2VCCSA_SENSE
AH20 M26 R253 0_0402_5%
VAXG52 VCCSA2
AH18 VAXG53 VCCSA3 L26 1 0 1 0.80 V
AH17 VAXG54 VCCSA4 J26 1 1 1 1
J25 C100 C447 C476 C477 + C877
VCCSA5
VCCSA6 J24 330U_2.5V_M_R17 1 0 0.75 V
H26 @ @ ESR 17mohm
VCCSA7 2 2 2 2 2
VCCPLL Decoupling: VCCSA8 H25
1 1 0.65 V
1.8V RAIL
+1.8VS
1X 330U (6m ohm), 1X 10U, 2x1U 10U_0805_10V6K 10U_0805_10V6K
1.2A Bottom Socket Edge

R76
2 1 10U_0805_10V6K +1.8VS_VCCPLL B6 H23 VCCSA_SENSE
VCCPLL1 VCCSA_SENSE VCCSA_SENSE <39>
MISC
B 0_0805_5% A6 R95 B
VCCPLL2
1 A2 VCCPLL3 1 2
C185 1 1 1 VCCSA_VID0 0_0402_5% @
@+ C186 C206 C230 C22 VCCSA_VID0
FC_C22
VCCSA_VID1 C24 VCCSAP_VID1 <39>
1U_0402_6.3V6K
2
2
2 2 2 2
R114 R119 IF WPS3@, short PJ30.
330U_B2_2.5VM_R15M 1U_0402_6.3V6K Sandy Bridge_rPGA_Rev0p61 @ @
10K_0402_5% 10K_0402_5%
+1.5V_CPU +1.5V
1
1
PJ30 @
2 2 1 1
+1.5V_CPU +1.5V
JUMP_43X118
PS3@ Vgs=10V,Id=14.5A,Rds=6mohm
C213 1 2 0.1U_0402_16V4Z Q33 @
PS3@ 1 8
C212 1 S D
2 0.1U_0402_16V4Z 2 S D 7
2
PS3@ 1 3 6
C211 1 S D
2 0.1U_0402_16V4Z R449 C179 4 G D 5
PS3@ 470_0805_5% 10U_0805_10V4K
C210 1 2 0.1U_0402_16V4Z @ @ FDS6676AS_SO8 R455 @
2 RUN_ON_CPU1.5VS3 1 2 +VSB
3 1
220K_0402_5%
6
1
C472 R420
SUSP 5 0.1U_0402_25V6 820K_0402_5%
Q46B @ @ 2 SUSP SUSP <5,25,33,40>
2N7002DW-T/R7_SOT363-6 2 Q46A
2
A @ 2N7002DW-T/R7_SOT363-6 A
1
@

Sandy Bridge_POWER-2
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

JCPUH JCPUI JCPUE (CFG[17:0] internal pull high to VCCIO)
AT35 AJ22
VSS1 VSS81
AT32 AJ19 L7
VSS2 VSS82 RSVD28 CFG2
AT29 AJ16 T35 F22 AG7
VSS3 VSS83 VSS161 VSS234 CFG0 RSVD29
AT27 AJ13 T34 F19 <5> CFG0 AK28 AE7
VSS4 VSS84 VSS162 VSS235 CFG[0] RSVD30
1
AT25 AJ10 T33 E30 T5 PAD CFG1 AK29 AK2
VSS5 VSS85 VSS163 VSS236 T6 PAD CFG2 CFG[1] RSVD31 R254
AT22 AJ7 T32 E27 AL26 W8
VSS6 VSS86 VSS164 VSS237 T7 PAD CFG3 CFG[2] RSVD32 1K_0402_1%
AT19 AJ4 T31 E24 AL27
VSS7 VSS87 VSS165 VSS238 T11 PAD CFG4 CFG[3] @
AT16 AJ3 T30 E21 AK26
VSS8 VSS88 VSS166 VSS239 T12 PAD CFG5 CFG[4]
AT13 AJ2 T29 E18 AL29 AT26
2
VSS9 VSS89 VSS167 VSS240 T15 PAD CFG6 CFG[5] RSVD33
AT10 AJ1 T28 E15 AL30 AM33
D AT7 AH35 T27 E13 AM31 AJ27 D
AT4 AH34 T26 E10 AM32
AT3 AH32 P9 E9 AM30
AR25 AH30 P8 E8 AM28
AR22 AH29 P6 E7 AM26
VSS15 VSS95 VSS173 VSS246 T44 PAD CFG[11]
AR19
VSS16 VSS96
AH28 P5
VSS174 VSS247
E6 CFG12 AN28
CFG[12]
PEG Static Lane Reversal - CFG2 is for the 16x
AR16 AH26 P3 E5 T45 PAD CFG13 AN31 T8
AR13 AH25 P2 E4 AN26 J16
AR10 AH22 N35 E3 AM27 H16 1: Normal Operation; Lane # definition matches
AR7
AR4
VSS19
VSS20
VSS21
VSS99
VSS100
VSS101
AH19
AH16
N34
N33
VSS177
VSS178
VSS179
VSS250
VSS251
VSS252
E2
E1
T26 PAD
T27 PAD
CFG16
CFG17
AK31
AN29
CFG[15]
CFG[16]
CFG[17]
RSVD39
RSVD40
G16
CFG2
* socket pin map definition
AR2 AH7 N32 D35
VSS22 VSS102 VSS180 VSS253
AP34
VSS23 VSS103
AH4 N31
VSS181 VSS254
D32 0:Lane Reversed
AP31 AG9 N30 D29
AP28 AG8 N29 D26 AR35
VSS25 VSS105 VSS183 VSS256 T22 PAD RSVD41 CFG4
AP25 AG4 N28 D20 AJ31 AT34
VSS26 VSS106 VSS184 VSS257 T24 PAD RSVD1 RSVD42
AP22 AF6 N27 D17 AH31 AT33
VSS27 VSS107 VSS185 VSS258 RSVD2 RSVD43
1
AP19 AF5 N26 C34 T25 PAD AJ33 AP35
VSS28 VSS108 VSS186 VSS259 T23 PAD RSVD3 RSVD44 R255
AP16 AF3 M34 C31 AH33 AR34
VSS29 VSS109 VSS187 VSS260 RSVD4 RSVD45 1K_0402_1%
AP13 AF2 L33 C28
VSS30 VSS110 VSS188 VSS261 @
AP10 AE35 L30 C27
AP7 AE34 L27 C25 AJ26
2
VSS32 VSS112 VSS190 VSS263 RSVD5
RESERVED
AP4 AE33 L9 C23
AP1 AE32 L8 C10
AN30
VSS35 VSS115
AE31 L6
VSS193 VSS266
C1 SA_DIMM_VREFDQ RSVD46
B34
AN27 AE30 L5 B22 CPU_RSVD6 B4 A33
VSS36 VSS116 VSS194 VSS267 CPU_RSVD7 RSVD6 RSVD47
AN25 AE29 L4 B19 D1 A34
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
AE28
AE27
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
RSVD7
SB_DIMM_VREFDQ RSVD48
RSVD49
RSVD50
B35
C35 Embedded Display Port Presence Strap
1
AN16 AE26 L1 B13
AN13 AE9 K35 B11 F25
VSS41 VSS121 VSS199 VSS272 R115 R116 RSVD8
AN10 AD7 K32 B9 F24 1 : Disabled; No Physical Display Port
C
AN7
AN4
VSS42
VSS43
VSS122
VSS123
AC9
AC8
K29
K26
VSS200
VSS201
VSS273
VSS274
B8
B7
1K_0402_1% 1K_0402_1% F23
D24
RSVD9
RSVD10
AJ32
* attached to Embedded Display Port
C
2
AM29
VSS45 VSS125
AC6 J34
VSS203 VSS276
B5 G25
RSVD12 RSVD52
AK32 CFG4
AM25
VSS46 VSS126
AC5 J31
VSS204 VSS277
B3 G24
RSVD13 0 : Enabled; An external Display Port device is
AM22 AC3 H33 B2 E23 connected to the Embedded Display Port
AM19 AC2 H30 A35 D23
AM16 AB35 H27 A32 C30 AH27
VSS49 VSS129 VSS207 VSS280 RSVD16 RSVD53 T28 PAD
AM13 AB34 H24 A29 A31
AM10 AB33 H21 A26 B30
VSS51 VSS131 VSS209 VSS282 RSVD18 CFG6
AM7 AB32 H18 A23 B29
AM4 AB31 H15 A20 D30 AN35 CLK_RES_ITP <16>
VSS53 VSS133 VSS211 VSS284 RSVD20 RSVD54 CFG5
AM3 AB30 H13 A3 B31 AM35 CLK_RES_ITP# <16>
AM2 AB29 H10 A30
VSS55 VSS135 VSS213 RSVD22
1
AM1 AB28 H9 C29
VSS56 VSS136 VSS214 RSVD23 R257 R256
AL34 AB27 H8
VSS57 VSS137 VSS215 1K_0402_1% 1K_0402_1%
AL31 AB26 H7
VSS58 VSS138 VSS216 @ @
AL28 Y9 H6 J20
AL25 Y8 H5 B18 AT2
2
VSS60 VSS140 VSS218 RSVD25 RSVD56
AL22 Y6 H4 A19 AT1
VSS61 VSS141 VSS219 RSVD26 RSVD57
AL19
VSS62 VSS142
Y5 H3
VSS220
VCCIO_SEL RSVD58
AR1
AL16 Y3 H2
VSS63 VSS143 VSS221
AL13 Y2 H1 J15
AL10 W35 G35
VSS65 VSS145 VSS223
AL7 W34 G32
VSS66 VSS146 VSS224
AL4 W33 G29 B1
VSS67 VSS147 VSS225 KEY
AL2 W32 G26
VSS68 VSS148 VSS226
AK33
VSS69 VSS149
W31 G23
VSS227 PCIE Port Bifurcation Straps
AK30 W30 G20
VSS70 VSS150 VSS228
AK27 W29 G17
VSS71 VSS151 VSS229
AK25 W28 G11 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
AK22
AK19
VSS72
VSS73
VSS74
VSS152
VSS153
VSS154
W27
W26
F34
F31
VSS230
VSS231
VSS232
Sandy Bridge_rPGA_Rev0p61 @ *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
AK16 U9 F29 disabled
VSS75 VSS155 VSS233
AK13
VSS76 VSS156
U8 CFG[6:5]
AK10
VSS77 VSS157
U6 01: Reserved - (Device 1 function 1 disabled ; function
AK7 U5 2 enabled)
VSS78 VSS158
AK4 U3
VSS79 VSS159
AJ25
VSS80 VSS160
U2 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @ CFG7
1
R258
1K_0402_1%
@
2
PEG DEFER TRAINING
1: (Default) PEG Train immediately following xxRESETB

de assertion
CFG7
0: PEG Wait for BIOS for training
A A

Sandy Bridge_GND/RSVD/CFG
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
JDDRL DDR3 SO-DIMM A
1 2
+VREF_DQA
DDR_A_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_A_D4
DDR_A_D5
Reverse Type DDR_A_DQS[0..7] <7>
5 DQ0 DQ5 6 DDR_A_DQS#[0..7] <7>

1 1 DDR_A_D1 7 8
C156 C157 DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] <7>
11 12 DDR_A_DQS0
DM0 DQS0
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
13 VSS VSS 14 DDR_A_MA[0..15] <7>
2 2 DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
D
23 DQ9 DQ13 24 D
25 VSS VSS 26
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS1# DM1 SM_DRAMRST#
Close to JDDRL.1 29 DQS1 RESET# 30 SM_DRAMRST# <7,12> +1.5V
31 VSS VSS 32
35 DQ11 DQ15 36
1
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20 R79
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46
2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48 +VREF_DQA
49 50 DDR_A_D22
VSS DQ22
1
DDR_A_D19 DQ18 DQ23 R81
53 DQ19 VSS 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
2
DQ25 VSS DDR_A_DQS#3
61 VSS DQS3# 62
63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
69 DQ27 DQ31 70
71 VSS VSS 72
DDRA_CKE0 73 74 DDRA_CKE1
<7> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <7>
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
C
<7> DDR_A_BS2 79 BA2 A14 80 C
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
DDRA_CLK0 101 102 DDRA_CLK1
<7> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <7>
DDRA_CLK0# 103 104 DDRA_CLK1#
<7> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <7>
105 VDD VDD 106
DDR_A_MA10 DDR_A_BS1 +1.5V
107 A10/AP BA1 108 DDR_A_BS1 <7>
DDR_A_BS0 109 110 DDR_A_RAS#
<7> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <7>
111 VDD VDD 112
1
DDR_A_WE# 113 114 DDRA_SCS0#
<7> DDR_A_WE# W E# S0# DDRA_SCS0# <7>
DDR_A_CAS# 115 116 DDRA_ODT0 R80
<7> DDR_A_CAS# CAS# ODT0 DDRA_ODT0 <7>
117 118 1K_0402_1%
DDR_A_MA13 VDD VDD DDRA_ODT1
119 A13 ODT1 120 DDRA_ODT1 <7>
DDRA_SCS1# 121 122
2
<7> DDRA_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAA
TEST VREF_CA
127 VSS VSS 128
1
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37 R82
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_A_DQS#4 VSS VSS
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1
2
B DQS4 VSS DDR_A_D38 C161 C162 B
139 VSS DQ38 140
DDR_A_D34 141 142 DDR_A_D39
DQ34 DQ39
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
DDR_A_D35 143 144

DQ35 VSS DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
DDR_A_DQS#5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
151 VSS DQS5# 152
153 154 DDR_A_DQS5 Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
DM5 DQS5
155 VSS VSS 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160 close to JDDRL.126 +1.5V
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 @ +1.5V +0.75VS
DDR_A_D49 DQ48 DQ52 DDR_A_D53 C218 1 2 390U_2.5V_M_R10
+
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_A_DQS#6 169 170 C164 1 2 0.1U_0402_16V4Z C165 1 2 10U_0603_6.3V6M
DDR_A_DQS6 DQS6# DM6 C166 1
171 DQS6 VSS 172 2 10U_0603_6.3V6M
173 174 DDR_A_D54 C167 1 2 0.1U_0402_16V4Z
DDR_A_D50 VSS DQ54 DDR_A_D55 C168 1
175 DQ50 DQ55 176 2 10U_0603_6.3V6M C169 2 1 1U_0402_6.3V6K
DDR_A_D51 177 178 C170 1 2 0.1U_0402_16V4Z
DQ51 VSS DDR_A_D60 C171 1
179 VSS DQ60 180 2 10U_0603_6.3V6M C172 2 1 1U_0402_6.3V6K
DDR_A_D56 181 182 DDR_A_D61 C173 1 2 0.1U_0402_16V4Z
DDR_A_D57 DQ56 DQ61 C174 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M C175 2 1 1U_0402_6.3V6K
185 186 DDR_A_DQS#7
VSS DQS7# DDR_A_DQS7 C176 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M C177 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62 C178 1 2 10U_0603_6.3V6M
193 DQ59 DQ63 194
R90 1 2 195 196
10K_0402_5% VSS VSS
A 197 SA0 EVENT# 198 A
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <12,16,25>
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <12,16,25>
1 1 +0.75VS 203 VTT VTT 204 +0.75VS
1
C181 C182
205 GND1 BOSS1 206
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
R91 207 208

2 2 10K_0402_5% GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
2
FOX_AS0A626-U2SN-7F_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
A B C D E
+1.5V +1.5V
JDDRH
1 2
+VREF_DQB
DDR_B_D0
3
VREF_DQ
VSS
VSS
DQ4 4 DDR_B_D4
DDR_B_D5
Reverse Type
5 6
DDR_B_D1 7
DQ0
DQ1
DQ5
VSS 8
DDR_B_DQS#0
DDR3 SO-DIMM B
9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0
1 1 13 VSS VSS 14
C183 C184 DDR_B_D2 15 16 DDR_B_D6 DDR_B_DQS#[0..7] <7>
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
19 VSS VSS 20 DDR_B_DQS[0..7] <7>
2 2 DDR_B_D8 21 22 DDR_B_D12
1
23 DQ9 DQ13 24 DDR_B_D[0..63] <7> 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_MA[0..15] <7>
DDR_B_DQS1 DQS1# DM1 SM_DRAMRST#
29 DQS1 RESET# 30 SM_DRAMRST# <7,11>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
Close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 DDR_B_D20 +1.5V
39 DQ16 DQ20 40
DQ17 DQ21
43 VSS VSS 44
1
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2 R83
47 DQS2 VSS 48
49 50 DDR_B_D22 1K_0402_1%
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
2
DQ19 VSS DDR_B_D28
55 VSS DQ28 56 +VREF_DQB
DQ24 DQ29
1
DDR_B_D25 59 60
DQ25 VSS DDR_B_DQS#3 R84
61 VSS DQS3# 62
63 64 DDR_B_DQS3 1K_0402_1%
DM3 DQS3
65 VSS VSS 66
2
69 DQ27 DQ31 70
71 VSS VSS 72
DDRB_CKE0 73 74 DDRB_CKE1
<7> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <7>
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
2
<7> DDR_B_BS2 79 BA2 A14 80 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDRB_CLK0 101 102 DDRB_CLK1
<7> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <7>
DDRB_CLK0# 103 104 DDRB_CLK1#
<7> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <7>
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 <7>
DDR_B_BS0 109 110 DDR_B_RAS#
<7> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <7>
111 VDD VDD 112
1
DDR_B_WE# 113 114 DDRB_SCS0#
<7> DDR_B_WE# W E# S0# DDRB_SCS0# <7>
DDR_B_CAS# 115 116 DDRB_ODT0 R86
<7> DDR_B_CAS# CAS# ODT0 DDRB_ODT0 <7>
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDRB_ODT1
119 A13 ODT1 120 DDRB_ODT1 <7>
DDRB_SCS1# 121 122
2
<7> DDRB_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAB
TEST VREF_CA
127 VSS VSS 128
1
DDR_B_D37 129 130 DDR_B_D32
DDR_B_D36 DQ32 DQ36 DDR_B_D33 R94
131 DQ33 DQ37 132
133 134 1K_0402_1%
DDR_B_DQS#4 VSS VSS
135 DQS4# DM4 136 1 1
DDR_B_DQS4 137 138 C187 C188
2
3 DQS4 VSS DDR_B_D38 3
139 VSS DQ38 140
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
DDR_B_D34 141 142 DDR_B_D39

DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS 144
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
151 VSS DQS5# 152
DDR_B_DQS5
Layout Note: Layout Note: Place these 4 Caps near Layout Note:
153 DM5 DQS5 154
155 VSS VSS 156 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
DDR_B_D42 157 158 DDR_B_D46 Close to JDDRH.126
159 DQ43 DQ47 160
161 162 +1.5V
DDR_B_D48 VSS VSS DDR_B_D52 +1.5V +0.75VS
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 VSS VSS 168
DDR_B_DQS#6 169 170 C190 1 2 0.1U_0402_16V4Z C191 1 2 10U_0603_6.3V6M
DDR_B_DQS6 DQS6# DM6 C192 1
171 DQS6 VSS 172 2 10U_0603_6.3V6M
173 174 DDR_B_D50 C193 1 2 0.1U_0402_16V4Z
DDR_B_D54 VSS DQ54 DDR_B_D51 C194 1
175 DQ50 DQ55 176 2 10U_0603_6.3V6M C195 2 1 1U_0402_6.3V6K
DDR_B_D55 177 178 C196 1 2 0.1U_0402_16V4Z
DQ51 VSS DDR_B_D60 C197 1
179 VSS DQ60 180 2 10U_0603_6.3V6M C198 2 1 1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61 C199 1 2 0.1U_0402_16V4Z
DDR_B_D57 DQ56 DQ61 C200 1
183 DQ57 VSS 184 2 10U_0603_6.3V6M C201 2 1 1U_0402_6.3V6K
185 186 DDR_B_DQS#7
VSS DQS7# DDR_B_DQS7 C202 1
187 DM7 DQS7 188 2 10U_0603_6.3V6M C203 2 1 1U_0402_6.3V6K
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 C204 1 2 10U_0603_6.3V6M
193 DQ59 DQ63 194
R98 1 2 195 196
10K_0402_5% VSS VSS
4 197 SA0 EVENT# 198 4
199 200 PM_SMBDATA
+3VS VDDSPD SDA PM_SMBDATA <11,16,25>
201 202 PM_SMBCLK
SA1 SCL PM_SMBCLK <11,16,25>
1 1 1 R99 2 +0.75VS 203 VTT VTT 204 +0.75VS
C207 C208 10K_0402_5%
@ @ 205 206
GND1 BOSS1
2.2U_0603_6.3V6K
0.1U_0402_16V4Z
207 208
2 2 GND2 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
FOX_AS0A626-UASN-7F_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
Custom 1.0
PWWHA LA-7202P M/B
A B C D E
A B C D E F G H
+LCD_VDD +3VS
Reserve for EMI request
1
R107
1 @ 2 150_0603_5% R108
R78 0_0402_5% 100K_0402_5% +3VS
L55 CAM@
2
1 1 USB20_P11_R
<19> USB20_P11 2 2
2
6
<19> USB20_N11 4 3 USB20_N11_R 2 W=60mils
1 4 3 Q1A C228
1
WCM-2012-900T_0805 2N7002DW-T/R7_SOT363-6 2 0.1U_0402_16V7K
3
S
Q17
1 @ 2 1 1 2
R109 2 LCDPWR_GATE
G
AO3413_SOT23
1
R96 0_0402_5% 47K_0402_5% 1
3
D
1
LCD_EDID_CLK C229 +LCD_VDD
<18> LCD_EDID_CLK
0.01U_0402_25V7K W=60mils
LCD_EDID_DATA UMA_ENVDD 5 2
<18> LCD_EDID_DATA <18> UMA_ENVDD
D2 Q1B 1
2 1 LED_PWM 2N7002DW-T/R7_SOT363-6 C233
<18> PCH_PWM
4
0.1U_0402_16V4Z
2
RB751V40_SC76-2
R120 R112 2
47K_0402_5% 100K_0402_5%
Close to LVDS Connector
1
LCD/PANEL BD. Conn.
W=20mils CAM@
CAM@ 0.1U_0402_16V4Z
+3VS 1 2+3VS_LVDS_CAM 1 2
R388 0_0603_5% C225
2 2
D84 @
JLVDS @ 2
1 1 1
31 G1 2 2 3
32 3 USB20_N11_R
G2 3 USB20_P11_R PACDN042Y3R_SOT23-3
33 G3 4 4
34 G4 5 5
6 INT_MIC_CLK
6 INT_MIC_CLK <28>
7 INT_MIC_DATA 1.5A L15
7 INT_MIC_DATA <28>
8 +LCD_VDD_R 2 1 +LCD_VDD
8 0_0805_5%
9 9 1 1
10 10 +3VS
11 LCD_EDID_CLK C226 C227
11 LCD_EDID_DATA 0.1U_0402_16V4Z 4.7U_0805_10V4Z
12 12
Pin13 is GND pin but LVDS cable is NC. 2 2
13 13 For EMI
14 14 LCD_TXOUT0- <18> 1 1
15 LCD_TXOUT0+ <18> @
15 C231 C232
16 16
17 LCD_TXOUT1- <18> 680P_0402_50V7K 0.1U_0402_16V4Z
17 2 2
18 18 LCD_TXOUT1+ <18>
19 19
20 20 LCD_TXOUT2- <18>
21 21 LCD_TXOUT2+ <18>
22 22
23 23 LCD_TXCLK- <18>
24 24 LCD_TXCLK+ <18>
25 LED_PWM
25 BKOFF#_R D1
26 26 1 2 BKOFF# <30>
27 RB751V40_SC76-2
3 27 3
28 28 1 2
29 R113 10K_0402_5%
29
30 30
ACES_88341-3001 +LCD_INV B+
Rated Current MAX:600mA
2 1 L2
1 1 FBMA-L11-201209-221LMA30T_0805
C234 C235
68P_0402_50V8J 0.1U_0402_25V6
2 2
4 4

LVDS
Custom 1.0
PWWHA LA-7202P M/B
A B C D E F G H
A B C D E
CRT CONNECTOR
1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils
3
1 1 2
1 3 RB491D_SOT23-3 1 1
1.1A_6V_MINISMDC110F-2
C237
0.1U_0402_16V4Z
L3 2
<18> UMA_CRT_R 1 2 NBQ100505T-800Y_0402 CRT_R_L @
<18> UMA_CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
<18> UMA_CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
JCRT @
6 6
T76 PAD 11
R138 R139 R140 CRT_R_L 11
1
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
1
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 7 7
1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 12
2 2
8 8
2 2 2 2 2 2 HSYNC 13 13
CRT_B_L 3
2
3
+CRT_VCC 9 9
VSYNC 14 16
T77 PAD 14 G
4 4 G 17
10 10
CRT_DDC_CLK 15 15
5 5
ALLTO_C10532-11505-L_15P-T
2 2
+CRT_VCC
1 2
C244 0.1U_0402_16V4Z 2 1
R141 10K_0402_5%
5
1
OE#
P
2 4 D_CRT_HSYNC 1 2 HSYNC
<18> UMA_CRT_HSYNC A Y
+CRT_VCC L6 10_0402_5%
G
U6
SN74AHCT1G125GW _SOT353-5
5
1OE#
P
2 4 D_CRT_VSYNC 1 2 VSYNC
<18> UMA_CRT_VSYNC A Y L7 10_0402_5%
10P_0402_50V8J
10P_0402_50V8J
1 1
G
U7
SN74AHCT1G125GW _SOT353-5 C245 C246
3
@ @
2 2
3 3
+CRT_VCC
+3VS
2
R153 R159
4.7K_0402_5% 4.7K_0402_5%
1
2
Q205A
<18> UMA_CRT_CLK 5 1 6 CRT_DDC_CLK
2N7002DW -T/R7_SOT363-6
Q205B
<18> UMA_CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW -T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @
4 4

CRT
1.0
PWWHA LA-7202P M/B
A B C D E
5 4 3 2 1
U2A
CMOS Setting, near DDR Door JCOMS @ PCH_RTCX1 LPC_AD0
2 1 A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 <30,31>
+RTCVCC R292 1 2 PCH_RTCRST# 1 2 C216 15P_0402_50V8J A38 LPC_AD1
LPC
FWH1 / LAD1 LPC_AD1 <30,31>
20K_0402_5% Y3 PCH_RTCX2 C20 B37 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 <30,31>
1
10M_0402_5%
C247 2 1 2 1 C37 LPC_AD3
NC OSC FWH3 / LAD3 LPC_AD3 <30,31>
1U_0402_6.3V6K PCH_RTCRST# D20 RTCRST#
R291
3 4 D36 LPC_FRAME#
NC OSC FWH4 / LFRAME# LPC_FRAME# <30,31>
PCH_SRTCRST# G22
32.768KHZ_12.5PF_Q13MC14610002 SRTCRST# +3VS
iME Setting. E36
RTC
2
JME @ SM_INTRUDER# LDRQ0#
2 1 K22 K36
R293 1 INTRUDER# LDRQ1# / GPIO23
2PCH_SRTCRST# 1 2 C205 15P_0402_50V8J
20K_0402_5% PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 2 1
INTVRMEN SERIRQ SERIRQ <30,31>
C248 2 1 R136 10K_0402_5%
1U_0402_6.3V6K
AM3 SATA_PRX_C_DTX_N0
SATA0RXN SATA_PRX_C_DTX_N0 <24>
D R286 1 2 33_0402_5% AZ_BITCLK N34 AM1 SATA_PRX_C_DTX_P0 D
<28> AZ_BITCLK_HD HDA_BCLK SATA0RXP SATA_PRX_C_DTX_P0 <24>
SATA 6G
SATA_PTX_DRX_N0 +3VS
Integrated SUS 1.05V VRM Enable AZ_SYNC L34
SATA0TXN AP7
AP5 SATA_PTX_DRX_P0
SATA_PTX_DRX_N0 <24> HDD
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 <24>
High - Enable Internal VRs <28> PCH_SPKR

PCH_SPKR T10 SPKR SATA1RXN AM10
PCH_INTVRMEN (must be always pulled high) AM8 SATA_LED# R336 2 1 10K_0402_5%
R142 1 SATA1RXP
<28> AZ_RST_HD# 2 33_0402_5% AZ_RST# K34 HDA_RST# SATA1TXN AP11
SATA1TXP AP10
CR_WAKE# R334 2 1 10K_0402_5%
+RTCVCC AZ_SDIN0_HD E34 AD7 SATA_PRX_C_DTX_N2
<28> AZ_SDIN0_HD HDA_SDIN0 SATA2RXN SATA_PRX_C_DTX_N2 <24>
AD5 SATA_PRX_C_DTX_P2
SATA2RXP SATA_PRX_C_DTX_P2 <24>
R117 1 SM_INTRUDER# SATA_PTX_DRX_N2 PCH_GPIO19 R335 1 2 10K_0402_5%
2
1M_0402_5%
G34 HDA_SDIN1 SATA2TXN AH5
AH4 SATA_PTX_DRX_P2
SATA_PTX_DRX_N2 <24> ODD
SATA2TXP SATA_PTX_DRX_P2 <24>
R118 1 2 PCH_INTVRMEN C34
IHDA
330K_0402_5% HDA_SDIN2
+3VS
PCH_SPK SATA3RXN
AB8
+3VALW 2 @ 1 A34 AB10
@ High = Enabled (No Reboot) R273 1K_0402_5% HDA_SDIN3 SATA3RXP
AF3
SATA3TXN
1 2 PCH_SPKR Low = Disabled (Default) SATA3TXP
AF1
R276 1K_0402_5% R289 1 2 33_0402_5% AZ_SDOUT A36
<28> AZ_SDOUT_HD
SATA
HDA_SDO
Y7
+3VALW SATA4RXN
Y5
R580 1 SATA4RXP
<30> PWRME_CTRL# 2 0_0402_5% C36 AD3
CR_CPPE# HDA_DOCK_EN# / GPIO33 SATA4TXN
1 2 AD1
R560 10K_0402_5% CR_CPPE# SATA4TXP
N32
HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
HDA_SDO SATA5RXP Y1
AB3
PCH_JTAG_TCK SATA5TXN
J3 AB1
JTAG_TCK SATA5TXP
ME debug mode,
T37 PAD PCH_JTAG_TMS H7 Y11
JTAG
this signal has a weak internal pull down JTAG_TMS SATAICOMPO
*Low = Disable (default)

High = Enable (flash descriptor security overide)
T38 PAD PCH_JTAG_TDI K5 JTAG_TDI SATAICOMPI Y10 SATAICOMP 1
R279
2
37.4_0402_1%
+1.05VS_VCC_SATA
T39 PAD PCH_JTAG_TDO H1 JTAG_TDO

AB12
C SATA3RCOMPO C
HDA_SYNC SATA3COMPI AB13 SATA3_COMP 1

R280
2
49.9_0402_1%
+1.05VS_SATA3
*This signal has a weak internal pull

H=>On Die PLL is supplied by 1.5V
down
PCH_SPICLK T3
SPI_CLK SATA3RBIAS
AH1 RBIAS_SATA3 1 2
R281 750_0402_1%
L=>On Die PLL is supplied by 1.8V PCH_SPICS# Y14
SPI_CS0#
Need to pull high for Huron River platform SA000041P00 T1
SPI
AZ_SYNC SPI_CS1# SATA_LED#
+3VALW 2 1 P3
R284 1K_0402_5% SATALED#
4M Byte PCH_SPIDI V4 V14 CR_WAKE#
+5VS +3VS SPI_MOSI SATA0GP / GPIO21
PCH_SPIDO U3 P1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19 PCH_GPIO19 <19>
2
G
Q21 BOOT BIOS Strap Bit 0

1 2 AZ_SYNC_R 3 1 U13 1
for EMI COUGARPOINT_FCBGA989~D Q65R3@
<28> AZ_SYNC_HD
R156 33_0402_5% PCH_SPICS# C494
S
1 8
PCH_SPIDO CS# VCC PCH_SPICLK
2 7
BSS138_NL_SOT23-3 DO HOLD# PCH_SPICLK 0.1U_0402_16V4Z
1 2 3 6
WP# CLK
1
R1444 1M_0402_5% @ PCH_SPIDI 2
1 2 4 5
R285 0_0402_5% GND DI R397
W25Q32BVSSIG_SO8 10_0402_5%
RTC schematic for non-chargeable
2
1
C86
10P_0402_50V8J +RTCVCC D13 +RTCBATT
remove socket for DVT phase, due to ME
3
height limitation 2
1
+3VL
Please close to U2 PCH 1 2 2 1

R277 1K_0402_5%
C486 BAV70W_SOT323-3
1
0.1U_0402_16V4Z
B 2 B
+
@ JRTC
LOTES_AAA-BAT-054-K01
-
2
0812 -> Add R277 for RTC reserve charge
+3VALW +3VALW +3VALW
2
R363 R330 R278
200_0402_5% 200_0402_5% 200_0402_5%
1
PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI
2
R306 R295 R301
100_0402_1% 100_0402_1% 100_0402_1%
A A
1
1 2 PCH_JTAG_TCK
R355 51_0402_1%

PCH_HDA/JTAG/SATA/SPI/LPC
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
U2B +3VALW 2 R232 1 2.2K_0402_5% +3VS

PCIE_PRX_C_LANTX_N1 BG34 2 R260 1 2.2K_0402_5% R400 4.7K_0402_5%
<26> PCIE_PRX_C_LANTX_N1 PERN1
5
PCIE_PRX_C_LANTX_P1 BJ34 E12 EC_LID_OUT# Q3B R386 4.7K_0402_5%
<26> PCIE_PRX_C_LANTX_P1 PERP1 SMBALERT# / GPIO11 EC_LID_OUT# <30>
LAN C498 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 AV32
<26> PCIE_PTX_C_LANRX_N1 PETN1
C497 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 AU32 H14 PCH_SMBCLK PCH_SMBDATA 3 4
<26> PCIE_PTX_C_LANRX_P1 PETP1 SMBCLK PM_SMBDATA <11,12,25>
2
PCIE_PRX_WLANTX_N2 BE34 C9 PCH_SMBDATA Q3A 2N7002DW-T/R7_SOT363-6
<25> PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
PCIE_PRX_WLANTX_P2 BF34
<25> PCIE_PRX_WLANTX_P2 PERP2
WLAN <25> PCIE_PTX_C_WLANRX_N2 C501 2 1 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BB32 PCH_SMBCLK 6 1
PCIE_PTX_WLANRX_P2 PETN2 PM_SMBCLK <11,12,25>
C502 2 1 0.1U_0402_16V7K AY32
SMBUS
<25> PCIE_PTX_C_WLANRX_P2 PETP2
A12 DRAMRST_CNTRL_PCH 2N7002DW-T/R7_SOT363-6
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36 PERN3
D BJ36 C8 PCH_SMLCLK0 D
PERP3 SML0CLK
AV34 PETN3
AU34 G12 PCH_SMLDATA0 +3VALW 2 R364 1 2.2K_0402_5% +3VS
PETP3 SML0DATA
BF36 PERN4 2 R385 1 2.2K_0402_5%
5
BE36 Q4B
PERP4 PCH_GPIO74
AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13
BB34 PCH_SMLDATA1 3 4
PETP4 EC_SMB_DA2 <30>
E14 PCH_SMLCLK1
PCI-E*
SML1CLK / GPIO58
2
BG37 Q4A 2N7002DW-T/R7_SOT363-6
PERN5 PCH_SMLDATA1
BH37 PERP5 SML1DATA / GPIO75 M16
AY36 PCH_SMLCLK1 6 1
PETN5 EC_SMB_CK2 <30>
BB36 PETP5 2N7002DW-T/R7_SOT363-6
BJ38 PERN6
BG38
Controller
PERP6
AU36 PETN6 CL_CLK1 M7
AV36 PETP6
Control Link only for support Intel IAMT.
Link
BG40 PERN7 CL_DATA1 T11
BJ40 PERP7
AY40 +3VALW
+3VS PETN7
BB40 PETP7 CL_RST1# P10
R287 1 2 10K_0402_5% CLKREQ_JET# BE38 PERN8

EC_LID_OUT# R123 1 2 10K_0402_5%
BC38 PERP8
R338 1 2 10K_0402_5% CLKREQ_WLAN# AW 38 PETN8
DRAMRST_CNTRL_PCH R228 1 2 1K_0402_5%
AY38 PETP8 PCH_GPIO74 R234 1 2 10K_0402_5%
M10 PCH_GPIO47
CLK_LAN# PEG_A_CLKRQ# / GPIO47 PCH_SMLCLK0 R238 1
<26> CLK_LAN# Y40 CLKOUT_PCIE0N 2 10K_0402_5%
C
LAN CLK_LAN Y39 C
<26> CLK_LAN CLKOUT_PCIE0P
AB37 PCH_SMLDATA0 R239 1 2 10K_0402_5%
CLOCKS
CLKREQ_LAN# CLKOUT_PEG_A_N
<26> CLKREQ_LAN# J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38
PCH_GPIO47 R251 1 2 10K_0402_5%
CLK_WLAN# AB49 AV22 CLK_CPU_DMI#
<25> CLK_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# <5>
WLAN CLK_WLAN AB47 AU22 CLK_CPU_DMI
<25> CLK_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <5>
CLKREQ_WLAN# M1
<25> CLKREQ_WLAN# PCIECLKRQ1# / GPIO18
AM12 CLK_DPLL#
CLKOUT_DP_N / CLKOUT_BCLK1_N T13 PAD
AM13 CLK_DPLL 120 MHz for eDP
CLKOUT_DP_P / CLKOUT_BCLK1_P T14 PAD
AA48 CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 PCH_CLK_DMI# PCH_CLK_DMI# R242 1 2 10K_0402_5%
CLKREQ_JET# CLKIN_DMI_N PCH_CLK_DMI PCH_CLK_DMI R243 1
V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 2 10K_0402_5%
CLKIN_GND1# R244 1 2 10K_0402_5%

Y37 CLKIN_GND1_N CLKIN_DMI2_N BJ30 CLKIN_GND1# CLKIN_GND1 R245 1 2 10K_0402_5%
CLKOUT_PCIE3N CLKIN_GND1
Y36 CLKOUT_PCIE3P CLKIN_GND1_P CLKIN_DMI2_P BG30
CLK_DOT# R246 1 2 10K_0402_5%
CLKREQ_CR# A8 CLK_DOT R247 1 2 10K_0402_5%
PCIECLKRQ3# / GPIO25 CLK_DOT#
G24
CLKIN_DOT_96N
E24 CLK_DOT From Clock Gen. CLK_SATA# R248 1 2 10K_0402_5%
CLKIN_DOT_96P CLK_SATA R249 1
Y43 CLKOUT_PCIE4N 2 10K_0402_5%
Y45 CLKOUT_PCIE4P
AK7 CLK_SATA# CLK_14M_PCH R250 1 2 10K_0402_5%
+3VALW PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_SATA
L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P / CKSSCD_P AK5
R343 1 210K_0402_5% CLKREQ_LAN# V45 K45 CLK_14M_PCH

CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
B R344 1 PCH_GPIO26 B
210K_0402_5% For EMI
CLKREQ_USB30# L14 H45 CLK_PCILOOP
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCILOOP <19>
R345 1 210K_0402_5% CLKREQ_CR#
@
R346 1 210K_0402_5% CLKREQ_USB30# AB42 CLKOUT_PEG_B_N XTAL25_IN V47 PCH_X1 CLK_PCILOOP 2 @ 1 2 1
Please place under DDR SODIMM. AB40 V49 PCH_X2 R417 10_0402_5% C474 22P_0402_50V8J
R348 1 PANEL_SEL CLKOUT_PEG_B_P XTAL25_OUT
210K_0402_5% 10/25
PASSWORD_CLEAR# E6 PEG_B_CLKRQ# / GPIO56
R351 1 210K_0402_5% PASSWORD_CLEAR#
1
JPW Y47 XCLK_RCOMP 1 2

XCLK_RCOMP +1.05VS_VCCDIFFCLKN
@ V40 R354 90.9_0402_1%
CLKOUT_PCIE6N
V42
2
CLKOUT_PCIE6P
delete test-point for EMI request
LVDS_SEL T13 PCIECLKRQ6# / GPIO45
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43
V37
FLEX CLOCKS
R233 @ CLKOUT_PCIE7P PCH_48MCLK 1

<10> CLK_RES_ITP# 2 1 0_0402_5% CLKOUTFLEX1 / GPIO65 F47 R576 2
48MCLK_CR <27>
R282 2 @ 1 0_0402_5% PANEL_SEL K12 22_0402_5% R365 2 1 1M_0402_5%
<10> CLK_RES_ITP PCIECLKRQ7# / GPIO46
H47 CLK_FLEX2
CLKOUTFLEX2 / GPIO66 T31 PAD
R352 2 1 0_0402_5% CLK_BCLK_ITP# AK14 Y2
<5> CLK_CPU_ITP# CLKOUT_BCLK0_N / CLKOUT_PCIE8N
R353 2 1 0_0402_5% CLK_BCLK_ITP AK13 K49 CLK_FLEX3 T33 PAD PCH_X1 1 2 PCH_X2
<5> CLK_CPU_ITP CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
1 25MHZ_20PF_7A25000012 1
COUGARPOINT_FCBGA989~D Q65R3@ C506 C507
27P_0402_50V8J 27P_0402_50V8J
2 2
+3VALW
A PANEL_SEL A
@
1 2 PANEL_SEL R347 1 2 10K_0402_5% LVDS_SEL
R584 10K_0402_5% PANEL_SEL H L
Channel LVDS EDP Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_PCI-E/SMBUS/CLK
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
U2C
<6> DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <6>
<6> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<6> DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<6> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3
+3VALW DMI3RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
BC12 FDI_CTX_PRX_N4
FDI_RXN4 FDI_CTX_PRX_N4 <6>
D <6> DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 D
DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <6>
PS3@ <6> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
2 1 DRAMPWROK <6> DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
R316 200_0402_5% <6> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20
PCH_SUSPWRDN_R DMI3RXP FDI_CTX_PRX_P0
2 1 BG14 FDI_CTX_PRX_P0 <6>
R218 10K_0402_5% DMI_PTX_CRX_N0 FDI_RXP0 FDI_CTX_PRX_P1
<6> DMI_PTX_CRX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <6>
2 1 RI# DMI_PTX_CRX_N1 AW20 BF14 FDI_CTX_PRX_P2
<6> DMI_PTX_CRX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <6>
R220 10K_0402_5% DMI_PTX_CRX_N2 BB18 BG13 FDI_CTX_PRX_P3
2 1 PCH_LOW_BAT# DMI_PTX_CRX_N3 AV18 BE12 FDI_CTX_PRX_P4
DMI
FDI
R221 10K_0402_5% BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <6>
DMI_PTX_CRX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<6> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <6>
DMI_PTX_CRX_P1 AY20 BH9 FDI_CTX_PRX_P7
<6> DMI_PTX_CRX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
DMI_PTX_CRX_P2 AY18
<6> DMI_PTX_CRX_P2 DMI2TXP
DMI_PTX_CRX_P3 AU18
<6> DMI_PTX_CRX_P3 DMI3TXP
2 1 PCH_RSMRST# AW16 FDI_INT
FDI_INT FDI_INT <6>
R127 10K_0402_5% PCH_DPWROK 1 2 PCH_RSMRST#
2 1 PM_PWROK +1.05VS_PCH 1 2 DMI_COMP BJ24 AV12 FDI_FSYNC0 R222 0_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <6>
R128 10K_0402_5% R130 49.9_0402_1%
2 1 SYS_PWROK BG25 BC10 FDI_FSYNC1 Stuff R222 if do not support DeepSX state
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <6>
R129 10K_0402_5%
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <6>
R160 750_0402_1%
BB10 FDI_LSYNC1
FDI_LSYNC1 FDI_LSYNC1 <6>
0_0402_5% DSWVREN +RTCVCC

8/30 Reserve R259 For cost down plan DSWVRMEN
A18
1 @ R259 2
System Power Management

C +3VS PAD T34 SUSACK# C12 E22 PCH_DPWROK DSWVREN R224 2 1 330K_0402_5% C
0.1U_0402_16V4Z SUSACK# DPWROK
1 2 R225 2 @ 1 330K_0402_5%
C250 <5> XDP_DBRESET# XDP_DBRESET# K3 B9 EC_SWI#
SYS_RESET# WAKE# EC_SWI# <26>
5
U12
1
P
<5,30,41> VGATE IN1

4 SYS_PWROK P12 N3 PM_GPIO32 DSWVREN must be always pulled high to +RTCVCC
PM_PWROK O SYS_PWROK CLKRUN# / GPIO32
2
：
<5,30> PM_PWROK IN2
G
DSWVREN - Internal Deep Sleep 1.05V regulator
：
SN74AHC1G08DCKR_SC70-5 PM_PWROK PM_PWROK_R SUS_STAT# T17 PAD
1 2 L22 G8
* H Enable
3
R216 0_0402_5% PWROK SUS_STAT# / GPIO61

32.768 KHz L Disable
L10 N14 CLK_EC <30>
APWROK SUSCLK / GPIO62
DRAMPWROK B13 D10 PM_SLP_S5#

<5> DRAMPWROK DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <30>
SUSACK# 2 @ 1 PCH_SUSPWRDN_R +3VS
R137 0_0402_5% PCH_RSMRST# C21 H4 PM_SLP_S4#
<30> PCH_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <30>
PM_GPIO32 R313 1 2 8.2K_0402_5%
Stuff R137 if EC does not want to <30> PCH_SUSPWRDN 1 2 PCH_SUSPWRDN_R K16 SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# F4 PM_SLP_S3#
PM_SLP_S3# <30>
R320 0_0402_5%
involve in the handshake mechanism 8/18 Change Net name from PM_CLKRUN# to
for the DeepSX state entry and exit <5,30> PBTN_OUT# PBTN_OUT# E20
PWRBTN# SLP_A#
G10 PM_SLP_A# T35 PAD
PCH_GPIO32 by HW Review demand
1 2 PCH_ACIN H20 G16 PM_SLP_SUS# T58 PAD +3VALW
+3VALW ACPRESENT / GPIO31 SLP_SUS#
R469 330K_0402_5%
B B
D12 PCH_LOW_BAT# E10 AP14 H_PM_SYNC EC_SWI# R319 1 2 10K_0402_5%
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>
1 2
<30,36> ACIN
RB751V40_SC76-2 RI# A10 K14 PCH_GPIO29 PCH_GPIO29 R563 1 @ 2 10K_0402_5%
RI# SLP_LAN# / GPIO29
COUGARPOINT_FCBGA989~D Q65R3@
H_PM_SYNC C898 1 2 220P_0402_50V7K

@
9/1 Reserve C894 for ESD requset

D16
PM_PWROK 2 1 PCH_RSMRST#
RB751V40_SC76-2
D14
<35,37> POK 1 2
RB751V40_SC76-2
A A

PCH_DMI/FDI/PM
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
U2D
UMA_ENBKL J47 AP43
<30> UMA_ENBKL L_BKLTEN SDVO_TVCLKINN
UMA_ENVDD M45 AP45
<13> UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
PCH_PW M P45 AM42
<13> PCH_PW M L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
<13> LCD_EDID_CLK LCD_EDID_CLK T40
LCD_EDID_DATA L_DDC_CLK
<13> LCD_EDID_DATA K47 L_DDC_DATA SDVO_INTN AP39
SDVO_INTP AP40
D LCTL_CLK T45 D
LCTL_DATA L_CTRL_CLK
P39 L_CTRL_DATA
1 2 LVDS_IBG AF37 P38
R219 2.37K_0402_1% LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39
1 2 UMA_ENBKL T40 PAD
R230 100K_0402_5% AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
AT40 HDMI_HPD
DDPB_HPD HDMI_HPD <20>
LCD_TXCLK- AK39
LVDS
<13> LCD_TXCLK- LVDSA_CLK#
1
LCD_TXCLK+ AK40 AV42
<13> LCD_TXCLK+ LVDSA_CLK DDPB_0N
AV40 R1433
+3VS LCD_TXOUT0- DDPB_0P
<13> LCD_TXOUT0- AN48 LVDSA_DATA#0 DDPB_1N AV45 100K_0402_5%
LCD_TXOUT1- AM47 AV46
Digital Display Interface

<13> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P
LCD_TXOUT2- AK47 AU48
<13> LCD_TXOUT2-
2
LCTL_CLK LVDSA_DATA#2 DDPB_2N
2 1 AJ48 LVDSA_DATA#3 DDPB_2P AU47
R471 2.2K_0402_5% AV47
LCD_TXOUT0+ DDPB_3N
<13> LCD_TXOUT0+ AN47 LVDSA_DATA0 DDPB_3P AV49
2 1 LCTL_DATA LCD_TXOUT1+ AM49
<13> LCD_TXOUT1+ LVDSA_DATA1
R472 2.2K_0402_5% LCD_TXOUT2+ AK49
<13> LCD_TXOUT2+ LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
2 1 LCD_EDID_CLK P42
R223 2.2K_0402_5% DDPC_CTRLDATA
AF40 LVDSB_CLK#
2 1 LCD_EDID_DATA AF39 AP47
R229 2.2K_0402_5% LVDSB_CLK DDPC_AUXN
DDPC_AUXP AP49
AH45 AT38 R473 2 1 100K_0402_5%
UMA_CRT_CLK LVDSB_DATA#0 DDPC_HPD
2 1 AH47 LVDSB_DATA#1
C R237 2.2K_0402_5% AF49 AY47 C
LVDSB_DATA#2 DDPC_0N
AF45 LVDSB_DATA#3 DDPC_0P AY49
2 1 UMA_CRT_DATA AY43
R231 2.2K_0402_5% DDPC_1N
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49
UMA_CRT_B N48 M43

<14> UMA_CRT_B CRT_BLUE DDPD_CTRLCLK
1 2 UMA_CRT_B UMA_CRT_G P49 M36
<14> UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
R240 150_0402_1% UMA_CRT_R T49
<14> UMA_CRT_R CRT_RED
1 2 UMA_CRT_G AT45
CRT
R241 150_0402_1% UMA_CRT_CLK DDPD_AUXN
<14> UMA_CRT_CLK T39 CRT_DDC_CLK DDPD_AUXP AT43
<14> UMA_CRT_DATA UMA_CRT_DATA M40 BH41 R524 2 1 100K_0402_5%
UMA_CRT_R CRT_DDC_DATA DDPD_HPD
1 2
R318 150_0402_1% BB43
UMA_CRT_HSYNC DDPD_0N
<14> UMA_CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
UMA_CRT_VSYNC M49 BF44
<14> UMA_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BE44
DDPD_2N BF42
2 1 CRT_IREF T43 BE42
R311 1K_0402_0.5% DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
B B
A A

PCH_CRT/LVDS
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
U2E
NV_CE#0 AY7
NV_CE#1 AV7
BG26 TP1 NV_CE#2 AU3
BJ26 TP2 NV_CE#3 BG4
BH25 TP3
BJ16 TP4 NV_DQS0 AT10
BG16 TP5 NV_DQS1 BC8
D AH38 TP6 D
AH37 TP7 NV_DQ0 / NV_IO0 AU2
AK43 TP8 NV_DQ1 / NV_IO1 AT4
AK45 TP9 NV_DQ2 / NV_IO2 AT3
C18 TP10 NV_DQ3 / NV_IO3 AT1
N30 TP11 NV_DQ4 / NV_IO4 AY3
H3 TP12 NV_DQ5 / NV_IO5 AT5
AH12 TP13 NV_DQ6 / NV_IO6 AV3
NVRAM
AM4 TP14 NV_DQ7 / NV_IO7 AV1
AM5 TP15 NV_DQ8 / NV_IO8 BB1
+3VS Y13 BA3
TP16 NV_DQ9 / NV_IO9
K24 TP17 NV_DQ10 / NV_IO10 BB5
RP1 L24 BB3
PCI_PIRQC# TP18 NV_DQ11 / NV_IO11
8 1 AB46 TP19 NV_DQ12 / NV_IO12 BB7
7 2 PCH_GPIO4 AB45 BE8
RSVD
PCH_GPIO2 TP20 NV_DQ13 / NV_IO13
6 3 NV_DQ14 / NV_IO14 BD4
5 4 PCI_PIRQA# BF6
NV_DQ15 / NV_IO15
8.2K_0804_8P4R_5% B21 AV5
TP21 NV_ALE NV_CLE
8/23 PIN swap for layout request M20 TP22 AY1
RP2 AY16 TP23
DF_TVS NV_CLE
8 1 PCH_GPIO52 BG46 AV10
PCH_GPIO53 TP24 NV_RCOMP
7 2
6 3 PCH_GPIO54 AT8
RF_OFF# NV_RB#
5 4
BE28 TP25 NV_RE#_WRB0 AY5
8.2K_0804_8P4R_5% BC30 BA2
TP26 NV_RE#_WRB1
BE32 TP27
RP3 BJ32 AT12
PCH_GPIO50 TP28 NV_WE#_CK0
8 1 BC28 TP29 NV_WE#_CK1 BF3
7 2 PCI_PIRQB# BE30
ODD_DA# TP30
6 3 BF32 TP31
C W L_OFF# USB20_N0 C
5 4 BG32 TP32 USBP0N C24 USB20_N0 <24>
AV26 A24 USB20_P0 USB-LEFT1
TP33 USBP0P USB20_P0 <24>
8.2K_0804_8P4R_5% BB26 C25 USB20_N1
TP34 USBP1N USB20_N1 <24>
AU28 B25 USB20_P1 USB-LEFT2
TP35 USBP1P USB20_P1 <24>
1 2 PCH_GPIO5 AY30 C26
R321 8.2K_0402_5% TP36 USBP2N
AU26 TP37 USBP2P A26
1 2 PCI_PIRQD# AY26 K28
R322 8.2K_0402_5% TP38 USBP3N
AV28 TP39 USBP3P H28
AW30 TP40 EHCI 1 USBP4N E28 DMI & FDI Termination Voltage
USBP4P D28
USBP5N C28
USBP5P A28 Set to VCC when HIGH
USBP6N C29 NV_CLE
USBP6P B29
USB port6 and port7 are disabled on HM65 Set to VSS when LOW
PCI_PIRQA# K40 N28
PCI_PIRQB# PIRQA# USBP7N
K38 M28
PCI
PCI_PIRQC# PIRQB# USBP7P
H38 PIRQC# USBP8N L30
PCI_PIRQD# G38 K30 +1.8VS
PIRQD# USBP8P USB20_N9
USBP9N G30 USB20_N9 <25>
PCH_GPIO50 C46 E30 USB20_P9 WiMax&BT combo card
USB
REQ1# / GPIO50 USBP9P USB20_P9 <25>
1
PCH_GPIO52 C44 C30 USB20_N10
REQ2# / GPIO52 USBP10N USB20_N10 <27>
PCH_GPIO54 E40 EHCI 2 A30 USB20_P10 Card Reader R324
REQ3# / GPIO54 USBP10P USB20_P10 <27>
L32 USB20_N11 2.2K_0402_5%
USBP11N USB20_N11 <13>
RF_OFF# D47 K32 USB20_P11 Int. Camera
GNT1# / GPIO51 USBP11P USB20_P11 <13>
PCH_GPIO53 E42 G32
2
W L_OFF# GNT2# / GPIO53 USBP12N NV_CLE
<25> W L_OFF# F46 GNT3# / GPIO55 USBP12P E32 2 1 H_SNB_IVB# <5>
C32 R323 1K_0402_5%
USBP13N
USBP13P A32
PCH_GPIO2 G42
ODD_DA# PIRQE# / GPIO2
<24> ODD_DA# G40 PIRQF# / GPIO3 8/18 Change R324 From 1K to 2.2K by
PCH_GPIO4 C42 C33 USBBIAS 1 2
B PCH_GPIO5 D44
PIRQG# / GPIO4 USBRBIAS# R535 22.6_0402_1% Intel check list demand B
PIRQH# / GPIO5
Within 500 mils
USBRBIAS B33
T32 PAD PCI_PME# K10 PME# H_SNB_IVB# C895 1 2 220P_0402_50V7K
PLT_RST# PLT_RST# C6 A14 USB_OC#0 USB-Left @
<5,25,26,30,31> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC#0 <24,30>
K20 USB_OC#1
OC1# / GPIO40 USB_OC#2
OC2# / GPIO41 B17
2
22_0402_5% 1 2 R525 CLK_EC_R H49 C16 SLP_CHG_M3

<30> CLK_PCI_EC CLKOUT_PCI0 OC3# / GPIO42
R534 22_0402_5% 1 2 R526 CLK_PCH H43 L16 SLP_CHG_M4 9/1 Reserve C895 for ESD requset
<16> CLK_PCILOOP CLKOUT_PCI1 OC4# / GPIO43
100K_0402_5% 22_0402_5% 1 2 R527 CLK_SIO J48 A16 USB_OC#5
<31> CLK_PCI_DDR CLKOUT_PCI2 OC5# / GPIO9
K42 D14 USB_OC#6
CLKOUT_PCI3 OC6# / GPIO10 USB_OC#7
H40 C14
1
CLKOUT_PCI4 OC7# / GPIO14
COUGARPOINT_FCBGA989~D Q65R3@ +3VALW
RP4
USB_OC#6 4 5
USB_OC#0 3 6
Boot BIOS Strap USB_OC#5 2 7
SLP_CHG_M4 1 8
RF_OFF# PCH_GPIO19 Boot BIOS Loaction
10K_0804_8P4R_5%
1K_0402_5% @ 1 R537 RF_OFF# 8/23 PIN swap for layout request
2 0 0 LPC RP5
1K_0402_5% @ 1 R538 PCH_GPIO19 USB_OC#1
2 PCH_GPIO19 <15> 0 1 Reserved USB_OC#2
4
3
5
6
SLP_CHG_M3
1 0 PCI USB_OC#7
2
1
7
8
A
1 1 SPI * 10K_0804_8P4R_5%
A
1K_0402_5% 2 @ W L_OFF#
A16 Swap Override Strap
1 R536
Low= A16 swap override Enable
WL_OFF# 2010/09/03 2012/12/31
* High= A16 swap override Disable Issued Date Deciphered Date Title
PCH_PCI/USB/NAND
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+3VS
+3VALW U2F
ODD_EN# 1 2
HDMI_HPD T7 C40 ODD_EN# R106 10K_0402_5%
<18> HDMI_HPD BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# <33>
2 1 USB30_SMI# GATEA20 1 2
R390 1K_0402_5% PCH_GPIO1 A42 B41 PCH_W L_BT_LED R548 10K_0402_5%
EC_SMI# TACH1 / GPIO1 TACH5 / GPIO69 KB_RST#
1 2 1 2
R558 10K_0402_5% PCH_GPIO6 H36 C41 LOGO_LED R559 10K_0402_5%
PCH_GPIO12 TACH2 / GPIO6 TACH6 / GPIO70 LOGO_LED
1 2 1 2
R556 10K_0402_5% <30> EC_SCI# EC_SCI# E38 A40 MAXIC_SELECT T75 PAD R436 10K_0402_5%
PCH_GPIO28 TACH3 / GPIO7 TACH7 / GPIO71 PCH_W L_BT_LED
D 1 2 1 2 D
R557 10K_0402_5% <30> EC_SMI# EC_SMI# C10 R110 10K_0402_5%
3D_DET# GPIO8
1 2
R549 10K_0402_5% PCH_GPIO12 C4 LAN_PHY_PWR_CTRL / GPIO12
+3VS USB30_SMI# G2 P4 GATEA20
GPIO15 A20GATE GATEA20 <30>
AU16
CPU/MISC
BT_ON# PCH_GPIO16 PECI
1 2 U2 SATA4GP / GPIO16
R567 10K_0402_5% P5 KB_RST#
RCIN# KB_RST# <30>
1 @ 2 HDMI_HPD
GPIO
R539 10K_0402_5% PCH_GPIO17 D40 AY11 H_PW RGOOD
TACH0 / GPIO17 PROCPWRGD H_PW RGOOD <5>
1 2 PCH_GPIO1
R540 10K_0402_5% BT_DET# T5 AY10 PCH_THRMTRIP# 1 2
SCLOCK / GPIO22 THRMTRIP# H_THERMTRIP# <5>
1 2 BT_DET# R416 390_0402_5%
R542 10K_0402_5% E8 T14
OPTIMUS_EN# GPIO24 / MEM_LED INIT3_3V#
1 2
R554 10K_0402_5% PCH_GPIO27 E16 GPIO27
1 2 ODD_DETECT# This signal has weak internal
R545 200K_0402_5% PCH_GPIO28 P8
1 2 PCH_GPIO6 GPIO28
AH8
pull-up, can't be pulled low
R546 10K_0402_5% BT_ON# NC_1
<25> BT_ON# K1 STP_PCI# / GPIO34
1 2 PCH_GPIO16
NC_2 AK11 8/18 Remove PCH PECI by HW Review demand
R577 10K_0402_5% T74 PAD PCH_GPIO35 K4
EC_SCI# GPIO35
1 2 NC_3 AH10
R550 10K_0402_5% ODD_DETECT# V8
<24> ODD_DETECT# SATA2GP / GPIO36
1 2 CIR_EN# AK10
R551 100K_0402_5% PCH_GPIO37 NC_4
M5 SATA3GP / GPIO37
1 @ 2 ISDBT_DET P37
C R552 10K_0402_5% OPTIMUS_EN# NC_5 C
N2 SLOAD / GPIO38
1 2 PCH_GPIO49
R553 10K_0402_5% CIR_EN# M3
PCH_GPIO17 SDATAOUT0 / GPIO39
1 2
R555 10K_0402_5% ISDBT_DET V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO49 V3 BG48
SATA5GP / GPIO49 VSS_NCTF_16
3D_DET# D6 BH3
@ USB30_SMI# GPIO57 VSS_NCTF_17
2 1
R437 10K_0402_5% BH47
PCH_GPIO37 VSS_NCTF_18
1 2
R547 100K_0402_5% A4 BJ4
PCH_GPIO27 VSS_NCTF_1 VSS_NCTF_19
2 1
R402 10K_0402_5% A44 BJ44
VSS_NCTF_2 VSS_NCTF_20
A45 VSS_NCTF_3 VSS_NCTF_21 BJ45
1 2 ISDBT_DET
NCTF
R328 47K_0402_5% A46 BJ46
VSS_NCTF_4 VSS_NCTF_22
B3 VSS_NCTF_7 VSS_NCTF_25 C2
B47 VSS_NCTF_8 VSS_NCTF_26 C48
BD1 VSS_NCTF_9 VSS_NCTF_27 D1

B B
GPIO28
BD49 VSS_NCTF_10 VSS_NCTF_28 D49
On-Die PLL Voltage Regulator
H_THERMTRIP# C896 2 220P_0402_50V7K
* H: Enable BE1 VSS_NCTF_11 VSS_NCTF_29 E1 1
@
L: Disable BE49 VSS_NCTF_12 VSS_NCTF_30 E49
H_PW RGOOD C897 1 2 220P_0402_50V7K
BF1 F1 @
R325 @ VSS_NCTF_13 VSS_NCTF_31
1 2 1K_0402_5% PCH_GPIO28
BF49 VSS_NCTF_14 VSS_NCTF_32 F49
9/1 Reserve C896, C897 for ESD requset

GPIO8
Integrated Clock Chip Enable (Removed)
H: Disable
L: Enable
*
R326 1 @ 2 1K_0402_5% EC_SMI#
A A
Integrated clock enable functionality
is achieved by soft-strap
The current default is clock enable
PCH_CPU/GPIO
B 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+1.05VS_VCCP U2G POWER To solve CRT issue

+3VS
PCH Power Rail Table
PJ31 @ 1300mA L12
2 1 1U_0402_6.3V6K +1.05VS_PCH AA23 U48 +VCCA_DAC 0.1U_0402_10V7K 1 R104 2 +VCCA_DAC_R 2 1 S0 Iccmax
2 1
AC23
VCCCORE[1] 1mA VCCADAC 2.2_0603_1% BLM18PG181SN1D_0603 Voltage Rail Voltage
VCCCORE[2] 1 1 Current (A)
CRT
JUMP_43X118 1 1 1 1 AD21 C512 C288 C286
C274 C269 C275 C289 VCCCORE[3] 0.01U_0402_25V7K
AD23 VCCCORE[4] VSSADAC U47
D D
VCC CORE
AF21 VCCCORE[5]
V_PROC_IO 1.05 0.001
10U_0603_6.3V6M AF23 2 2
2 2 2 2 VCCCORE[6] 10U_0603_6.3V6M +3VS
AG21 VCCCORE[7]
AG23
VCCCORE[8]
V5REF 5 0.001
1U_0402_6.3V6K 1U_0402_6.3V6K AG24 1mA AK36 +VCCA_LVDS 1 2
VCCCORE[9] VCCALVDS R541 0_0603_5%
AG26 VCCCORE[10]
AG27
VCCCORE[11] VSSALVDS
AK37 V5REF_SUS 5 0.001
AG29 VCCCORE[12]
AJ23
LVDS
VCCCORE[13] +1.8VS
AJ26
VCCCORE[14] VCCTX_LVDS[1]
AM37 VCC3_3 3.3 0.266
AJ27 L1
VCCCORE[15] +VCCTX_LVDS 0.01U_0402_25V7K
AJ29 AM38 2 1
VCCCORE[16] VCCTX_LVDS[2]
AJ31 VCCCORE[17] 1 BLM18PG181SN1D_0603 VCCADAC 3.3 0.001
+1.05VS_PCH 60mA VCCTX_LVDS[3]
AP36 C256
C514 C513 22U_0805_6.3V6M
VCCTX_LVDS[4]
AP37 0.01U_0402_25V7K VCCADPLLA 1.05 0.08
AN19 2
VCCIO[28]
VCCADPLLB 1.05 0.08
BJ22 +3VS
T30 PAD VCCAPLLEXP
V33 VCCCORE 1.05 1.3
HVCMOS
VCC3_3[6]
AN16 VCCIO[15]
1
AN17
VCCIO[16]
C272 VCCDMI 1.05 0.042
V34 0.1U_0402_10V7K
VCC3_3[7]
AN21 2 VCCIO 1.05 2.925
VCCIO[17] +VCCAFDI_VRM +1.5VS
AN26 R474
VCCIO[18] 0_0603_5% VCCASW 1.05 1.01
+VCCAFDI_VRM
VCCIO[19] 2925mA
AN27 AT16 1 2
C VCCVRM[3] C
+1.05VS_PCH AP21 +VCCP_VCCDMI R480 +1.05VS_VCCP VCCSPI 3.3 0.02
VCCIO[20] 0_0805_5%
1U_0402_6.3V6K AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO[21] VCCDMI[1]
1 VCCDSW 3.3 0.002
DMI
AP24 R477 +1.05VS_PCH
1 1 1 1 1
VCCIO
C277 C273 C279 C510 C511 VCCIO[22] 0_0805_5% C276
AP26 AB36 +1.05VS_VCC_DMI 1 2 1U_0402_6.3V6K VCCDFTERM 1.8 0.19
10U_0603_6.3V6M 1U_0402_6.3V6K VCCIO[23] 20mA VCCIO[1] 2
2 2 2 2 2 1
AT24
VCCIO[24] C270 VCCRTC 3.3 6 uA
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2
AN33 VCCIO[25]
VCCDFTERM VCCSUS3_3 3.3 0.97
AN34 AG16 +1.8VS
+3VS VCCIO[26] VCCPNAND[1]
VCCSusHDA 3.3 / 1.5 0.01
NAND / SPI
BH29 AG17
VCC3_3[3] VCCPNAND[2]
1 1
C290 190mA VCCVRM 1.5 0.16
0.1U_0402_10V7K AJ16 C278
VCCPNAND[3] 0.1U_0402_10V7K
2 +VCCAFDI_VRM 2 VCCCLKDMI 1.05 0.02
AP16
VCCVRM[2]
AJ17
VCCPNAND[4]
T36 PAD BG6

VCCFDIPLL
VCCSSC 1.05 0.095
+3VS
+1.05VS_PCH AP17
VCCIO[27]
VCCDIFFCLKN 1.05 0.055
FDI
V1
20mA VCCSPI
+VCCP_VCCDMI AU20
VCCDMI[2] 1 VCCALVDS 3.3 0.001
B B
C281
COUGARPOINT_FCBGA989~D Q65R3@ 1U_0402_6.3V6K VCCTX_LVDS 1.8 0.06
2
A A

PCH_POWER-1
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
+3VS
L18
1 2 +3VS_VCC_CLKF33
10UH_LB2012T100MR_20% 1 1
C301 C310
10U_0603_6.3V6M 1U_0402_6.3V6K +3VALW
2 2 T42 PAD
U2J POWER +1.05VS_PCH
1 AD49 N26
C324 VCCACLK VCCIO[29]
1
D 0.1U_0402_10V7K P26 D
VCCIO[30] C328
T16
@ 2 VCCDSW3_3 3mA 1U_0402_6.3V6K
"@" Avoid leakage C305 VCCIO[31]
P28
2
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
0.1U_0402_10V7K T29
+3VS_VCC_CLKF33 VCCIO[33] +3VALW
T38
VCC3_3[5]
T23
VCCSUS3_3[7]
T41 PAD BH23 1
VCCAPLLDMI2 C321 +3VALW
119mA VCCSUS3_3[8]
T24
+5VALW +3VALW
+1.05VS_PCH AL29 0.1U_0402_10V7K
VCCIO[14]
V23
USB
VCCSUS3_3[9] 2
1
2
+VCCSUS AL24 V24
DCPSUS[3] VCCSUS3_3[10] C332 R512 D8
1
C300 P24 0.1U_0402_10V7K 100_0402_5% RB751V40_SC76-2
1U_0402_6.3V6K VCCSUS3_3[6] 2
@ AA19
1
+1.05VS_PCH 2 VCCASW[1] +PCH_V5REF_SUS
T26 +1.05VS_PCH
VCCIO[34]
AA21
VCCASW[2] 1010mA 1
AA24 1mA M26 +PCH_V5REF_SUS C326

VCCASW[3] V5REF_SUS 0.1U_0603_25V7K
AA26 @ 2
Clock and Miscellaneous

1 1 VCCASW[4]
C311 C312 AN23 +VCCA_USBSUS C335 1 2 1U_0402_6.3V6K
DCPSUS[4]
AA27
22U_0805_6.3V6M VCCASW[5]
AN24 +3VALW
2 2 VCCSUS3_3[1]
AA29
22U_0805_6.3V6M VCCASW[6]
+5VS +3VS
AA31
VCCASW[7]
C C
1U_0402_6.3V6K AC26 P34 +PCH_V5REF_RUN
VCCASW[8] 1mA V5REF
2
+3VALW
1 1 1
C323 C294 C308 AC27 R490 D7
VCCASW[9] 100_0402_5%
N20 RB751V40_SC76-2
PCI/GPIO/LPC
1U_0402_6.3V6K 1U_0402_6.3V6K VCCSUS3_3[2]
AC29 1
2 2 2 VCCASW[10]
N22
1
+1.05VS_PCH VCCSUS3_3[3] C293 +PCH_V5REF_RUN
AC31
VCCASW[11]
P20 1U_0402_6.3V6K 1
L13 VCCSUS3_3[4] 2
AD29
+1.05VS_VCCADPLLA VCCASW[12] C304
1 2 P22
BLM18PG181SN1D_0603 VCCSUS3_3[5] +3VS 1U_0603_10V6K
AD31
L14 VCCASW[13] 2
1 2 +1.05VS_VCCADPLLB W21 AA16
BLM18PG181SN1D_0603 VCCASW[14] VCC3_3[1]
+3VS 1
W23 W16 C313
VCCASW[15] VCC3_3[8] 0.1U_0402_10V7K
1 1 1 1
C287 C295 C291 C298 W24 T34
1U_0402_6.3V6K VCCASW[16] VCC3_3[4] 2
1U_0402_6.3V6K W26 1 2
2 2 2 2 VCCASW[17] C306
10U_0603_6.3V6M 10U_0603_6.3V6M W29 0.1U_0402_10V7K +3VS
VCCASW[18]
W31 AJ2
+1.05VS_PCH VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS_PCH
1
R522 W33 R516
+VCCDIFFCLK VCCASW[20] C297
2 1 AF13 2 1
VCCIO[5] 0.1U_0402_10V7K
0_0603_5% +VCCRTCEXT N16 2 0_0805_5%
1 DCPRTC 1
C337 1 AH13 C329
1U_0402_6.3V6K C334 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3
2 VCCVRM[4] VCCIO[13] 2
B 2 B
AF14
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLA VCCIO[6]
BD47
SATA
R485 VCCADPLLA 80mA T43 PAD
AK1
+1.05VS_VCCDIFFCLKN +1.05VS_VCCADPLLB VCCAPLLSATA +VCCAFDI_VRM
2 1 BF47
1
VCCADPLLB 80mA
0_0603_5% C320 AF11 +VCCAFDI_VRM
1U_0402_6.3V6K +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
AF17
VCCIO[7] R491
AF33
2 VCCIO[8] +1.05VS_VCC_SATA
VCCIO[9] 55mA
AF34 AC16 2 1
+1.05VS_VCCDIFFCLKN VCCIO[2] 0_0805_5%
AG34
+1.05VS_PCH VCCIO[11]
AC17 1
VCCIO[3] C331
AG33 AD17 1U_0402_6.3V6K
VCCIO[10] 95mA VCCIO[4]
1 2
C318
1U_0402_6.3V6K +VCCSST V16 +1.05VS_PCH
DCPSST
2 1
0.1U_0402_10V7K
+1.05VM_VCCSUS T17 T21 +VCCME_22 1 2
C299 DCPSUS[1] VCCASW[22] R509 0_0402_5%
V19
MISC
2 DCPSUS[2]
+1.05VS_VCCP V21 +VCCME_23 1 2
R511 VCCASW[23] R517 0_0402_5%
1mA
CPU
+1.05VS_PCH 1 2 0.1U_0402_10V7K +V_CPU_IO BJ8

R521 @ V_PROC_IO +VCCME_21
T19 1 2
+1.05VM_VCCSUS 0_0603_5% VCCASW[21] R520 0_0402_5%
2 1 1 1 1
C322 C303 +RTCVCC
0_0603_5% C325 +3VALW
1
RTC
C316 4.7U_0603_6.3V6K 0.1U_0402_10V7K 0.1U_0402_10V7K A22 10mA P32

HDA
2 2 2 VCCRTC VCCSUSHDA
1U_0402_6.3V6K
2 1 1 1 1
C327 C330 C336 COUGARPOINT_FCBGA989~D Q65R3@ C307
A A
0.1U_0402_16V4Z
1U_0402_6.3V6K 0.1U_0402_10V7K
2 2 2 2

PCH_POWER-2
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
U2I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
U2H B15 K7
VSS[164] VSS[264]
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
D AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36 D
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
C C
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
B AH36 AW2 D22 G14 B
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
COUGARPOINT_FCBGA989~D Q65R3@ G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

PCH_GND
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
SATA ODD Conn

+5VS
Place closely JHDD SATA CONN.
1.2A SW2 @
1 1 1 1 JODD @
Close to JODD 1 3
C356 C357 C358 C359 ODD_DA#_R 2 4

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
10U_0603_6.3V6M GND SATA_PTX_C_DRX_P2 C378 1
2 2 0.01U_0402_25V7K SATA_PTX_DRX_P2 <15>
SMT1-05-A_4P
6
5
2 2 2 2 A+ SATA_PTX_C_DRX_N2 C377 1
A- 3 2 0.01U_0402_25V7K SATA_PTX_DRX_N2 <15>
GND 4
5 SATA_PRX_DTX_N2 C376 1 2 0.01U_0402_25V7K
B- SATA_PRX_DTX_P2 SATA_PRX_C_DTX_N2 <15>
6 C375 1 2 0.01U_0402_25V7K
D B+ SATA_PRX_C_DTX_P2 <15> D
GND 7
SATA HDD DP 8 ODD_DETECT#_R 1 @ 2 ODD_DETECT# <20>

+5V 9 +5VS_ODD R561 0_0402_5%
Conn. +5V
MD
10
11 ODD_DA#_R 1 @ 2 ODD_DA# <19>
15 12 R562 0_0402_5% 1
GND GND @
14 GND GND 13
C450
0.1U_0402_16V4Z
SANTA_206401-1_RV 2
+5VS_ODD Place components closely ODD CONN.
Close to JHDD ESD request 1.1A
JHDD
1 1 1 1 1
1 C352 C353 @ C354 C355 C360
GND SATA_PTX_C_DRX_P0 C369 1
A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P0 <15>
3 SATA_PTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A- SATA_PTX_DRX_N0 <15> 2 2 2 2 2
GND 4
5 SATA_PRX_DTX_N0 C368 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N0 <15>
6 SATA_PRX_DTX_P0 C370 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P0 <15>
GND 7
V33
V33
8
9
10
+3VS USB Conn. Left Side
V33
GND 11
GND 12 W=60mils
C GND
V5
13
14 +5VS
+5VALW 2.5A +USB_VCCA For EMI C
15 U14
V5
V5 16 1 GND VOUT 8 2 1
17 2 7 C361 1000P_0402_50V7K
GND VIN VOUT
Reserved 18 3 VIN VOUT 6
GND 19 <30> USB_EN# 4 EN FLG 5 USB_OC#0 <19,30>
V12 20 1
24 21 RT9715BGS_SO8
GND V12 C362
23 GND V12 22
4.7U_0805_10V4Z
2 @
SANTA_191201-1 +5VALW
@
2
R568
100K_0402_5%
1
USB_EN#
B B
+USB_VCCA +USB_VCCA
W=60mils C85 1 2 220U_6.3V_M_R15 W=60mils
+
C63 1 2 1000P_0402_50V7K C61 1 2 1000P_0402_50V7K
2 @ 1 C64 1 2 0.1U_0402_16V4Z 2 @ 1 C60 1 2 0.1U_0402_16V4Z

R843 0_0402_5% R842 0_0402_5%
L87 JUSB1 @ L86 JUSB2 @

<19> USB20_N0 3 3 4 4 1 VCC GND 5 <19> USB20_N1 3 3 4 4 1 VCC GND 5
USB20_N0_R 2 6 USB20_N1_R 2 6
USB20_P0_R D- GND USB20_P1_R D- GND
3 D+ GND 7 3 D+ GND 7
<19> USB20_P0 2 2 1 1 4 GND GND 8 <19> USB20_P1 2 2 1 1 4 GND GND 8
WCM-2012-900T_0805 ALLTOP C107L8-10405-L WCM-2012-900T_0805 ALLTOP C107L8-10405-L
2 @ 1 2 @ 1
R839 0_0402_5% R838 0_0402_5%
D65 @ D62 @
USB20_N0_R 2 USB20_N1_R 2
1 1
USB20_P0_R 3 USB20_P1_R 3
A PJDLC05C_SOT23-3 PJDLC05C_SOT23-3 A

SATA-HDD/ODD/USB
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
WLAN&BT Combo module circuits
Slot 1 Half PCIe Mini Card-WLAN/ WiMax
BT BT
on module on module
Enable Disable
+3VALW 2 1 +3V_WLAN
2 1
PJ27@ JUMP_43X79 BT_CRTL H L
+3VS 2 1
2 1
PJ26@ JUMP_43X79 BT_ON# L H
Short PJ27 for Wimax **If +3V_WLAN is +3VS, please
Short PJ26 for WLAN remove D24
BT_CTRL
3
2N7002DW-T/R7_SOT363-6
6
40 mils Q50B
+3V_WLAN +1.5VS
For SED <20> BT_ON# 5
Q50A
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2N7002DW-T/R7_SOT363-6
4
1 1 1 1 1 1 <5,9,33,40> SUSP
1
1
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254
47P_0402_50V8J 47P_0402_50V8J
2
2
2 2 2 @ 2 2 2 @
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
+3VS
For SED
2
G
+1.5VS +3V_WLAN
JWLAN @ WLAN_OFF# 1 3 WL_OFF# <19>
R1443 1 2
S
0_0402_5% 1 2
3
3 4
4 Add level shift circuit for WL_OFF# to
BT_CTRL 1 @ 2BT_CTRL_R 5 6 2N7002_SOT23-3 Q36 avoide leakage from WLAN to PCH
5 6
<16> CLKREQ_WLAN# 7 8
7 8
9 10
9 10 WLAN_OFF# 1 @
<16> CLK_WLAN# 11 12 2 +3V_WLAN
11 12 R565 10K_0402_5%
<16> CLK_WLAN 13 14
13 14
15 16
15 16
17 18
17 18 WLAN_OFF#
19 20
19 20 PLT_RST#
21 22 PLT_RST# <5,19,26,30,31>
21 22
<16> PCIE_PRX_WLANTX_N2 23 24
23 24
<16> PCIE_PRX_WLANTX_P2 25 26
25 26
27 28
27 28
29 30 PM_SMBCLK <11,12,16>
29 30
<16> PCIE_PTX_C_WLANRX_N2 31 32 PM_SMBDATA <11,12,16>
31 32
<16> PCIE_PTX_C_WLANRX_P2 33 34
33 34
35 36 USB20_N9 <19>
35 36
WLAN/ WiFi 37
37 38
38 USB20_P9 <19> WiMax&BT combo card
+3V_WLAN 39 40
39 40
41 42
41 42
43 44
43 44
45 46 BT_CTRL 1 R327 2 E51_RXD_R
R16 45 46 1K_0402_5%
47 48
47 48
<30> E51_TXD 10_0402_5%2 49 50
49 50
<30> E51_RXD 1 2 E51_RXD_R 51
51 52
52 For isolate Intel Rainbow Peak and
0_0402_5% Compal Debug Card.
R17 53 54
GND1 GND2
Debug card using
FOX_AS0B226-S40N-7F
8/30 Reserve R1443 for WLAN Mini PCIE Card Pin5

PCIe-WLAN
1.0
PWWHA LA-7202P M/B
A B C D E
UL1
+3V_LAN CL3 to CL6 close to Pin 27,39,47,48
CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 31 +LAN_VDD10 CL7 to CL8 close to Pin 12,42
<16> PCIE_PRX_C_LANTX_P1 HSOP LED3/EEDO
37
LED1/EESK
<16> PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 LL1
8111E@ 1 2
+LAN_REGOUT 1 2 CL3 0.1U_0402_16V4Z
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N 1 2
<16> PCIE_PTX_C_LANRX_P1 PCIE_PTX_C_LANRX_N1 18 HSIP EECS/SCL
32 RL1 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_16V4Z
<16> PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA Layout Note: LL1 must be 1 2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_16V4Z
CLKREQ_LAN# 2 1 16 1 LAN_MDI0+ CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
<16> CLKREQ_LAN# CLKREQB MDIP0
RL19 0_0402_5% 2 LAN_MDI0- 200mil to LL1 8111E@ 2 2 8111E@ CL6 0.1U_0402_16V4Z
PLT_RST# MDIN0 LAN_MDI1+
<5,19,25,30,31> PLT_RST# 25 4 1 2
PERSTB MDIP1 LAN_MDI1- 8111E@ CL7 0.1U_0402_16V4Z
MDIN1 5
1 +3V_LAN CLK_LAN 19 7 LAN_MDI2+ 1 2 1
<16> CLK_LAN CLK_LAN# REFCLK_P NC/MDIP2 LAN_MDI2-
20 8 8111E@ CL8 0.1U_0402_16V4Z
<16> CLK_LAN# REFCLK_N NC/MDIN2 LAN_MDI3+
NC/MDIP3 10
RL24 2 @ 1 10K_0402_5% CLKREQ_LAN# 11 LAN_MDI3-
LAN_X1 NC/MDIN3
43
RL25 2 @ EC_SWI# CKXTAL1
1 10K_0402_5%
LAN_X2 44 13 +LAN_VDD10 +LAN_EVDD10
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_VDD10
29 CL19, CL20,CL21 close to pin 13,29,45, respectively
DVDD10
RTL8105E RTL8111E DVDD10 41 1 2 CL22 close to pin 3, respectively
EC_SWI# 28 LL2 0_0603_5% CL23,CL24,CL25 close to pin 6,9,41, respectively
<17> EC_SWI# LANWAKEB
Pin14 NC NC 1 1
+3VS ISOLATE# 26 27 1 2
ISOLATEB DVDD33 +3V_LAN CL17
Pin15 NC 10K ohm PD DVDD33 39 CL18 CL19 0.1U_0402_16V4Z
1U_0402_6.3V6K 0.1U_0402_16V4Z 1 2
Pin38 1K ohm Pull-high 2 2 CL20 0.1U_0402_16V4Z
14 12 +3V_LAN
NC/SMBCLK AVDD33
1
RL21 2 8111E@ 1 10K_0402_5% 15 42 1 2

RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 CL21 0.1U_0402_16V4Z
1K_0402_5% 8111E@
AVDD33
48 Close to Pin 21 1 2
RL6 8111E@ CL22 0.1U_0402_16V4Z
@ ENSWREG 33 1 2
2
ENSWREG 8111E@ CL23 0.1U_0402_16V4Z

21 +LAN_EVDD10
ISOLATE# WOL_EN EVDD10 +3V_LAN +LAN_VDDREG
1 2 +LAN_VDDREG 34 1 2
RL433 0_0402_5% VDDREG 8111E@ 8111E@ CL24 0.1U_0402_16V4Z
35 VDDREG AVDD10 3 +LAN_VDD10
AVDD10 6 1 2 1 2
9 LL3 0_0603_5% 1 1 8111E@ CL25 0.1U_0402_16V4Z
AVDD10
1 2 46 RSET AVDD10 45
RL7 Sx Enable Sx Disable S0 RL5 2.49K_0402_1% CL28 CL29
15K_0402_5% Wake up Wake up 24 36 +LAN_REGOUT 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
GND REGOUT 8111E@ 2 2 8111E@
49 PGND 60 mils
WOL_EN LOW HIGH HIGH RTL8111E-VB RTL8105E-VL
RTL8111E-GR_QFN48_6X6 +3V_LAN
2 8111E@ 2
PWM Mode LDO Mode
1
RL4 0 ohm NC
RL4 (Pull High)
0_0402_5%
8111E@ NC 0 ohm
+3VALW TO +3V_LAN +3V_LAN RL23 (Pull Down)
2
YL1 ENSWREG
LAN_X1 1 2 LAN_X2
1
+3VALW
1 25MHZ_20PF_7A25000012 RL23
+3VALW 0_0402_5%
1 1 1
CL683 + CL684 CL26 CL27 8105E@
220U_6.3V_M_R16 10U_0805_10V6K 27P_0402_50V8J 27P_0402_50V8J
2
1
2 @
RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm 2 2 2 2
100K_0402_5% @
@ 0.1U_0402_16V7K
2
1
2
S
@ RL432 @ QL51 PJ29
2
G
<30> WOL_EN 1 2 2 JUMP_43X79 FOR EMI ISN TEST DEMAND.
@
+3V_LAN
1
47K_0402_5% 2 AO3413_SOT23 D
1
@
1
CL482 8/30 Add UL3 at DVT

0.01U_0402_25V7K
1
2
CL681
1
CL682 UL3 LAN Conn.
1U_0402_6.3V6K
4.7U_0805_10V4Z 1 LAN_MDI0+ 1 16 RJ45_MIDI0+
@ 2 LAN_MDI0- TD+ TX+ RJ45_MIDI0- JLAN
2 15
3 TD- TX- 3
3 CT CT 14
4 13 RJ45_MIDI3- 8
NC NC PR4-
5 12
NC NC RJ45_MIDI3+
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. LAN_MDI1+
6
7
CT CT 11
10 RJ45_MIDI1+
7 PR4+
LAN_MDI1- RD+ RX+ RJ45_MIDI1- RJ45_MIDI1-
8 9 6
RD- RX- PR2-
RJ45_MIDI2- 5
X'FORM_ LFE8456E PR3-
8105E@ RJ45_MIDI2+ 4 PR3+
1
UL4 RJ45_MIDI1+ 3
CL39 1000P_0402_50V7K PR2+ DL1
For P/N and footprint
1
1 24 2 1 1 8111E@ 2 RJ45_MIDI0- 2 AZC199-02SPR7G_SOT23-3
Please place them to ISPD page LAN_MDI3- TCT1 MCT1 RJ45_MIDI3- PR1-
2 23 8111E@ RL11 75_0402_1% @
TD1+ MX1+
3
SA00003PO30 LAN_MDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI0+ 1
TD1- MX1- CL40 1000P_0402_50V7K PR1+
3
UL1 4 21 2 1 1 8111E@ 2 9
LAN_MDI2- TCT2 MCT2 8111E@ RL12 75_0402_1% RJ45_MIDI2- SHLD1
5 20
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+
6 19 10
TD2- MX2- SHLD2
3
CL41 1000P_0402_50V7K
7 18 2 1 1 2 @
3
LAN_MDI1- TCT3 MCT3 RL13 75_0402_1% RJ45_MIDI1- SANTA_130452-C
8 17
8105E-VL 10/100M LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ @ AZC199-02SPR7G_SOT23-3
9 TD3- MX3- 16
1
8105E@ CL42 1000P_0402_50V7K DL2
10 15 2 1 1 2 8/30 Reserve DL1 and DL2 for ESD request
1
LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0-
11 TD4+ MX4+ 14
LAN_MDI0+ 12 13 RJ45_MIDI0+
TD4- MX4-
RJ45_GND 1 2 LANGND
Place CL34, CL35 colse 1 1 CL36 1000P_1808_3KV7K 1 1
to LAN chip @ SUPERWORLD_SWG150401 CL37 CL38
4 CL35 CL34 8111E@ 4.7U_0603_6.3V6K 4
0.1U_0402_25V4K 0.1U_0402_25V4K 220P_0402_50V6K @
2 2 2 2

PCIe-LAN-RTL8105E/8111E
Custom 1.0
PWWHA LA-7202P M/B
A B C D E
5 4 3 2 1
D D
For EMI request
1 2
@ CC2 100P_0402_50V8J
@ RC6 10_0402_5% @ CC10 10P_0402_50V8J
48MCLK_CR 1 2 1 2
RC2
6.19K_0402_1%
2 1
Close to IC UC1
1 REFE
GPIO0 17 0620 --> remove CR_LED#
RC1 2 1 0_0402_5% USB20_N10_R 2
<19> USB20_N10 DM
RC3 2 1 0_0402_5% USB20_P10_R 3 24 48MCLK_CR < 48MHz >
<19> USB20_P10 DP CLK_IN 48MCLK_CR <16>
+3VS 4 3V3_IN XD_D7 23

+VCC_3IN1 5 CARD_3V3
+V1_8 6 22
V18 SP14 SD_DATA2_MS_DATA5
1 SP13 21 0620 --> remove CARD-RADER LED
CC7 7 20 MS_DATA1_SD_DATA3
1U_0402_6.3V6K XD_CD# SP12
SP11 19
SDW P_MSCLK 8 18 SDCMD
2 SP1 SP10
9 SP2 SP9 16
SD_DATA1 10 15 MS_DATA2_SDCLK
SP3 SP8
EPAD
SD_DATA0 11 14
SP4 SP7 SDCD#
CC3, CC4, CC5, CC6, 12 SP5 SP6 13
CC7, RC2, RC3, UC1
RTS5137-GR_QFN24_4X4
form CARD@ to mount
25
C C
0715 --> change P/N to RTS5137 (SA000043500)
< 2 in 1 Card Reader >

0624 --> change CARDREADER conn.
JREAD @
MS_DATA1_SD_DATA3
D3 1 SDCMD
CMD 2
VSS1 3
VDD 4 MS_DATA2_SDCLK
+VCC_3IN1
CLK 5
VSS2 6 1
CC6
1
CC5
7 SD_DATA0
D0 SD_DATA1 0.1U_0402_16V4Z 1U_0402_6.3V6K
D1 8
SD_DATA2_MS_DATA5 2 2
D2 9
10 SDW P_MSCLK
WP SDCD#
CD 11
GND1 12
GND2 13
GND3 14
GND4 15
B B
TAITW _PSDAT3-09GLAS1N14N
For EMI request
@ RC4 10_0402_5% @ CC8 10P_0402_50V8J

MS_DATA2_SDCLK 1 2 1 2
@ RC5 10_0402_5% @ CC9 10P_0402_50V8J

SDW P_MSCLK 1 2 1 2
A A

PCIe-CardReader RTS5137
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
5 4 3 2 1
Codec 600 mA RA2

+PVDD1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +5VS
Beep sound
1 1 0_0603_5% 1 1
CA57 CA56 CA44 CA43
2 2 2 2
+3VS 1 2 0.1U_0402_16V4Z +DVDD_IO 10U_0603_6.3V6M 10U_0603_6.3V6M
RA19 0_0603_5%
1 1 EC Beep RA7
CA2 CA1 1 2
<30> EC_BEEP#
+1.5VS 1 @ 2 47K_0402_5%
RA20 0_0603_5% 10U_0603_6.3V6M +3VS_DVDD
2 2
D D
place close to chip
PCI Beep RA8
CA13
RA1 0.1U_0402_16V4Z 35 mA <15> PCH_SPKR 1 2 1 2 MONO_IN
+3VS 2 1 47K_0402_5%
0_0603_1% 1 1 0.1U_0402_16V4Z
CA8 +AVDD
CA7 RA3
10U_0603_6.3V6M 68 mA 10U_0603_6.3V6M 0.1U_0402_16V4Z 1 2 +5VS
2 2 0_0603_5%
1
1
39
46
25
38
1 1 1 1
9
UA1 CA3 CA4 CA5 CA6 RA12 CA18
4.7K_0402_5% 100P_0402_50V8J
PVDD1
PVDD2
AVDD1
AVDD2
DVDD_IO
DVDD
2
place close to chip
2
2 2 2 2
10U_0603_6.3V6M 0.1U_0402_16V4Z
23 LINE1_L SPK_OUT_L+ 40 SPKL+ <29>

24 LINE1_R SPK_OUT_L- 41 SPKL- <29>
14 LINE2_L SPK_OUT_R+ 45 SPKR+ <29>
4.7U_0805_10V4Z CA23 15 44
LINE2_R SPK_OUT_R- SPKR- <29>
<29> MIC1_R_L 2 1
Ext. Mic 21 32 RA4 75_0402_1%
MIC1_L HP_OUT_L HP_L <29>
<29> MIC1_R_R 2 1 22 MIC1_R HP_OUT_R 33 RA5 75_0402_1%
HP_R <29> place close to chip
4.7U_0805_10V4Z CA29
AZ_BITCLK_HD
Int. Mic 16
17
MIC2_L @
C MIC2_R @ C
SYNC 10 AZ_SYNC_HD <15> 1 2 1 2
+3VS R746 10_0402_5%
INT_MIC_DATA 2 6 CA80 22P_0402_50V8J
<13> INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <15>
@
2
INT_MIC_CLK RA46 3 close to Audio Codec(UA1) for EMI AZ_SYNC_HD 1 2
<13> INT_MIC_CLK GPIO1/DMIC_CLK
1 FBMA-10-100505-301T 5 AZ_SDOUT_HD <15> R235
SDATA_OUT 4.7K_0402_5% @ CA81 22P_0402_50V8J
CA83 EC_MUTE#
4 PD# 8 AZ_SDIN0_HD_R 2 1 @
<30> EC_MUTE# SDATA_IN AZ_SDIN0_HD <15>
27P_0402_50V8J @ RA6 33_0402_5% AZ_RST_HD# 1 2
1
2
EC_MUTE# 11 47 CA82 22P_0402_50V8J
<15> AZ_RST_HD# RESET# EAPD
SPDIFO 48
1
1 2 MONO_IN 12
RA45 CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
4.7K_0402_5% SENSE_A 13 SENSE A

29 place close to chip
2
MIC2_VREFO
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R
EC control EC_MUTE# behavior: 1 2 36 CBP LDO_CAP 28 1 2
CA15 CA28
High-state / low-state 2.2U_0603_6.3V6K 35 27 AC_VREF 10U_0603_6.3V6M
CBN VREF +MIC1_VREFO_R +MIC1_VREFO_L
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
MIC1_VREFO_L JDREF
1 1
43 34 1 2 CA16
PVSS2 CPVEE CA14 2.2U_0603_6.3V6K CA17 10U_0603_6.3V6M
42 PVSS1 1 1
CA47 1 2 0.1U_0603_50V7K 49 26 @ @ @
B DVSS2 AVSS1 2 2 CA37 CA36 B
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V6K 1U_0402_6.3V6K
ALC259-GR_QFN48_7X7 2 2
CA49 1 2 0.1U_0603_50V7K place close to chip
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA18 0_0603_5%
RA18 CLOSE TO ALC259
Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
<29> MIC_SENSE 2 1
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A <29> NBA_PLUG
RA21 39.2K_0402_1%
10K PORT-C (PIN 23, 24)
5.1K (PIN 48)

A A
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17) Int. MIC
10K PORT-H (PIN 20)

HDA-ALC259
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
Speaker Connector Ext. Mic RA31 2 1 +MIC1_VREFO_L
1K_0402_5% RA32 2.2K_0402_5%
2 1 MIC1_L
<28> MIC1_R_L
placement near Audio Codec UA1 <28> MIC1_R_R 2 1 MIC1_R
1K_0402_5%
RA22 2 1 +MIC1_VREFO_R
RA33 2.2K_0402_5%
RA30
SPKR+ 2 1 SPK_R1
<28> SPKR+
0_0603_5% 1
CA25
@ 470P_0402_50V8J 2
2 CA27
1 1U_0402_6.3V6K
@
CA26 1
RA34 @ 470P_0402_50V8J
SPKR- 2 SPK_R2
<28> SPKR- 2 1
0_0603_5%
RA35
SPKL+ 2 1 SPK_L1
<28> SPKL+
0_0603_5% 1
CA19
@ 470P_0402_50V8J 2
2 CA24
1 1U_0402_6.3V6K
@
CA20 1
RA36 @ 470P_0402_50V8J
SPKL- 2 SPK_L2
<28> SPKL- 2 1
0_0603_5%
HeadPhone/LINE Out JACK

JLINE
5 5
@ DA4 PJDLC05_SOT23-3
3 <28> NBA_PLUG 4 4 GND 10
1 GND 9
2 LA6 1 2 HP_R_L 3 8
<28> HP_R 3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
JSPK LA7 1 2 HP_L_L 2
<28> HP_L 2
SPK_L1 1 KC FBM-L11-160808-121LMT 0603 1
SPK_L2 1 1
2 2
SPK_R1 3 1 FOX_JA63331-B39S4-7F
SPK_R2 3 @
4 4 3
1 CA45 CA46 CA11 @
@ DA5 PJDLC05_SOT23-3 ACES_85204-0400N 2 100P_0402_50V8J 100P_0402_50V8J
@ 2
3
1 DA6 @ 0.1U_0402_16V4Z
2 PJDLC05_SOT23-3
For EMI
Ext.MIC/LINE IN JACK
JEXMIC
5 5
<28> MIC_SENSE 4 4 GND 10

GND 9
MIC1_R LA8 1 2 MIC1_L_R 3 8
3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
MIC1_L LA9 1 2 MIC1_L_L 2 2
KC FBM-L11-160808-121LMT 0603 1 1
FOX_JA63331-B39S4-7F
3 1 @
1
2 CA41 CA42 CA21
100P_0402_50V8J 100P_0402_50V8J
DA7 @ 2
PJDLC05_SOT23-3 0.1U_0402_16V4Z
For EMI

AUDIO AMP/MIC/SPK/VR
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
+3VL R737
+3VL 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 H_PROCHOT# <5,35>
<41> VR_HOT#
1 1 1 1 2 2 C442
C436 1 2
1
C437 C438 C439 C440 C441 D
For EMI 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z H_PROCHOT#_EC 2 Q41 C518
2 2 2 2 1 1 G 47P_0402_50V8J
2
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K S 2N7002_SOT23
22
33
96
67
3
9
CLK_PCI_EC U19 930@
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
1
R377
10_0402_5%
@ GATEA20 1 21
<20> GATEA20 GATEA20/GPIO00 PWM0/GPIO0F
KB_RST# 2 23 EC_BEEP#
<20> KB_RST# EC_BEEP# <28>
2
D KBRST#/GPIO01 BEEP#/PWM1/GPIO10 D
1 SERIRQ 3 PWM Output 26 FANPWM BATT_TEMPA 1 2
<15,31> SERIRQ SERIRQ# FANPWM0/GPIO12 FANPWM <5>
C443 LPC_FRAME# 4 27 ACOFF C445 100P_0402_50V8J
<15,31> LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF <36>
22P_0402_50V8J LPC_AD3 5 ACIN_D 1 2
<15,31> LPC_AD3 LPC_AD3/LAD3
@ LPC_AD2 7 C446 100P_0402_50V8J
2 <15,31> LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA
<15,31> LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA <35>
LPC_AD0 10 64
<15,31> LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
LPC & MISC 65 ADP_I
ADP_I/AD2/GPI3A ADP_I <35,36>
CLK_PCI_EC 12 66 ADP_V
<19> CLK_PCI_EC CLK_PCI_EC/PCICLK AD3/GPI3B ADP_V <36>
PLT_RST# 13 AD Input 75
<5,19,25,26,31> PLT_RST# PCIRST#/GPIO05 AD4/GPI42
ECRST# 37 76
+3VL R378 EC_SCI# EC_RST#/ECRST# AD5/GPI43
<20> EC_SCI# 20
47K_0402_5% EC_SCI#/GPIO0E +3VS
38
ECRST# CLKRUN#/GPIO1D
2 1 68
DAC_BRIG/DA0/GPO3C
70 EN_DFAN1 <5>
EN_DFAN1/DA1/GPO3D IREF
2 1 DA Output IREF/DA2/GPO3E
71 IREF <36>
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ R758 10K_0402_5%
KSI0/GPIO30 DA3/GPO3F CHGVADJ <36>
KSI1 56 H_PROCHOT#_EC 1 2
KSI2 KSI1/GPIO31 @
57
KSI3 KSI2/GPIO32 EC_MUTE#
58 83 EC_MUTE# <28>
KSI4 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN# +5VS
59 84 USB_EN# <24>
KSI5 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B
60 85
KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C H_PROCHOT#_EC
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
KSI7 62 87 TP_CLK TP_CLK 1 2
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <32>
KSO0 39 88 TP_DATA R379 4.7K_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <32>
KSO1 40 TP_DATA 1 2
KSO2 KSO1/GPIO21 R381 4.7K_0402_5%
41
KSO3 KSO2/GPIO22 VGATE
42 97 VGATE <5,17,41>
KSO4 KSO3/GPIO23 SDICS#/GPXIOA00 WOL_EN
43 98 WOL_EN <26>
KSO5 KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 PWRME_CTRL#
KSO5/GPIO25 Int. K/B For EMI
44 99 PWRME_CTRL# <15>
KSO6 ME_EN/SDIMOSI/GPXIOA02 LID_SW#
45 109
KSO7 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 LID_SW# <31>
46
KSO7/GPIO27 SPI Device I/F
KSO8 47
KSO9 KSO8/GPIO28 EC_SI_SPI_SO SPI_CLK_R
48 119 EC_SI_SPI_SO <31> 2 1 SPI_CLK <31>
C KSI[0..7] KSO10 KSO9/GPIO29 SPIDI/MISO EC_SO_SPI_SI R738 0_0402_5% C
<31> KSI[0..7] 49 120 EC_SO_SPI_SI <31>
KSO11 KSO10/GPIO2A SPIDO/MOSI SPI_CLK_R
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 1
KSO[0..17] KSO12 51 128 SPI_CS# C449
<31> KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# <31>
KSO13 52 33P_0402_50V8J
KSO14 KSO13/GPIO2D @
53
KSO15 KSO14/GPIO2E 2
54 73
RP7 KSO16 KSO15/GPIO2F GPIO40 EC_PECI
81 74 1 930@ 2 H_PECI <5>
EC_SMB_CK1 KSO17 KSO16/GPIO48 H_PECI/GPIO41 FSTCHG R461 43_0402_1%
+3VL 1 8 82
KSO17/GPIO49 GPIO FSTCHG/GPIO50
89 FSTCHG <36>
2 7 EC_SMB_DA1 90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# <32>
+3VS 3 6 EC_SMB_CK2 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <31>
4 5 EC_SMB_DA2 EC_SMB_CK1 77 92 BATT_CHG_LOW_LED#
<35> EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# <32>
EC_SMB_DA1 78 93 SYSON 1 2
<35> EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55
2.2K_0804_8P4R_5% EC_SMB_CK2 79 95 SYSON R5 4.7K_0402_5%
<16> EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON <38>
EC_SMB_DA2 80 121 VR_ON
<16> EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <41>
127 ACIN_D
AC_IN/GPIO59
SM Bus
PM_SLP_S3# 6 100 PCH_RSMRST#
<17> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 PCH_RSMRST# <17>
SLP_S5# 14 101 EC_LID_OUT# R341 330K_0402_5%
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <16>
EC_SMI# 15 102 EC_ON +3VL 1 2
<20> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_ON <32>
16 103
GPIO0A EC_SWI#/GPXIOA06 PM_PWROK D21
17 104 PM_PWROK <5,17>
USB_OC#0_RR GPIO0B ICH_PWROK/GPXIOA07 BKOFF# ACIN_D
18
GPIO0C GPIO BKOFF#/GPXIOA08
105 BKOFF# <13> 2 1 ACIN <17,36>
PCH_SUSPWRDN 19 GPO RF_OFF#/GPXIOA09 106
<17> PCH_SUSPWRDN SUS_PWR_DN_ACK/GPIO0D
25 107 RB751V40_SC76-2
@ FAN_SPEED1 INVT_PWM/PWM2/GPIO11 GPXIOA10 SA_PGOOD
<5> FAN_SPEED1 28 108 SA_PGOOD <39>
PLT_RST# FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 @
1 2 29
C819 1U_0402_6.3V6K E51_TXD FANFB1/GPIO15
<25> E51_TXD 30 2 1
E51_RXD EC_TX/GPIO16 R740 0_0402_5%
<25> E51_RXD 31 110
@ ON/OFFBTN# EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 UMA_ENBKL
<32> ON/OFFBTN# 32 112 UMA_ENBKL <18>
SUSP# PWR_LED# ON_OFF/GPIO18 ENBKL/GPXIOD02
1 2 <32> PWR_LED# 34 114
C820 180P_0402_50V8J NUM_LED# SUSP_LED#/GPIO19 EAPD/GPXIOD03
<31> NUM_LED# 36
NUM_LED#/GPIO1A GPI EC_THERM#/GPXIOD04 115 To avoid current leakage
116 SUSP#
SUSP#/GPXIOD05 SUSP# <33,38,40>
B 117 PBTN_OUT# B
PBTN_OUT#/GPXIOD06 PBTN_OUT# <5,17>
118 USB_OC#0_R
EC_PME#/GPXIOD07
122
XCLK1
<17> CLK_EC 2 930@ 1 123 124 +EC_V18R
R743 0_0402_5% XCLK0 V18R
Close to EC
AGND
GND
GND
GND
GND
GND
C448 SUSP# R423 2 1 10K_0402_5%

1
1 4.7U_0805_10V4Z
R1446 KB930QF-A1_LQFP128_14X14 VR_ON R462 2 1 10K_0402_5%
11
24
35
94
113
69
100K_0402_5% C899
930@ 20P_0402_50V8J
2 930@
2
+3VALW Co-lay KB9012 with KB930

C818 @
2 1
5
U44 0.1U_0402_16V4Z 9012@ 9012@

1 USB_OC#0_RR 2 R744 1 EC_PECI 2 R742 1
P
<17> PM_SLP_S5# IN1

4 SLP_S5# 0_0402_5% 0_0402_5%
O
<17> PM_SLP_S4# 2
IN2
R744 close to R461
G
SN74AHC1G08DCKR_SC70-5
3
@ USB_OC#0_R 2 930@ 1 USB_OC#0 <19,24>

R741 0_0402_5%
2 1
R739 0_0402_5% 1 9012@ 2 H_PECI
R475 43_0402_1%
U19 9012@
A A
1 2 E51_TXD
R342 100K_0402_5% EC KB9012 A1

LPC-EC-KB930
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
Place the PAD under DDR DIMM.
SPI Flash (256KB) Lid SW LPC Debug Port
+3VL +3VS H7 @
+3VL R403
1 2 6 5
0_0402_5%
20mils +3VALW
1
C451 U22 930@ @ R401 1 2 7 4
<15,30> SERIRQ PLT_RST# <5,19,25,26,30>
0.1U_0402_16V4Z 8 4 +3V_LID 1 2 R392 0_0402_5%
930@ VCC VSS 0_0402_5%
2
3 W <15,30> LPC_AD3 8 3 LPC_AD2 <15,30>
1
7 R383
HOLD
47K_0402_5% <15,30> LPC_AD1 9 2 LPC_AD0 <15,30>
SPI_CS# 1 U21
<30> SPI_CS# S APX9132ATI-TRL_SOT23-3
2
SPI_CLK 6 10 1
<30> SPI_CLK C <15,30> LPC_FRAME# CLK_PCI_DDR <19>
2 3
GND
VDD VOUT LID_SW # <30>
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
<30> EC_SO_SPI_SI D Q EC_SI_SPI_SO <30>
2
W 25X10BVSNIG_SO8 1 1 DEBUG_PAD R393
1
22_0402_5%
C453 C452 @
0.1U_0402_16V4Z 10P_0402_50V8J
1
2 2
2
SPI_CLK 1 930@ 2 1 2 930@
R394 10_0402_5% C454 10P_0402_50V8J C457
22P_0402_50V8J
1 @
For EMI
For EMI
For EMI
Close to JKB
KSO16 1 2
C401 100P_0402_50V8J
KSO17 1 2
C402 100P_0402_50V8J
KSO2 1 2
C404 100P_0402_50V8J
KSO1 1 2
C405 100P_0402_50V8J
KSO0 1 2
C406 100P_0402_50V8J
KSO4 1 2
KEYBOARD CONN. KSO3
C407
1
100P_0402_50V8J
2
C408 100P_0402_50V8J
KSO5 1 2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] <30>
KSO14 1 2
KSO[0..17] C410 100P_0402_50V8J
KSO[0..17] <30>
KSO6 1 2
C411 100P_0402_50V8J
KSO7 1 2
JKB C412 100P_0402_50V8J
JKB34 1 2 +3VS KSO13 1 2
34 KSO16 R372 300_0402_5% C413 100P_0402_50V8J
33 KSO8
32 1 2
KSO17 C415 100P_0402_50V8J
31 KSO9
30 1 2
C416 100P_0402_50V8J
29 KSO2 KSO10
28 1 2
KSO1 C417 100P_0402_50V8J
27 KSO0 KSO11
26 1 2
KSO4 C418 100P_0402_50V8J
25 KSO3 KSO12
24 1 2
KSO5 C419 100P_0402_50V8J
23 KSO14 KSO15
22 1 2
KSO6 C420 100P_0402_50V8J
21 KSO7 KSI7
20 1 2
KSO13 C421 100P_0402_50V8J
19 KSO8 KSI2
18 1 2
KSO9 C422 100P_0402_50V8J
17 KSO10 KSI3
16 1 2
KSO11 C423 100P_0402_50V8J
15 KSO12 KSI4
14 1 2
KSO15 C424 100P_0402_50V8J
13 KSI7 KSI0
12 1 2
KSI2 C425 100P_0402_50V8J
11 KSI3 KSI5
10 1 2
KSI4 C427 100P_0402_50V8J
9 KSI0 KSI6
8 1 2
KSI5 C429 100P_0402_50V8J
7 KSI6 KSI1
6 1 2
KSI1 C431 100P_0402_50V8J
5
4
JKB4 2 1 +3VS CAPS_LED# 1 2
CAPS_LED# R376 300_0402_5% C433 100P_0402_50V8J 2010/09/03 2012/12/31 Title
3 CAPS_LED# <30> Issued Date Deciphered Date
NUM_LED#
2 NUM_LED#
NUM_LED# <30>
1
C435
2
100P_0402_50V8J SPI ROM/LID/Debug/KB
1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ACES_88170-3400 1.0
@
PWWHA LA-7202P M/B
5 4 3 2 1
+3VL
Power Button 51_ON# <34>
TP Button/Conn.
2
For debug R395
1
D
100K_0402_5% 2 Q7
<30> EC_ON 2N7002_SOT23-3
G
LEFT
2
ON/OFFBTN# S SW1
ON/OFFBTN# <30>
3
TOP side R396 SW_L 1 3
1 10K_0402_5%
C458 2 4 JTOUCH @
0.1U_0402_25V6 1
1
@ SMT1-05_4P +5VS 1
<30> TP_CLK 2
6
5
2 2
<30> TP_DATA 3
SW3 @ SW_L 3
4
SW_R 4
1 3 5 7
D 5 G7 D
6 8
6 G8
BTM side 2 4 For EMI request RIGHT 2
SW4 1 P-TWO_161021-06021_6P-T
SMT1-05-A_4P SW_R 1 3 3
6
5
PWR/B to MB Conn. 2 4 D19 @

AZ5125-02S.R7G_SOT23-3
SMT1-05_4P
6
5
3
2
JPOWER @ 0816->change JTOUCH connector
1 ON/OFFBTN#
1 D20 @
2
2 AZ5125-02S.R7G_SOT23-3
3
3
3
4
4 D83 @
5
1
G1
6 AZ5125-02S.R7G_SOT23-3
G2
ACES_85201-0405N
For EMI request
1
For ESD
POWER/SUSPEND LED Screw Hole

H6 H8 H9 H10 H11 H12 H13 H14
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
Vf=1.9V~2.4V @ @ @ @ @ @ @ @
If=5mA
1
D22
+5VALW 1 2 2 1 PWR_LED# <30>

C R398 510_0402_5% YG H1 H26 C
H_2P7x3P2N H_2P7N
HT-110UYG5_YELLOW GREEN @ @
3
1
SB
BATT CHARGE/FULL LED
H15 H16
H_5P0N H_5P0N
CPU @ @
1
Vf=1.8V~2.0V H23 H21 H22 H20
If=5mA(max) H_4P7 H_4P2x4P7 H_4P2x4P7 H_4P2
@ @ @ @
1
D25
2 1 2 BATT_CHG_LOW_LED# <30>
+5VALW 1 A R399 510_0402_5%
MINI CARD -- WLAN
3 1 2 BATT_FULL_LED# <30>
YG R404 510_0402_5% H18 H19
H_3P3 H_3P3
HT-210UD5-UYG5_AMBER-YEL GRN @ @
1
B B
PCB Fedical Mark PAD

FD1 FD2 FD3 FD4
@ @ @ @
1
ISPD
U2 Q65R1@ ZZZ
PCH PCB LA-7202P
PJP1 45@
PJP1
A A

PWR&TP CON/LED/ISPD
1.0
PWWHA LA-7202P M/B
5 4 3 2 1
A B C D E
+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

Vgs=10V,Id=9A,Rds=18.5mohm +1.8VS
+3VALW +3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW +5VS +1.5V +1.5VS
4.7U_0805_10V4Z
2
4.7U_0805_10V4Z +5VS Vgs=10V,Id=14.5A,Rds=6mohm
1 1 1 1 1 1 R470
Q29 C460 4.7U_0805_10V4Z Q30 C462 Q31 WPS3@ C464 470_0805_5%
470_0805_5%
470_0805_5%
470_0805_5%
8 C459 C461 For EMI C463
S 1
8
S 1
8
D D D S 1
2
Q31
OLS@
7
S 2
7
S 2
7
1U_0402_6.3V6K 1U_0402_6.3V6K S 2 1U_0402_6.3V6K
OLS@
1
D 2 2 D 2 2 D 2 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
6 R406 R407 R408
S 3
6
S 3
6
D D D S 3
5 4 5 4 2 2 5 4
D G D G OLS@ C822 C821 D G
OLS@
1
1 SI4800BDY_SO8 D 1
1 R409 2 +VSB SI4800BDY_SO8 1 R410 2 +VSB SI4800BDY_SO8 1 R411 2 +VSB Q190
3 1
3 1
3 1
0.022U_0402_25V7K
0.01U_0402_25V7K
4.7U_0805_10V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1 OLS@ 1 47K_0402_5% 1 OLS@ 1 47K_0402_5% @ @ 1 1 220K_0402_5% 2 SUSP
6
1 1
0.1U_0402_25V6
OLS@
C466 FDS6676AS_SO8 G
OLS@
C470
C465 R412 Q10A C467 C468 R413 Q11A C469 R414 Q12A PS3@ S 2N7002_SOT23-3
3
330K_0402_5% OLS@ Q10B 200K_0402_5% OLS@ Q11B 820K_0402_5% Q12B
2 2 OLS@ SUSP 2 2 @ SUSP 2 2 SUSP
2 5 2 5 OLS@ 2 5
2N7002DW-T/R7_SOT363-6 OLS@ 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2
2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
4
+5VS TO +5VS_ODD
+5VS
+5VS_ODD +3VALW
+3VS +5VS For S3 CPU Power Saving
2
+5VALW +0.75VS +1.05VS_VCCP
2
2
@ @ C471 Vgs=-4.5V,Id=3A,Rds<97mohm R425

R457 R441 0.1U_0402_16V7K 100K_0402_5%
2
470_0805_5% @ 10K_0402_5% @ PS3@
5
2
Q53B 1 @ R422 R421 R468
1
3
S
@R440
@ R440 Q45 PJ28 100K_0402_5% 22_0805_5% 470_0805_5%
2
0.75VR_EN# <40>
1
G
<20> ODD_EN# 4 3 1 2 2 JUMP_43X79
3
@
1
6
+5VS_ODD
1
2N7002DW-T/R7_SOT363-6 47K_0402_5% 2
D SUSP
<5,9,25,40> SUSP
1
Q53A @ AO3413_SOT23 PS3@ Q44B
1
C217 <39,40> VCCPPWRGD 1 2 0.75VR_EN 5 2N7002DW-T/R7_SOT363-6
1
2 ODD_EN# R158 100K_0402_5% PS3@ D Q189 D Q60 2
2 0.01U_0402_25V7K
1
1 @ D Q61 SUSP 2N7002_SOT23-3
1 2 2
4
6
2N7002DW-T/R7_SOT363-6 1 Q44A 2 2N7002_SOT23-3 G G
<30,38,40> SUSP#
1
C680 2N7002DW-T/R7_SOT363-6 G S 2N7002_SOT23-3 S
3
C679 1U_0402_6.3V6K PS3@ S
3
4.7U_0805_10V4Z 2 @ SUSP 2
@ 2
1
+3VALW +5VALW
Each 250pF on CAP_MOS1 (2) will make

Slew Rate(uS/V) increase of 100uS/V
+5VS +3VS
U46 NLS@
1 10
SUSP# R415 MOS1_D MOS1_S
2 1
0.01U_0402_25V7K
0_0402_5% 1
3 NLS@ 2 9 3
@
ON_MOS1 CAP_MOS1 C249

1 1
C236
C496
0.1U_0402_16V4Z
2 0.1U_0402_16V4Z @
3 8
5_VDD GND @
2 2
4 7
ON_MOS2 CAP_MOS2
+5VALW
5 6
MOS2_D MOS2_S
11
GND
0.01U_0402_25V7K
1 SLG59M232VTR_TDFN14-10_3X2 1 1 C255
NLS@
C252 0.1U_0402_16V4Z
120P_0402_50V4Z @
C500
2 NLS@
2 2
SUSP# 2 R419 1
0.01U_0402_25V7K
0_0402_5% 1
NLS@
@
C499
2
4 4

DC-DC INTERFACE
1.0
PWWHA LA-7202P M/B
A B C D E
A B C D
1 2
@ PR1
@ 1K_1206_5%
VIN PD1
PL1 2 1 N3 1 2
PF1 SMB3025500YA_2P VIN B+
DC_IN_S1 1 2 DC_IN_S2 1 2 RLS4148_LL34-2 @ PR2
@ PJP1
1K_1206_5%
1 10A_125V_451010MRL
+
1 2
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
+ 2 @PR3
1
3 1K_1206_5%
PC4
PC1
PC2
PC3
1
- 1
1
4
2
- @ PR4 @ PR5
SINGA_2DW -0005-B03 100K_0402_1% 2.2M_0402_5% PR38 @
1 2 2 1 511K_0402_1%
VL
2
N1
@ PD2
8
RB715F_SOT323-3 @ PU2B
2 5
P
<37> EN0 +
1 7 O
<36> ACON 3 6 2 1
VIN -
1
LM393DG_SO8 PR6 @ PR35 @
1
PD3 34K_0402_1% 255K_0402_1% PC14 @
<36>
PR36 @ 1000P_0402_50V7K
6251VREF
RLS4148_LL34-2 @ PC13 @ PR7 150K_0402_1%
2
1000P_0402_50V7K 66.5K_0402_1%
2
1
@
2
PC16
1
1000P_0402_50V7K
2
1
1
@ PR39
1
PR8 D 47K_0402_1%
PR9
@ PQ1
PQ4 68_1206_5% 68_1206_5% 2 2 1
SSM3K7002FU_SC70-3 G PACIN <36>
TP0610K-T1-E3_SOT23-3
PD4 S
3
2 1 N1 3 1
BATT+ VS
1
2 2
RLS4148_LL34-2
1
N1
1
PR10 PC6
1
100K_0402_1% 0.22U_0603_25V7K PC5 2 +5VALW P
8
PU2A
2
0.1U_0603_25V7K
3
2
P
+ @
PR11 1 PQ2
1 2 O DTC115EUA_SC70-3
<32> 51_ON# 2
3
-
G
22K_0402_1%
LM393DG_SO8
4
@
@ PJ332
+3VALW P 2 2 1 1 +3VALW
@ PJ333 JUMP_43X118
2 1 @ PJ152
+3VLP 2 1 +3VL (5A,200mils ,Via NO.= 10)
2 1 1
JUMP_43X39 OCP=8.6A 2
JUMP_43X118
(100mA,40mils ,Via NO.= 2)
@ PJ352 @ PJ153
+5VALW P 2 2 1 1 +5VALW +1.5VP 2 2 1 1 +1.5V
JUMP_43X118 JUMP_43X118
3
(5A,200mils ,Via NO.= 10) (16A,640mils ,Via NO.= 32) 3
OCP=7.9A
@ PJ72
+VSBP 2 2 1 1 +VSB @ PJ182 @ PJ402
JUMP_43X39 +1.8VSP 2 1 +1.8VS 2 1
2 1 2 1
(120mA,40mils ,Via NO.= 1) JUMP_43X118 JUMP_43X118
(1.65A,70mils ,Via NO.= 4) @ PJ403
@ PJ76 OCP=4.2A 2 1
+1.05VS_VCCPP 2 1 +1.05VS_VCCP
+0.75VSP 2 2 1 1 +0.75VS JUMP_43X118
JUMP_43X79
@ PJ452
(1A,40mils ,Via NO.= 2)
+VCCSAP 2 2 1 1 +VCCSA
JUMP_43X118
(6A,240mils ,Via NO.= 12) (17A,680mils ,Via NO.=34)
@ PJ502
2 2 1 1
JUMP_43X118
@ PJ503 ACIN
+GFX_COREP 2 2 1 1 +GFX_CORE Precharge detector
4
JUMP_43X118 Min. typ. Max. 4
(33A,1320mils ,Via NO.=66)

OCP=40A H-->L 14.42V 14.74V 15.23V
L-->H 15.39V 15.88V 16.39V
DCIN/VIN DECTOR
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. PWWHA LA-7202 M/B
A B C D
A B C D
1
VMB 1
PL2
PH1 under CPU botten side :
@ PJP2 PF2 SMB3025500YA_2P
1 BATT_S1 1 2 1 2
CPU thermal protection at 95 degree C
1 BATT+
2 2
3 15A_65V_451015MRL
Recovery at 56 degree C
3 BATT_P4
4 4
5 BATT_P5
5
1
10 6 EC_SMDA PC8
GND 6 PC7
1
11 7 EC_SMCA @ PC15
GND 7 PR14 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K
12 8
2
GND 8 1K_0402_1%
13 GND 9 9
SUYIN_200045MR009G171ZR
2
PD6
VL
1
PJSOT24C_SOT23-3
1
PD5 2
PJSOT24C_SOT23-3 1 PR15
3
1
PR16 19.6K_0402_1%
6.49K_0402_1% PC9
2
2
2 1 0.1U_0603_25V7K
2
+3VL
2
ADP_I <30,36>
PR18
1
8.66K_0402_1%
1
PR19 PU1
1
2
1 8 PR22 2
1
1K_0402_1% VCC TMSNS1 3.48K_0402_1%
PH1
2 7
2
GND RHYST1
2
100K_0402_1%_NCP15W F104F03RC
2
PR20 PR21 BATT_TEMPA <30> 3 6
2
OT1 TMSNS2
100_0402_1% 100_0402_1%
<37> VS_ON 4 OT2 RHYST2 5 1 2
1
1
G718TM1U_SOT23-8 PR28
EC_SMB_DA1 <30> 3.09K_0402_1% PR27
<5,30> H_PROCHOT# 100K_0402_1%
1
EC_SMB_CK1 <30>
2
1
D PR29
PQ7 2 10K_0402_1%
SSM3K7002FU_SC70-3 G
S
2
@ PJ334
2 1
+3VS
2 1
JUMP_43X39
PQ5
TP0610K-T1-E3_SOT23-3 Adapter Throttle Watt Recovery Watt Throttle Point Recovery Point
B+ 3 1 +VSBP 65W_UMA 71.25W 62.4W 1.48V 1.308V

3 3
0.22U_0603_25V7K
75W_DIS 85.5W 72W 1.78V 1.5V

100K_0402_1%
1
PC10
1
1
PR23
PC11 @
VL 0.1U_0603_25V7K
75W_QCore 85.5W 72W 1.78V 1.5V
@
2
2
2
PR24
2
1 2
PR25 22K_0402_1%
100K_0402_1%
1
D
PR26
1 2 2 PQ6
<17,37> POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1
@ PC12
.1U_0402_16V7K
2
4 4

BATTERY CONN / OTP
1.0
PWWHA LA-7202 M/B
A B C D
A B C D
PQ208
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
AO4435L_SO8
1 8
1
PC207
PC208
PC209
2 7
3 6
PQ203 PR215 5
PQ204 B+ CHG_B+
2
AO4435L_SO8 P2 P3 0.02_1206_1%
AO4409L_SO8
PL210
4
8 1 1 8 1 4 1 2
VIN 7 2 2 7 1.2UH_1231AS-H-1R2N=P3_2.9A_30%
6 3 3 6 2 3 CSIN
5 5
CSIP
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
VIN
1
1 1
PC231
PC232
PC233
2
PC211 PR236
1 2
VIN
2
1
5600P_0402_25V7K
47K_0402_1%
1
1
2
0.1U_0603_25V7K
6251VDD
PR210 LDO 5.075V PD9
47K_0402_1% PR212 PR226 PR237
2
ACSETIN ACOFF
PC210
191K_0402_1% 1 2
200K_0402_1% 10K_0402_1%
2
2.2U_0603_6.3V6K
PD201 1SS355_SOD323-2
1 1
PQ210 RB751V-40_SOD323-2 ACSETIN
1000P_0402_25V8J
1
PC212
DTA144EUA_SC70-3 1 PR290 2
VIN
1 1
3
1
1.26V
1
PC217
200K_0402_1%
2
PR228 PD10
PR227 14.3K_0402_1% PQ215
2 2 1 2
2
PR216 10_1206_5% DTC115EUA_SC70-3
2
10K_0402_1% 1SS355_SOD323-2
2
2 1 PU200
<30> FSTCHG
1
1
PC218 PC222
3
1 24 DCIN 2 1
VDD DCIN 0.1U_0402_25V6
1
2
0.1U_0603_25V7K
PR213 PR217
2 2 23 ACPRN
100K_0402_1% ACSET ACPRN
PQ211 150K_0402_1%
DTC115EUA_SC70-3 PR229 20_0402_5%
2
2
6251_EN 3 22 1 2 CSON
EN CSON
6
2
D
1
D
PC219
3
5
6
7
8
2 0.047U_0402_16V7K PACIN 2
G 4 21 1 2 CSOP PQ201 G
1
CELLS CSOP
PR230 20_0402_5% AO4466L_SO8 PQ216 S
3
S PQ212A PC213 SSM3K7002FU_SC70-3
1
2
DMN66D0LDW -7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5% 2
ICOMP CSIN
2
PC220 4
PQ212B PC214 PR218 6800P_0402_25V7K
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 VCOMP CSIP 19 1 2
1
3
D PL202
10K_0402_1% PR232 2_0402_5% PR235
5 0.01U_0402_25V7K PR219 10UH_MSCDRI-104A-100M-E_4.6A_20% BATT+
3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG
CHG1 4
<30,35> ADP_I ICM PHASE
100_0402_1%
1
5
6
7
8
S PC215 2 3
4
PR211 1 2
<34> 6251VREF 6251VREF 8 17 DH_CHG PQ202
VREF UGATE PR206
22K_0402_5% PR220 AO4466L_SO8 0.02_1206_1%
PACIN 154K_0402_1% .1U_0402_16V7K PC205 4.7_1206_5%
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
<34> PACIN 1 2 PR205
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 @
<30> IREF CHLIM BOOT
2
1
2.2_0603_1% 4
1
0.01U_0402_25V7K
0.1U_0603_25V7K
PC202
PC203
PC204
PR222 PD202
1
1
6251VREF
1 2 6251aclim 10 15 6251VDDP
<34> ACON ACLIM VDDP
1
RB751V-40_SOD323-2 PC206
PC216
2
PR221 75K_0402_1%
1 2 6251VDD 680P_0603_50V7K
2
3
2
1
120K_0402_1% 11 14 DL_CHG
VADJ LGATE PR233 4.7_0603_5%
2
1
2
2
PC221
PQ213 PR223 12 13 4.7U_0603_6.3V6M
GND PGND
1
DTC115EUA_SC70-3 20K_0402_1%
ACOFF 2
<30> ACOFF
2
ISL6251AHAZ-T_QSOP24
3
PR224
<30> CHGVADJ 1 2
3
15.4K_0402_1% 3
2
PR225
31.6K_0402_1% 6251VDD
VIN
1
PR241
1
10K_0402_1%
1
PR240 1 2 ACIN <17,30>
47K_0402_1% PR242
PR246
10K_0402_1%
309K_0402_1%
CC=0.25A~3A 2
2
PACIN PR247
2
IREF=1.016*Icharge 10K_0402_1%
1
1 2 ADP_V <30>
IREF=0.254V~3.048V PQ214
DTC115EUA_SC70-3
1
VCHLIM need over 95mV
1
ACPRN 2 PR243 PR248 PC223
14.3K_0402_1% 47K_0402_1% .1U_0402_16V7K
2
CHGVADJ=(Vcell-4)*9.445
2
Vin Detector
3
Vcell CHGVADJ
4V 0V
High 18.089V
4.2V 1.882V
4
Low 17.44V 4
4.35V 3.2935V
1.26 / 14.3 * 205.3 = 18.089V
CP mode
Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A
Vaclim=1.08V(65W) PR222=75k PR223=20k PR215=0.02
Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.63A CHARGER
Vaclim=0.736V(75W) PR222=24k PR223=20k PR215=0.02 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
PWWHA LA-7202 M/B
A B C D
5 4 3 2 1
2VREF_8205
D D
1
PC363
1U_0603_10V6K
2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2
PR363 PR365
RT8205_B+ 20K_0402_1% 19.1K_0402_1%
HCB2012KF-121T50_0805
1 2 1 2 RT8205_B+
PL331
ENTRIP1
ENTRIP2
B+ 1 2 +3VLP PR337 PR357
10U_1206_25V6M
10U_1206_25V6M
@ 150K_0402_1% 150K_0402_1%
1
1
1 2 1 2 PC366
PC360
PC368
PC367
10U_1206_25V6M
1U_0805_25V7
2
2
@
4.7U_0805_10V6K
8
7
6
5
5
6
7
8
PU330
1
PQ331 PQ351
PC361
ENTRIP2
VFB2
TONSEL
VFB1
ENTRIP1
VREF
C AO4466L_SO8 C
25
2
P PAD
4 4
7 VO2 VO1 24 POK <17,35>
PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AO4466L_SO8
1
2
3
3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 VBST2 VBST1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 0_0603_5% 0_0603_5% PL352
UG_3V 10 21 UG_5V
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% DRVH2 DRVH1 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 LL2 LL1 20 1 2
8
7
6
5
5
6
7
8
1
1
PQ332 LG_3V 12 19 LG_5V
DRVL2 DRVL1
SKIPSEL
PR336 PR356
330U_6.3V_M
VREG5
4.7_1206_5% 4.7_1206_5%
VCLK
1 1
GND
EN0
VIN
4 <34> EN0 4
2
2
PC332 + +
PC352
PR360 TPS51125ARGER_QFN24_4X4 PQ352
13
14
15
16
17
18
330U_6.3V_M
1
1
PC336 499K_0402_1%
2 PC356 2
680P_0603_50V7K AO4712L_SO8 1 2 AO4712L_SO8
B+
1
2
3
3
2
1
680P_0603_50V7K
2
2
Ipeak=5A
1
100K_0402_5%
Imax=3.5A
1
VL
PR361
PC362
F=305KHz
1
1U_0402_6.3V6K
PC364
2
B Total Capacitor 150uF 4.7U_0805_10V6K
B
2
ENTRIP1 ENTRIP2 RT8205_B+ Ipeak=5A
2
Imax=3.5A
D D F=245KHz
6
2 5 Total Capacitor 150uF

PQ360A G G PQ360B
1
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6 PC365
S S
2VREF_8205
1
0.1U_0603_25V7K
2
PR370
VL 2 1
100K_0402_1%
1
<35> VS_ON
PR371
VS 1 2 2
100K_0402_1%
0.01U_0402_16V7K
42.2K_0402_1%
PQ361
1
DTC115EUA_SC70-3
PR372
PC370
3
2
2
A A

3VALWP/5VALWP
1.0
PWWHA LA-7202 M/B
5 4 3 2 1
A B C D
HCB2012KF-121T50_0805
PL151
1.5_B+ 1 2
1
B+ 1
10U_1206_25V6M
4.7U_0805_25V6-K
4.7U_0805_25V6-K
0.1U_0402_25V4K
680P_0402_50V7K
0.1U_0402_25V4K
0.1U_0402_25V4K
1
1
1
PC166
PC163
PC169
PC165
PC167
PC168
PC164
5
6
7
8
2
2
2
@
@ @ @
PR164
255K_0402_1%
4
1 2
PR160
1 2 PR155 PQ151
<30> SYSON BST_1.5V
0_0402_5% 1 2
3
2
1
AO4466L_SO8
0_0603_5%
1
PL152
15
14
PC160 @
1
PU150 PC155 1.8U_D104C-919AS-1R8N_9.5A_30%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1
EN_SKIP
TP
BST
+1.5VP
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
3 12 LX_1.5V
OUT LX
5
6
7
8
1
PR161 PR157
1 2 4 11 1 2 PR156 1
+5VALW VCC
VFB=0.75V
ILIM +5VALW 4.7_1206_5%
100_0603_5% 13K_0402_1% + PC152
5 FB VDD 10
330U_6.3V_M
2
1
PC161 6 9 DL_1.5V 4
PGOOD DL
AGND
PGND
2
4.7U_0603_6.3V6K
2
PQ152
2
1
PC162 PC156
TPS5117_TQFN14_3P5X3P5 4.7U_0805_10V6K AO4712L_SO8 680P_0603_50V7K
3
2
1
2
DIS : UMA : 2
2
Ipeak=16.8A Ipeak=12A
Imax=12A Imax=8.4A
-------------------------------------------------
F=294KHz
PR162
1 2 Total Capacitor 720(uma) 1050(dis)uF,
10K_0402_1%
1
PR163
10K_0402_1%
2
Ipeak=1.65A
ILIM = 4A
F=1MHz
PU180
SY8033BDBC_DFN10_3X3 +3VALW +5VALW
PL182
+1.8VSP
4
3
@ PJ181 1UH_VMPI0703AR-1R0M-Z01_11A_20% 3
10 2 LX_1.8V
PG
+5VALW 2 2 1 1 PVIN LX 1 2
JUMP_43X39 9 3
68P_0402_50V8J
1
PVIN LX PJ1811
1
@ JUMP_43X39
1
1
4.7_1206_5%
1
8
PC187
PC184 SVIN
PR186
22U_0805_6.3VAM PR183
6 FB=0.6Volt 20K_0402_1%
22U_0805_6.3VAM
1
FB
22U_0805_6.3VAM
2
2
1U_0603_10V6K
5 EN
2
PC1811
1
1
NC
NC
TP
2
PC183
PC182
2
FB_1.8V
2
11
2
PR181
680P_0603_50V7K
1 2 EN_1.8V
1
<30,33,40> SUSP# @
1
1
PC186
0_0402_5% @ PC1821
PR184
1
2
2
10K_0402_1%
1
@ PR182 PC185@ 4.7U_0805_25V6-K

2
499K_0402_1% 0.1U_0402_10V7K
2
2
PU1801
6 VCNTL
5 VIN VOUT 3 +1.8VSP
@ PR1811 9 4
VIN VOUT
1
0_0402_5%
0.01U_0402_25V7K
1
SUSP# 1
PC1831
2 8 EN @
PR1821
22U_0805_6.3V6M
7 2
GND
POK FB
1
3K_0402_1%
2
1
PC1841
@ PC1851
2
@APL5930KAI-TRG_SO8 @
2
0.47U_0402_6.3V6K
1
4
@ 4
@ PR1831
2.4K_0402_1%
2
+1.5VP/+1.8VSP
Custom 1.0
PWWHA LA-7202 M/B
A B C D
5 4 3 2 1
HCB2012KF-121T50_0805
D D
PL451
VCCSAP_B+ 1 2
B+
0.1U_0402_25V6
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
10U_1206_25V6M
1
PC467
1
PC463
PC464
PC466
PC468
1U_0805_25V7
PC465
2
5
6
7
8
2
@
1
PR462
2
Ipeak=6A
255K_0402_1%
4
Imax=4.2A
F=276K
<33,40> VCCPPWRGD 1
PR460
2 BST_VCCSAP 1
PR455
2
PQ451
AO4466L_SO8 Toatal Capacitor 660u
3
2
1
0_0402_5% 0_0603_5%
BST_VCCSAP-1
1
@ PC460 PL452
15
14
1
.1U_0402_16V7K PU450 PC455 2.2UH_VMPI0703AR-2R2M-Z01_8A_20%
1 2 1 2 +VCCSAP
BST
EN_SKIP
TP
2
DH_VCCSAP 0.1U_0603_25V7K
2 13
TON DH
1
PR461 VOUT 3 12 LX_VCCSAP PR456 1
OUT LX
5
6
7
8
100_0402_1% PR457
1 2 4 11 1 2 +5VALW 4.7_1206_5% + PC452
+5VALW VCC ILIM
14.3K_0402_1% 330U_2.5V_M
2
FB 5 10 1 2
FB VDD 2
PR471
1
1 2 6 9 PC462 4 PC456
+3VS PGOOD DL
1
AGND
PGND
PC461 10K_0402_1% 4.7U_0805_10V6K
DL_VCCSAP 680P_0603_50V7K PR463
4.7U_0805_10V6K
2
PQ452 0_0402_5%
2
C TPS5117_TQFN14_3P5X3P5 AO4712L_SO8 C
7
3
2
1
2
2
<30> SA_PGOOD
@ PR472
10K_0402_1%
PR464
10_0402_5%
1
2 1 VCCSA_SENSE <9>
1
PR465
680_0402_1%
2
+3VS
1
PR466 PR467
5.1K_0402_1%
1
9.09K_0402_1%
2
2
PR468
10K_0402_1%
PR469
2
1
D 10K_0402_1%
2 1 2
G
S PR473
1
.1U_0402_16V7K
PQ453 C 0_0402_5%
100K_0402_1%
1
@ PR470
2 1 2 VCCSAP_VID1 <9>
PC470
SSM3K7002FU_SC70-3 B
E
3
PQ454
1
B B
MMST3904-7-F_SOT323-3
VID1 +VCCSAP
1 0.8V
0 0.9V
A A

+VCCSAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
PWWHA LA-7202 M/B
5 4 3 2 1
5 4 3 2 1
+1.5V
1
@ PJ75
1
JUMP_43X79
22
D PU75 D
1 VIN VCNTL 6 +3VALW
PC261 2 5
1
4.7U_0805_6.3V6K GND NC
1
3 7 PC264
PR282 PR280 VREF NC
2
0_0402_5% 1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
1 2
<5,9,25,33> SUSP 9
2
TP
G2992F1U_SO8
@ PR279
.1U_0402_16V7K
D +0.75VSP
1
0_0402_5%
SSM3K7002FU_SC70-3
PQ260
PC263
1K_0402_1%
1 2 2
<33> 0.75VR_EN#
1
G
2
S PR281 PC262
3
1
10U_0805_6.3V6M
2
PC260
.1U_0402_16V7K
2
For shortage changed
PL401
CSD17308Q3_SON8-5
HCB4532KF-800T90_1812
C 1.05VS_B+ 1 2 C
B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
10U_1206_25V6M
PC414
PC415
PC413
PR414
5
PQ401
255K_0402_1%
2
1 2
PC416
PR410 2 1 4
0_0402_5% @
<30,33,38> SUSP# 1 2 PR510
2.2_0603_1%
1
PC410 PR405 PC405 PL402
15
14
3
2
1
1
@ PU400 3.3_0603_1% 0.1U_0603_25V7K 1UH_FDUE1040D-1R0M-P3_21.3A_20%

.1U_0402_16V7K BST_1.05VS_VCCP
1 2 1 2 2 1 +1.05VS_VCCPP
EN_SKIP
TP
BST
2
2 13 DH_1.05VS_VCCP
TON DH
1
5
3 12 LX_1.05VS_VCCP PR406
OUT LX PR407 4.7_1206_5% 1
4 VCC ILIM 11 1 2 +5VALW + PC402
1 2
2
VFB=0.75V 11K_0402_1%
0_0402_5%
5 10 1 2 330U_6.3V_M
680P_0603_50V7K
FB VDD
PR420
4 <BOM Structure>
PR411 PC412 2
PC406
6 PGOOD DL 9
AGND
PGND
100_0603_1% 4.7U_0805_10V6K
AON6788_DFN8-5
2
1 2 DL_1.05VS_VCCP
+5VALW
1
PQ402
3
2
1
B TPS5117_TQFN14_3P5X3P5 B
7
8
1
PC411
4.7U_0603_6.3V6K
2
PR415
1 2
<33,39> VCCPPW RGD +3VS
10K_0402_1%
2
@ PR416
10K_0402_1%
1
PR412 PR421
4.02K_0402_1% 10_0402_5%
1 2 2 1 VCCIO_SENSE <8>
1
PR413 Ipeak=12A
10K_0402_1% Imax=8.75A
2
F=305KHz
Total Capacitor 990uF
A A

+1.05VS_VCCP/+0.75VSP
Custom 1.0
PWWHA LA-7202 M/B
5 4 3 2 1
5 4 3 2 1
CPU_B+ 1 2 B+
10U_1206_25V6M
10U_1206_25V6M
1000P_0402_50V7K
8.06K_0402_1%
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL501
PC574
PR530
PC530
PC563
PC564
PC565
PC567
HCB4532KF-800T90_1812
5
PR563 PH501 470KB_0402_5%_ERTJ0EV474J
1
1
1
CSD17308Q3_SON8-5
2 1 2 1 NTCG
3.83K_0402_1%
2
PR564 27.4K_0402_1% @ @
2
PQ501
2
2
1 2
UGATEG 2 1 4
PC556
1
330P_0402_50V7K PR507
330P_0402_50V7K
@ PR531 1 2 2.2_0603_1%
PC557
499K_0402_1% PC531 PL502
VCC_AXG_SENSE <9> +GFX_COREP
3
2
1
1
68P_0402_50V8K 0.36UH_PCMC104T-R36MN1R17_30A_20%
2 1 2 1 2 1 PHASEG 4 1
2 2 1 VSS_AXG_SENSE <9>
PC505
560U_6.3V_M
PC502
D PR532 PC532 0.22U_0603_25V7K 3 2 1 D
10K_0402_1%
PR570
PR571
422_0402_1% 330P_0402_50V7K PC558 BOOTG 2 1 2 1
1_0402_5%
4.7_1206_5%
2 1 2 1 2 1 1000P_0402_50V7K +
PR506
PR505
PC533 PR533 PR534 3.3_0603_1%
150P_0402_50V8J 475K_0402_1% 2.55K_0402_1% 2
0.047U_0603_16V7K
PR567
2
2
24.9K_0402_1%
PR539
PC534
16.5K_0402_1% LGATEG 4
1
1 +1.05VS_VCCPP PH504 10K_0402_1%_ERTJ0EG103FA
680P_0603_50V7K
AON6784_DFN8-5
UGATEG
PHASEG
LGATEG
PQ502
NTCG
1 2 1 2 1 2
BOOTG
ISNG
ISPG
PC506
PR572
1
130_0402_1%
54.9_0402_1%
.1U_0402_16V7K
7.5K_0402_1% PC570
2
3
2
1
2
1
PC560
1 2 .1U_0402_16V7K
2
PR538
PR573
PR537
2
11K_0402_1%
1 1 2 1 2
470P_0402_50V7K
@ PR574
49
48
47
46
45
44
43
42
41
40
39
38
37
2
2
PC571 100_0402_1%
590_0402_1%
PR575
@ PC572
.1U_0402_16V7K
GND
COMPG
FBG
VSENG
RTNG
ISPG
ISNG
NTCG
PROG2
BOOTG
UGG
PHG
LGG
<8> VR_SVID_DAT
1
1 36 BOOT2
<8> VR_SVID_ALRT# VWG BOOT2
2
2 35 UGATE2 1 2
2
<8> VR_SVID_CLK IMONG UG2
3 34 PHASE2 @ PC573
PGOODG PH2 0.01U_0402_16V7K
ISNG
ISPG
SVID_SDA 4 33
SDA VSSP2
1 2 +5VALW
SVID_ALERT# 5 32 LGATE2 PR562 @ PR576 0_0402_5%
ALERT# LG2 0_0603_5%
SVID_SCLK 6 31 VDDP+ 1 2 Connect to +5V can disable GFX portion,
SCLK ISL95831CRZ-T_TQFN48_6X6 VDDP +5VALW CPU_B+
PR540 but PR575 need to be removed.
2.2U_0603_10V6K
<30> VR_ON 1 2 7 30
VR_ON PWM3
CSD17308Q3_SON8-5
1
0_0402_5%
29.4K_0402_1%
0.033U_0603_16V7
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PC554
8 29 LGATE1
PR541 PGOOD LG1
1
C C
PC580
PC581
PC582
+3VS 1 2
1
PR542
PC561
9 28
PQ505
1.91K_0402_1%
2
IMON VSSP1
1
<5,17,30> VGATE 10 27 PHASE1 UGATE2 2 1 4
2
VR_HOT# PH1
2
2
11 26 UGATE1 PR508
NTC
ISEN3/ FB2
UG1 2.2_0603_1%
12 25 BOOT1 PL503
PROG1
ISUMN
ISUMP
3
2
1
VW BOOT1
COMP
ISEN2
ISEN1
VSEN
<30> VR_HOT# 0.36UH_PCMC104T-R36MN1R17_30A_20%
VDD
RTN
VIN
FB
43P_0402_50V8J
PHASE2 4 1
PU500
+CPU_CORE
13
14
15
16
17
18
19
20
21
22
23
24
1
PC537
PR544 PH502 470KB_0402_5%_ERTJ0EV474J PC515 3 2

1 2 1 2 0.22U_0603_25V7K
+1.05VS_VCCPP
680P_0603_50V7K 4.7_1206_5%
BOOT2 2
VDD+
1 2 1
2
3.83K_0402_1%
PR516
1 2 PR515
AON6788_DFN8-5
@ PR543 3.3_0603_1% PR580 PR581
PQ508
499_0402_1% 2 1 PR559 ISEN2 2 1 2 1 ISEN1
1
PR545 1 2
CPU_B+
2
PR560 LGATE2 10K_0402_1% 10K_0402_1%
27.4K_0402_1% 0_0603_5% 4
1.69K_0402_1%
1000P_0402_50V7K
8.06K_0402_1%
For Turbo mode , PH502 must be

1
1
PC516
ISEN2
PR558 PR582
changed 470K (b value = 4700)
2
1
PC539
VSUM+
ISEN1
2 1 2 1
PR546
+5VALW
3
2
1
1U_0603_10V6K
ISEN3
2
1_0603_5% 3.65K_0402_1%
2
PC540 1
PC548
PR583
2
2 1 PC549 VSUM- 2 1
0.22U_0603_25V7K
2
22P_0402_50V8J 1_0402_5%
VSUM+
2.61K_0402_1%
1
PR557
2 1
0.022U_0402_16V7K
PC541
0.22U_0402_10V6K
0.22U_0402_10V6K
B B
@ PR547 10P_0402_50V8J PC542 VSUM- PC562 0.22U_0402_6.3V6K CPU_B+
PR548
1
1
PC559
PC551
PC550
1 2 2 1 2 1 2 1
11K_0402_1%
1 2
1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
499K_0402_1% 2 1
100U_25V_M
499_0402_1%
PC569
100U_25V_M
100U_25V_M
CSD17308Q3_SON8-5
470P_0402_50V7K
PR556
PC583
PC584
PC585
PC568
PC566
PC543 PR549 1 1 1
2
2
330P_0402_50V7K
150P_0402_50V8J 316K_0402_1% PR551 PC544 0.22U_0402_6.3V6K @ PH503
1
10K_0402_1%_ERTJ0EG103FA + + +
2 1 2 1 2 1
PR554
PQ503
3.24K_0603_1% @
2
@ PC555 @ PR550 1.47K_0402_1% UGATE1 2 1 4

2
2
100P_0402_50V8J 2K_0402_1% VSUM- 2 2 2
2 1
PR509
.1U_0402_16V7K
2 1 2 1
PC545 330P_0402_50V7K 2.2_0603_1%
1
1
PC553
Reserve for slow rate 2 1 @PC552

@ PC552 @ PR555 PL504
<8> VCCSENSE
3
2
1
330P_0402_50V7K 100_0402_1% 0.36UH_PCMC104T-R36MN1R17_30A_20%
PC547
PC546 1000P_0402_50V7K 2 1 2 1 PHASE1 4 1

<8> VSSSENSE +CPU_CORE
2
2 1
680P_0603_50V7K 4.7_1206_5%
PC525 3 2
PR526
0.22U_0603_25V7K PR591
AON6788_DFN8-5
BOOT1 2 1 2 1 ISEN1 2 1
PQ504
PR525
3.3_0603_1% 10K_0402_1%
2
LGATE1 4
PR592 PR590
1
PC526
VSUM+ 2 1 2 1 ISEN2
3.65K_0402_1% 10K_0402_1%
3
2
1
2
PR593
VSUM- 2 1
1_0402_5%
A A

CPU_CORE/GFX
Custom 1.0
PWWHA LA-7202 M/B
5 4 3 2 1
5 4 3 2 1
PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------------------------
2010/12/31(PVT) P36 Charger Change PQ203,PQ208 to AO4435L Cost down
2010/12/31(PVT) P36 Charger add PQ207,PQ208,PQ209 10u EMI command

D D
2010/12/31(PVT) P36 Charger add snubber PR206,PC206 EMI command
2010/12/31(PVT) P36 Charger change boost to 2.2 ohm PR205 EMI command
2010/12/31(PVT) P35 +3VALW/+5VALW add snubber PR336,PC336,PR356,PC336 EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP add snubber PR156,PC156 EMI command
2010/12/31(PVT) P37 +1.5VP/+1.8VSP add PC165 for MEI EMI command

2010/12/31(PVT) P37 +VCCSA add snubber PR456,PC456 EMI command
C C
2010/12/31(PVT) P37 +VCCSA change output capacitor PC452 to OS-con cost down
2010/12/31(PVT) P37 +VCCSA change choke PL452 to molding cost down
2010/12/31(PVT) P38 +1.05VS/+0.75 add snubber PC406 PR406 EMI command
2010/12/31(PVT) P38 +1.05VS/+0.75 change 0.75V enable PR279 tp PR282 HW command
2010/12/31(PVT) P39 +CPU_CORE change PC549,PC515,PC525,PC 505 to correct rating design change
2010/12/31(PVT) P39 +CPU_CORE change PL502,PL503,PL504 to DCR 5% design change

B 2010/12/31(PVT) P39 +CPU_CORE change PC568 PC 566 to 5.8mmm capacitor design change B
2010/12/31(PVT) P39 +CPU_CORE change PL551 for load line adjust design change
2010/12/31(PVT) P39 +CPU_CORE change PR560 for program temperture design change
2010/12/31(PVT) P39 +CPU_CORE change PC502,PC531,PC532 for burn-in shun down design change
A A
Title
<Title>

A PWWHA LA-7202P M/B 1.0

5 4 3 2 1
5 4 3 2 1
HW PIR (Product Improve Record)

PWWHA LA-7202P SCHEMATIC CHANGE LIST
REVISION CHANGE: 1.0
GERBER-OUT DATE: 2011/02/18
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1) 01/24 05 modify FAN with BTO item PWM and RPM For HW BTO item
2) 01/24 05 modify RPM FAN connector pin define Request from thermal team
3) 02/14 30 co-lay KB9012 For BTO item
4) 02/15 24 Add C450 For ESD request
D D
C C
B B
A A

HW-PIR
Custom 1.0
PWWHA LA-7202P M/B
5 4 3 2 1
www.s-manuals.com

Pwwha: Delhi 10R

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A B C D E

LA-7202P REV 1.0 Schematic

2011-02-08 Rev 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s

CRT FDI X8 DMI X4

USB/B Left 2IN1 RTS5137 Int. Camera

LPC BUS HD Audio 3.3V 24MHz

Power Circuit DC/DC

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 2A +1.8VS

P-CHANNEL DESIGN CURRENT 1.8A +5VS_ODD

Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

N-CHANNEL DESIGN CURRENT 4A +3VS

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

Ipeak=94A, Imax=52A, Iocp min=122A DESIGN CURRENT 94A +CPU_CORE

Ipeak=17A, Imax=11.9A, Iocp min=19.23A DESIGN CURRENT 15A +1.05VS_VCCP

Ipeak=6A, Imax=4.2A, Iocp min=7A DESIGN CURRENT 6A +VCCSA

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

N-CHANNEL DESIGN CURRENT 2A +1.5VS

DESIGN CURRENT 1A +1.05V

DESIGN CURRENT 1.5A +0.75VS

Security Classification Compal Secret Data Compal Electronics, Inc.

( O MEANS ON X MEANS OFF )

BTO Option Table

PCH SM Bus Address

Power Device HEX Address

+3VS Clock Generator D2 H 1101 0010 b

S4 (Suspend to Disk) LOW LOW HIGH

S5 (Soft OFF) LOW LOW LOW

G3 LOW LOW LOW

Security Classification Compal Secret Data Compal Electronics, Inc.

JTAG & BPM

1A 01/24 pin define change by Thermal

IN 43_0402_1% @ PWM@ D86 C4 C379

Security Classification Compal Secret Data Compal Electronics, Inc.

PEG_ICOMPI and RCOMPO signals should be

PCI EXPRESS* - GRAPHICS

Security Classification Compal Secret Data Compal Electronics, Inc.

AB6 DDRA_CLK0 AE2 DDRB_CLK0

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY A

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @

<16> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

JCPUF POWER +1.05VS_VCCP Decoupling:

VCC18 VCCIO17 22U_0805_6.3V6M 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K 10U_0805_10V6K

VCC97 R102 R105

+GFX_CORE Decoupling: +GFX_CORE

Change C873 from 330uF to 560uF for power issue

Bottom Socket Edge

DDR3 -1.5V RAILS

1.2A Bottom Socket Edge

Security Classification Compal Secret Data Compal Electronics, Inc.

CFG Straps for Processor

Sandy Bridge_rPGA_Rev0p61 @ Sandy Bridge_rPGA_Rev0p61 @ CFG7

1: (Default) PEG Train immediately following xxRESETB

Security Classification Compal Secret Data Compal Electronics, Inc.

5 DQ0 DQ5 6 DDR_A_DQS#[0..7] <7>

DDR_A_D35 143 144