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CD4013BMS FN3080
CMOS Dual ‘D’-Type Flip-Flop Rev 0.00
December 1992
Features Pinout
• High-Voltage Type (20V Rating)
Q1 1 14 VDD
• Set-Reset Capability
Q1 2 13 Q2
• Static Flip-Flop Operation - Retains State Indefinitely
CLOCK 1 3 12 Q2
With Clock Level Either “High” Or “Low”
RESET 1 4 11 CLOCK 2
• Medium-Speed Operation - 16 MHz (typ.) Clock Toggle
Rate at 10V D1 5 10 RESET 2
SET 1 6 9 D2
• Standardized Symmetrical Output Characteristics
VSS 7 8 SET 2
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Functional Diagram
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V VDD
- 2V at VDD = 10V
14
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings 6
SET 1
4
RESET 1
Applications 8
SET 2
• Registers
9 12
D2 Q2
• Counters 11 F/F2 13
CLOCK 2 Q2
• Control Circuits
10
RESET 2
Description
7
CD4013BMS consists of two identical, independent data
type flip-flops. Each flip-flop has independent data, set, VSS
reset, and clock inputs and Q and Q outputs. These devices
can be used for shift register applications, and, by
connecting Q output to the data input, for counter and toggle
applications. The logic level present at the D input is
transferred to the Q output during the positive going
transition of the clock pulse. Setting or resetting is
independent of the clock and is accomplished by a high level
on the set or reset line, respectively.
The CD4013BMS is supplied in these 14 lead outline pack-
ages:
LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 2 A
2 +125oC - 200 A
o
VDD = 18V, VIN = VDD or GND 3 -55 C - 2 A
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
o
VDD = 18V 3 -55 C -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
o
2 +125 C - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
o o o
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25 C, +125 C, -55 C 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
o
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25 C 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
o
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25 C - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10A 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
o o o
Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25 C, +125 C, -55 C 3.5 - V
Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25o o
C, +125 C, -55 Co
- 4 V
VOL < 1.5V
Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being imple- 3. For accuracy, voltage is measured differentially to VDD. Limit is
mented. 0.050V max.
2. Go/No Go test with limits applied to inputs
LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns
Clock to Q, Q TPLH1 oC,
10, 11 +125 -55oC - 405 ns
Propagation Delay oC
TPHL2 VDD = 5V, VIN = VDD or GND 9 +25 - 400 ns
Set to Q, Reset to Q
10, 11 +125oC, -55oC - 540 ns
Propagation Delay TPLH2 VDD = 5V, VIN = VDD or GND 9 +25oC - 300 ns
Set to Q, Reset to Q oC,
10, 11 +125 -55oC - 405 ns
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
Clock to Q, Q TTLH
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input Fre- FCL VDD = 5V, VIN = VDD or GND 9 +25oC 3.5 - MHz
quency oC,
10, 11 +125 -55oC 3.5/1.35 - MHz
NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
LIMITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 1.0 A
+125oC - 30 A
o o
VDD = 10V, VIN = VDD or GND 1, 2 -55 C, +25 C - 2.0 A
+125oC - 60 A
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
oC
-55 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125o C 0.9 - mA
o
-55 C 1.6 - mA
oC
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125 2.4 - mA
-55o C 4.2 - mA
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125 C - -0.36 mA
oC
-55 - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125o C - -1.15 mA
o
-55 C - -1.6 mA
LIMITS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
o
-55 C - -4.2 mA
oC, +125oC,
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25 - - 3 V
55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - +7 - V
55oC
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 A
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage VNTH VDD = 10V, ISS = -10A 1, 4 +25oC - 1 V
Delta
P Threshold Voltage VPTH VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V
LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
P Threshold Voltage VPTH VSS = 0V, IDD = 10A 1, 4 +25oC - 1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record
OSCILLATOR
FUNCTION OPEN GROUND VDD 9V -0.5V 50kHz 25kHz
Static Burn-In 1 1, 2, 12, 13 3-11 14
(Note 1)
Static Burn-In 2 1, 2, 12, 13 7 3-6, 8-11, 14
(Note 1)
Logic Diagram
*4(10)
RESET CL SLAVE SECTION
MASTER SECTION
CL
p
p TG
n
*5(9) TG
n CL
DATA
CL
CL CL p
TG
p n
TG
n CL
CL Q
*6(8) 1(13)
SET
BUFFERED OUTPUTS
CL CL
Q
*3(11) 2(12)
CL
14 VDD
* All inputs are protected by CMOS protection network
7 VSS
TRUTH TABLE
CL* D R S Q Q
0 0 0 0 1
1 0 0 1 0
X 0 0 Q Q No
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
Logic 0 = Low * = Level change
Logic 1 = High X = Don’t care
N(N) = FF1/FF2 terminal assignments
30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5
20 10.0
10V
15 7.5
10V
10 5.0
5 2.5
5V 5V
0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS
-10 -5
-15
-10V -10V
-20 -10
-25
-15V -15V
-30 -15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHAR- FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHAR-
ACTERISTICS ACTERISTICS
250 250
150 150
10V
100 100
10V
15V
15V
50 50
0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD CA- FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD CA-
PACITANCE (CLOCK OR SET TO Q, CLOCK OR RE- PACITANCE (SET TO Q OR RESET TO Q)
SET TO Q)
104 8
AMBIENT TEMPERATURE (TA) = +25oC 6
4
tr, tf = 5ns
DISSIPATION PER DEVICE (PD) (W)
2
(VDD) = 15V
30 103 8
6 10V
4
25
2 10V
20 102
8 5V
6
4
15 CL = 50pF
2 CL = 15pF
10 10 8
6
AMBIENT TEMPERATURE (TA) = +25oC
4
5 INPUT tr = tf = 20ns
2
1
0 5 10 15 20 2 4 6 8 2 4 68 2 4 68 2 4 68 2 4 68
SUPPLY VOLTAGE (VDD) (V) 102 103 104 105 106
INPUT FREQUENCY (ft) (HZ)
FIGURE 8. TYPICAL MAXIMUM CLOCK FREQUENCY vs FIGURE 9. TYPICAL POWER DISSIPATION vs FREQUENCY
SUPPLY VOLTAGE
R
FO
E
IC
FF
O
ES
S AL
L
CA
LO
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T
TAC
N
CO