1.  The gates in this figure are implemented using TTL logic.

If the input of the inverter is open, and

you apply logic pulses to point B, the output of the AND gate will be ________.

A
a steady LOW
.

B
a steady HIGH
.

C
an undefined level
.

D
pulses
.
Answer: Option A
Explanation:
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2.  The gates in this figure are implemented using TTL logic. If the output of the inverter is open,
and you apply logic pulses to point B, the output of the AND gate will be ________.

A
a steady LOW
.

B
a steady HIGH
.

C
an undefined level
.

D
pulses
.
Answer: Option D
Explanation:
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3.  If A is LOW or B is LOW or BOTH are LOW, then X is LOW. If A is HIGH and B is HIGH, then X
is HIGH. These rules specify the operation of a(n) ________.
 A
AND gate
.

B
OR gate
.

C
NAND gate
.

D
XOR gate
.
Answer: Option A
Explanation:
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4.  A major advantage of ECL logic over TTL and CMOS is ________.
A
low power dissipation
.

B
high speed
.

C
both low power dissipation and high speed
.

D
neither low power dissipation nor high speed
.
Answer: Option B
Explanation:
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5.  The output of an XOR gate is HIGH only when ________.

A
both inputs = 0
.

B
both inputs = 1
.

C
the two inputs are unequal
.

D
both inputs are undefined
.
Answer: Option C
Explanation:
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6.  A 2-input gate that can be used to pass a digital waveform unchanged at certain times and
inverted at other times is a(n) ________.
A
AND gate
.

B
OR gate
.

C
NAND gate
.

D
XOR gate
.
Answer: Option D
Explanation:
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7.  The gates in this figure are implemented using TTL logic. If the output of the inverter has an
internal open circuit, what voltage would you expect to measure at the inverter's output?

A
Less than 0.4 V
.

B
1.6 V
.

C
Greater than 2.4 V
.

D
All of the above
.
Answer: Option B
Explanation:
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8.  When does the output of a NAND gate = 1?

A
Whenever a 0 is present at an input
.

B
Only when all inputs = 0
.
 C
Whenever a 1 is present at an input
.

D
Only when all inputs = 1
.
Answer: Option A
Explanation:
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9.  The number of input combinations for a 4-input gate is ________.

A
9
.

B
8
.

C
15
.

D
16
.
Answer: Option D
Explanation:
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10.  When does the output of a NOR gate = 0?

A
Whenever a 0 is present at an input
.

B
Only when all inputs = 0
.

C
Whenever a 1 is present at an input
.

D
Only when all inputs = 1
.
Answer: Option C
Explanation:
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