Output INPUTS

WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 1 1 1 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE

Output INPUTS
WIRE WIRE
I/O VCC 0 0 0 1 I/O VCC 0 1 0 1
PIN 14 13 12 11 10 9 8 PIN 14 13 12 11 10 9

74LS04 74LS08

PIN 1 2 3 4 5 6 7 PIN 1 2 3 4 5 6
I/O 0 1 1 0 1 GND I/O 0 1 0 0 0
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE

WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
1 I/O VCC 0 1 1 1 1 1 I/O VCC 0 1 1
8 PIN 14 13 12 11 10 9 8 PIN 14 13 12 11

74LS32 74LS00

7 PIN 1 2 3 4 5 6 7 PIN 1 2 3 4
GND I/O 0 1 1 1 0 1 GND I/O 0 1 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 0 0
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE

WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE WIRE
0 1 1 I/O VCC 0 1 0 1 1 0 I/O VCC 0
10 9 8 PIN 14 13 12 11 10 9 8 PIN 14 13
1

74LS02

0 0
5 6 7 PIN 1 2 3 4 5 6 7 PIN 1 2
1 0 GND I/O 0 1 0 1 0 0 GND I/O 1 1
WIRE WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE

WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 WIRE
1 1 1 1 0 I/O VCC 0 1 0 0 0 1
12 11 10 9 8 PIN 14 13 12 11 10 9 8
0 0 0 0 0 0 0

74LS32 4077

1 0 1 0 0 0
3 4 5 6 7 PIN 1 2 3 4 5 6 7
0 0 1 1 GND I/O 0 0 1 0 0 1 GND
WIRE
 EXPERIMENT NO 3
Combinational Circuits: Binary Adder and Sub
Learning Objectives:
•To derive the adder and subtrator circuit from tuth table specification
•To use different logic gates in implementing adder and subtractor circuits
•To design an 8-bit adder or subtractor using Logisim Component
Materials
Logisim, Logic Simulator
Gates: NAND, NOR, AND, OR, NOT, XOR, XNOR gates
Input: 1-bit input pin
Output: 1-bit output pin
Procedures:
1 Refer to the video lecture for the discussion of the concept of universal logic gates.
2 Base from the truth table of Half-Adder construct the circuit in using the 3 basic logic gates: AND, OR, IN
Paste the circuit at the space provided

Logisim Circuit for Question no. 2

3 Base from the truth table of Half-Adder , construct the circuit in using XOR
Paste the circuit at the space provided
4 Full-adder Implementation in Logisim using "Analyze Circuit" tool
4.1 Add a sub-circuit and name it Full-Adder. At the Main Menu, click Project, then Add Circuit as sh

4.2 From the main menu, choose Project, then Analyze Circuit from the sub-menu as shown
4.3 From the Combinational Analysis Winow Inputs Tab, add the input literal A as shown.
Then, Click Add

4.4 Add two more inputs, B and Cin

4.5 At the Outputs Tab, Add Cout and S as shown
4.6 At the table Tab, input the truth table of a full adder circuit. Then Click build Circuit
4.7 Paste at the space provided the Boolean Expression, Minimized Equation and the Circuit
5 Repeat Step.4 for Half-Subtracter Circuit with considerations of the inputs. Paste the circuit at the
6 Repeat Step.4 for Full-Subtracter Circuit with considerations of the inputs. Paste the circuit at the

PASTE THE LOGISIM HALF-SUBTARCTOR CIRCUIT HERE

7 Refer to the BB Exam item for the assigned Equation. Paste at the space provided the equation, KM
 Screen Capture your circuit construction and paste link here
Logical Function GIven:  F(W,X,Y,Z) = (1,4,5,7,10,13,14)

K-MAP HERE

WX\YZ OO O1 11 1O
OO 0 1 0 0
O1 1 1 1 0
11 0 1 0 1
1O 0 0 0 1

8 Design a circuit that takes A,B,C as input and performs half adder using gates (REFER TO BB EX
Screen capture the construction of the Half-Adder Circuit with verifying HALF-Adder component
Design a circuit that takes A,B,C as input and performs half adder using XORgXOR andaand basic or and inverter Illustrate the table,

TRUTH TABLE HERE

 9 Given the Truth table, map the POS in the K-Map

OO O1 11 1O
OOO 1 1 1 0
OO1 1 0 0 1
O11 1 0 1 0
O1O 1 0 1 0
11O 1 1 1 0
111 1 0 0 1
1O1 1 0 0 1
1OO 1 0 0 1

10 Refer to the BB Exam item for your assigned Operations. Paste the equation and Logisim circuit
at the space provided below. Design a MUX that will full-add, full-subtract, XOR, divide, OR and AND 4-bit inputs usin

PASTE YOUR CIRCUIT HERE FOR QUESTION NO. 10

11 Paste at the space provided the link of your video capture on the simulation
12 Paste your duscussion in the Discussion Link in BB Exam
13 Paste your conclusion on learning objectives at the CONCLUSION Blog in BB
14 Upload your answered excel file in the BB Exam
 IMENT NO 3
nary Adder and Subtractor Circuits

ic logic gates: AND, OR, INVERTER.

Logisim Circuit for Question no. 3

oject, then Add Circuit as shown in Fig. 2.2

ub-menu as shown
 PASTE YOUR CIRCUIT FOR QUESTION NO. 4.7 HERE

eral A as shown.

Step 4.5

k build Circuit Boolean Expression Cout = ~A ~B Cin + ~A B ~Cin + A ~B ~Cin + A B Cin

ion and the Circuit Minimized Expression Cout = ~A ~B Cin + ~A B ~Cin + A ~B ~Cin + A B Cin
puts. Paste the circuit at the space provided
puts. Paste the circuit at the space provided

PASTE THE LOGISIM FULL-SUBTARCTOR CIRCUIT HERE

ce provided the equation, KMAP and LOGISIM Circuit

 https://drive.google.com/file/d/1t Canonical SOP
Output = ~W ~Y Z + ~W X ~Y + ~W X Z + X ~Y Z + W Y ~Z
LOGISIM CIRCUIT HERE

ng gates (REFER TO BB EXAM ITEM FOR THE REQUIREMENT). Illustrate the table, K-MAP at the space provided
ng HALF-Adder component at the rightmost part of the workspace
sic or and inverter Illustrate the table, K-MAP at the space provided Screen capture the construction of the Half-Adder Circuit with verifying HALF-Adder component at the right

K-MAP HERE

https://drive.google.com/file

LOGISIM CIRCUIT HERE

uation and Logisim circuit
R, divide, OR and AND 4-bit inputs using a 4X1 MUX component.

ESTION NO. 10
https://drive.google.com/file/d/1UEqCrudOOi1DbSWWztW5w15s01uuqplK/view?usp=sharing
Cin + A B Cin S = B Cin + A Cin + A B
Cin + A B Cin S = B Cin + A Cin + A B
 B'C + AD' + C'

OO O1 11 1O
OO 0 1 3 2
O1 4 5 7 6
11 12 13 15 14
1O 8 9 11 10

he space provided

HALF-Adder component at the rightmost part of the workspace

ps://drive.google.com/file/d/1WbkP8FOSGTCMY6Jj14tSSPcxpjBgwNY5/view?usp=sharing
view?usp=sharing