IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India
CMOS-Memristor Inverter Circuit Design and
Analysis Using Cadence Virtuoso
Gaurav Sharma
Ph.D. Scholar, Department of ECE,
Malaviya National Institute of Technology,
Jaipur, India
2015rec9014@mnit.ac.in
Abstract—Memristor is known for its primary fundamental
property called the variation of resistance with memory and
time, thus memristor name combines memory plus resistor.
That’s why the major applications for memristors are
investigated solely in the field of neuromorphic systems and
memory. This paper investigates the benefits of combining
CMOS logic along with memristors. It is because of the way
that this field is currently existing in its initial phases of
exploration, different sorts of models exists in memristor, and
no specific agreement which suggests the best portray of
physical properties. All together further exploration is
regardless until the consideration of hybrid memristor.
memristor is considered for implementation of logic groups
like the memristors as logic inside memory, memristance as
calculation units. The paper incorporates the usage of CMOS-
memristor combination Inverter utilizing Cadence Virtuoso.
Its DC response is registered at different input Voltages and
contrasted with standard CMOS 180 nanometer technology.
Keywords—Memristor, Memristance, Cadence, Circuit
Design, Inverter Circuit, CMOS-Memristor
I. INTRODUCTION
Memristors are defined as a 1fourth class of
fundamental essential electrical circuit component [1],
abutting the most widely recognized resistor R, the capacitor
C, and the inductor L that shows one of their properties
basically at the nanoscale level. Hypothetically, memristive
frameworks or the Memristors , is derived from "memory
resistors", are a kind of essential circuit components that are
passive for keeping the relationship between the voltage v
and the time integrals of current i for two terminal device.
Subsequently, the memristor's state which can also be
termed as resistance, fluctuates according to the
memristance capacity M(q), permitting, through little read
levels, assessment of "history" or past condition voltage or
current [2]. The material execution impacts of IMPLY on
memristor [14] can be controlled by the qualities like,
hysteresis (expanding rate of progress as object state change
starting with one then onto the next) which, as different
other non–linear "abnormalities" in circuit hypothesis,
This work was supported by annual contingency grant from Ministry of
Electronics and Information Technology (Meity), Government of India.
Authors are with Department of Electronics & Communication, Malaviya
[978-1-5090-2807-8/16/$31.00
National Institute of Technology, Jaipur ©2016 India] (email:
302017,IEEE
2015rec9014@mnit.ac.in)
Lava Bhargava
Associate Professor, Department of ECE,
Malaviya National Institute of Technology,
Jaipur, India
lavab@mnit.ac.in
should be less abnormality than a fundamental property of
passive circuits [2]. Presently, Researcher Stanley Williams
is leading a group at HP Labs [3] which has developed the
first steady, stable and pragmatic model, the name
memristance assigned as a property of a known material was
almost non-existent or not referred to as normal as appeared
in Fig. 1 and its attributes are given in Fig.2. The electronics
and other field impacts always predominates the impact of
memristor at non–nanoscale separations, until the nanometer
technology becomes popular in scaling and material
fabrications [5]. These said properties at the nanoscale level
have been seen in real life before the improvement of HP
Labs models [6, 7, 8, 9].
The Memristor is introduced as a late found
detached circuit component. It was initially anticipated by
Leon Chua in 1971 [1], and was created by HP labs in 2008
[2]. This component was anticipated as a supplement of 3
previous circuit components (resistor, capacitor and
inductor) see Fig. 1. It can be seen that the memristance M,
which is the fundamental property of memristors, ties the
flux and charge by following relationship [10, 11, 12, 13]
df  Mdq (1)
Dividing (1) by dq yields the memristance
df
M (q)  (2)
dq
And by dt yields
V  M ( q) I (3)
The above conditions demonstrate that memristors
are resistive components in reality, with the property of
varying resistance called memristance, this fluctuating
resistance is a function of the current (or charge) which
went through the component. So the resistor along with
memory derives the memristor. Memristor as a new
component is exceptionally alluring for substitution of
memory cells. Memristor is non-volatile, so it devours no
static power, and decreases die area [14]. Memristors can
deliver stack over the CMOS layer, since they are framed
between two neighboring metal layers. Specified qualities of
 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India

memristor utilizes it as logical components. Like a memory thick dark line increases the memristance [11, 3, 4, 6]. Most
logic or as a CMOS logic (for parallel processing along with models incorporate a current limit, underneath which there
reduction of die area). This work narrates the test of is no adjustment in memristance (or a little change). So the
actualizing logics with memristors using CMOS inverter to voltage threshold (dependent on memristance) is substituted
verify that the NOT gate can work with voltage of up to 6V, in place of this current threshold when memristor acts as a
and possibly 7V with more than 2 buffers but will cause a circuit element [2].
failure at 8V [3, 6, 7, 9, 13].
II. LINEAR ION DRIFT MEMRISTOR
The principal pragmatic Titanium Dioxide
memristor was created by HP Labs is essentially in light of
a two-layer meager "stacked layers" of titanium dioxide
films, along with symmetrical lattices of oxygen and
titanium atoms. (The resistance of Titanium dioxide TiO2
changes in addition of oxygen atoms, that is the reason it is
utilized widely as a part of oxygen sensors) The random
movement of these atoms in this thin film are controlled by
the movement of electrons in that material, which permits a
change of state in the nuclear structure of the device or
memristor particularly. The base layer behaves like an
insulating material, and conduction is done by film layer at
the top due to extra oxygen vacancies in the TiO2 material.
The oxygen vacancies move towards the base of the layer, it
changes the resistance or the state, accordingly top layer Fig. 1. Relations of circuit elements R, L, C with Memristance M
keeps up a steady state in the top layer. To get to the
memristive properties, crossbars made of nanowires are
composed above and beneath of the top and base layers of
material, for exchanging of thoroughly [4, 9, 11, 12, 14].

III. MODELING OF MEMRISTOR

A. Titanium dioxide Model
The very first model of memristor was created by
Hewlett-Packard Labs. The model was exceptionally
oversimplified model, accepting “One” state variable. The
expectation from this model dignifies the movement of
charged particles in effect of vast field, conductance of the
media changes in concern with this development. This is
displayed by a component which is made out of 2 resistors Fig. 2. Linear Ion Drift Titanium dioxide based Memristor model
arrangement (RON, ROFF where, RON < ROFF). W is the state
variable which elaborates about the relative doped or A. Parameters Chosen
undoped part of every resistor (see Fig. 2.). Doped area is For the purpose of comparison between different
oxygen deficient TiO2 x acts as RON and Undoped is TiO2 memristor types, 5 classes of memristors were chosen and
behaves as ROFF, Both variable portions are sliced between parameterized according to the TEAM model. The
two Platinum electrode plates. parameters were chosen to achieve the following types of
memristors: linear memristor without current threshold,
linear memristor with current threshold, 3 types of nonlinear
V(t) =( RON [ W (t ) ] + ROFF [1 - W (t ) ]) i(t) (4) memristors with current threshold of 3, 5 and 10.
D D
Additional considerations in choosing parameters
W(t) = μv [ RON / D ] i(t) (5) were reasonable working levels on voltage, full swing of the
memristance in the given voltage, and reasonable switch
time (All the models where chosen to be symmetric between
IV. MEMRISTOR AS A CIRCUIT ELEMENT
ON and OFF switching).
At the point when current streams into the thick
dark line as shown in the above Fig. 1, the memristance
diminishes. At the point when current streams out of the
 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India

V. INVERTER DESIGN by the fact that in this circuit, the output of one gate is
connected to the input of another. This causes some of the
current that flows through an input node to exit the gate
from the output node instead of the other input. It is because
not all the current flows through one of the memristors a full
switching might not occur (due to the existence of a
threshold) and the output voltage is not always close to one
of the edges.

For this reason, memristors with lower threshold

voltages shown in Fig. 4,5,6,7 are less sensitive to the issue
and give improved results compared to memristors with
high thresholds in fig. 8, 9, this is the main reason why the
response of all three states is much more accurate in Fig.
4,5,6,7 as compared to Fig. 8, 9 The effect is highly
dependent on the structure of the circuit. Furthermore, for
different starting states of the memristors, different results
can be measured for the same input. Because of these
reasons it is very difficult to model the effect and solve it. A
very straightforward approach is to buffer every two gates
with a CMOS element (a buffer or an inverter), thus solving
the problem by elimination of current that flows through the
output node (because the gate of a transistor does not allow
Fig. 3. Inverter Design the flow of current). The integration of CMOS gates and
memristors forces usage of voltages that are suitable for the
CMOS – Memristor inverter functions with one process used in order to prevent breaches and other harmful
PMOS and two memristors (C1 and C2) in place of NMOS effects like 3V to 6V shown in Fig. 4,5,6,7. Moreover, the
having low threshold voltage to increase switching speed as connection between the CMOS level (silicon) and the
show in Fig. 3. The inverter is implemented using a 0.18 um memristor level (metals) presumably requires the use of area
process along with the dimensions of transistors as consuming VIAs. To reduce this, the number of buffers used
memristor, memristor film length is 10nm, with RON, ROFF is reduced to the minimum necessary to keep the correct
as 10kΩ and 1MΩ respectively, Wp=1.8 um, L=0.18 um. logic behavior of the circuit.
Memristor is for current feedback and memristor controls
the current passing through PMOS. Both are connected to
output through their positive terminals. ON and OFF
scheduling of PMOS switch is done by input Voltage Vin
due to constant Vdd. If input voltage Vi is set to 0 then
PMOS, C1 and C2 will be in ON state due to current passing
through memristor with RON activation, Other case
elaborates the cutoff of PMOS when source to gate voltage
becomes less than the threshold voltage of PMOS as a
consequence memristor C1 turns OFF and C2 remains in the
old state i.e. ON state. The behavior of gate voltage is
shown at different voltages. The following graphs in Fig.
4,5,6,7,8,9 shows the output of a memristor-CMOS inverter,
a buffer of two inverters in a row, and two inverter serial
buffer. It can be concluded that the hybrid NOT gate can
work good up to 6V and also at 7V to some extent with
more than 2 buffers. A supply voltage of 8V causes failure.
A very important problem of this logic family is
Fig. 4. DC Response for 3V
demonstrated in Fig. 9. In addition to the erosion of the
output voltage caused by the existence of a voltage divider
(expected to be 1%).
VI. RESULTS AND DISCUSSION
Analysis of graphs in the figures below states the
significant differences between the output voltages and the
supply voltages after settling. This difference is explained
IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India

Fig. 5. DC Response for 4V

Fig. 8. DC Response for 7V

Fig. 6. DC Response for 5V

Fig. 9. DC Response for 8V

VII. CONCLUSIONS
We have implemented CMOS logic based
memristor inverter circuit and analyzed its DC response in
Cadence Virtuoso. It can be concluded that with the help of
buffers, the response can be corrected and the circuit and
handle voltage till 7 V. After increasing till 8 V or above,
there is a breakdown and the response is not correct. This
proves the logic that memristors having lower threshold
voltages are less sensitive and shows improved output as
compared to memristors having higher threshold voltages.
The combination of CMOS gates and memristors includes
only usable voltages for the circuit to prevent breaches and
other distortion effects.

Fig. 7. DC Response for 6V

 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India

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