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    Ritvik
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    This document contains a Verilog module design for a task2 module that performs logic operations on inputs a, b, c, and d. The module assigns the inputs to internal variables, performs logic operations to calculate intermediate variables d1, d2, and d3, and uses a mux to assign the output out based on the values of d0, d1, d2, and d3. The document includes the module declaration, input/output declarations, assignments of inputs to internal variables, logic operations to calculate d1, d2, and d3, and the mux logic to assign the output out.

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    digital logic design da 1

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    This document contains a Verilog module design for a task2 module that performs logic operations on inputs a, b, c, and d. The module assigns the inputs to internal variables, performs logic operations to calculate intermediate variables d1, d2, and d3, and uses a mux to assign the output out based on the values of d0, d1, d2, and d3. The document includes the module declaration, input/output declarations, assignments of inputs to internal variables, logic operations to calculate d1, d2, and d3, and the mux logic to assign the output out.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    5 views4 pages

    Scan Sep 02, 2020

    Uploaded by

    Ritvik
    This document contains a Verilog module design for a task2 module that performs logic operations on inputs a, b, c, and d. The module assigns the inputs to internal variables, performs logic operations to calculate intermediate variables d1, d2, and d3, and uses a mux to assign the output out based on the values of d0, d1, d2, and d3. The document includes the module declaration, input/output declarations, assignments of inputs to internal variables, logic operations to calculate d1, d2, and d3, and the mux logic to assign the output out.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    1/3ELOT)

    IASY 2
    Rtk Poshan

    FM (O 21ViSIT,, 1 t2

    c a dakoul ne
    A Onol
    Do D
    B+D Bt 40 40
    AAL

    AtT

    AAC 13

    /1o /ruO
    Do-(A+C) CAA)
    (A + C )
    A
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    (A tcT
    A

    D2 (A+t)

    (AR +c) =>


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    (A +T)
    -CA+CT).(A4T)
    A (A+) =) A A+A= A
    (Oolt
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    Unput a by tyd, do, d \,oln,ol3

    OuutPut ouk
    ww out
    auugn d0ra
    aRugn oldnCa)

    aRng d e -
    ausgn d3= utd1le);

    Out= b?ld
    =D d?:d:? :(dRl:do)
    atan

    el uoolul
    Design unit vName Value Kind Ln iow
    module task2 (a,b, c, d, out,do, dl, d2,d3)
    ww mut a.b,C,d, d0, dl , d2,d3:
    ASSGNS
    output out
    wire ouc:
    FASCICMeS ass1gn a a
    ass1gn di (a)
    ASSlaN
    vm_capeaty= t0 Net
    assign d s ( a c )
    assign out-b? (d?d3:d2) : (d?dl:d0):
    S Net
    Out encdmioa
    dule

    Lbrary Project sim Wave task 2v mux2.v


    Transcipt
    torce -freeze sim:/task2/d 0 0, 50 p3)E 200
    SIM 23> Iun

    nirt:dd sim
    task2
    Latk2/a
    #ASSIGN
    AGST
    ak2/b

    ask Sto
    e
    task2/d
    task2/d0
    NCt
    taskej01
    vsim_capaaty Net
    TNet as/2
    Out Net
    /task2/a5
    task2/out Stu

    Now

    Cursor1

    brary ront mb JWave task 2 ma2v


    sin:/task2/d 0 0, 100
    rce-freeze
    M 23> Tun
    150 ps)
    M 24

    to Now: 80U ps De

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