Mindanao State University- Iligan Institute of Technology

College of Engineering and Technology

Department of Electrical, Electronics and Computer Engineering

Two-Stage
Operational
Amplifier
In partial fulfillment of the course requirements in
ECE 126 A8 (Introduction to Analog Circuits Design)

Submitted by:
Marven A. Yuson
(ID no. 2014-1430)

Submitted to:
Prof. Olga Joy L. Gerasta
 HAND CALCULATION IMPLEMENTED VALUES

DEVICE W/L DEVICE W/L

Mn1 4 Mn1 22
Mn2 4 Mn2 22
Mp3 21 Mp3 20
Mp4 21 Mp4 20
Mp5 24 Mp5 24
Mp6 128 Mp6 132
Mn7 70 Mn7 70
Mp8 34 Mp8 15
Mn10 10 Mn10 10
CC 3.3pF CC 2.61pF
IREF 14.30uA IREF 14.30uA

TWO STAGE OP AMP SCHEMATIC

OPERATING POINT:

LOW FREQUENCY GAIN 50dB

UNITY-GAIN FREQUENCY 10M HZ

SLEW RATE 10 V/uS

CMRR 50dB

PHASE MARGIN 60

EXPECTED SPECIFICATION
  GAIN, UNITY GAIN FREQUENCY & PHASE MARGIN

SIMULATION RESULTS:

Figure 1: OPEN LOOP GAIN

 Figure 2: PHASE MARGIN & GAIN BAND WIDTH

 COMMON MODE REJECTION RATIO (CMRR)

Figure 3: CMRR
SIMULATION RESULTS:

Figure 4: Slew rate & settling time

 Slew Rate and Settling Time

SIMULATION RESULTS:

Figure 5: ICMR

 INPUT COMMON MODE RANGE (ICMR)

SIMULATION RESULTS:

 PSRR
SIMULATION RESULTS:

Figure 6: PSSR+

Figure 7: PSSR-
 Output Voltage Swing

SIMULATION RESULTS:

Figure 8: OUTPUT VOLTAGE SWING

Figure 9: OUTPUT VOLTAGE SWING TRANSIENT RESPONSE