The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors

to perform timing and counting functions using three 16-bit registers. Each counter has 2 input
pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded
in its register. On command, it begins to decrement the count until it reaches 0, then it generates
a pulse that can be used to interrupt the CPU.

Differences between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter cannot be Reads and writes of the same counter can be
interleaved. interleaved.

8254 Architecture

The architecture of 8254 looks as follows −

Features of 8253 / 54
 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10 MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.
 8254 has a powerful command called READ BACK command, which allows the user to
check the count value, the programmed mode, the current mode, and the status of the
counter.

8254 Pin Description

Here is the pin diagram of 8254 −

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal -
OUT.

Data Bus Buffer

It is a tristate, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system
data bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.
Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode,
the RD and WR signals are connected to IOR and IOW, respectively. In the memory mapped I/O
mode, these are connected to MEMR and MEMW.
Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is
tied to a decoded address. The control word register and counters are selected according to the
signals on lines A0 & A1.

A1 A0 Result

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to either write a command
word, which specifies the counter to be used, its mode, and a read or write operation. Following
table shows the result for various control inputs.

A1 A0 RD WR CS Result

0 0 1 0 0 Write Counter 0

0 1 1 0 0 Write Counter 1

1 0 1 0 0 Write Counter 2

1 1 1 0 0 Write Control Word

0 0 0 1 0 Read Counter 0

0 1 0 1 0 Read Counter 1

1 0 0 1 0 Read Counter 2
 1 1 0 1 0 No operation

X X 1 1 0 No operation

X X X X 1 No operation

Counters

Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or
BCD. Its input and output is configured by the selection of modes stored in the control word
register. The programmer can read the contents of any of the three counters without disturbing
the actual count in process.

Operational modes
The D3, D2, and D1 bits of the control word set the operating mode of the timer. There are 6 modes
in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for
modes 2 and 3.
All modes are sensitive to the GATE input, with GATE high causing normal operation, but the
effects of GATE low depend on the mode:
 Modes 0 and 4: Counting is suspended while GATE is low, and resumed while GATE is high.
 Modes 1 and 5: The rising edge of GATE starts counting. GATE may go low without affecting
counting, but another rising edge will restart the count from the beginning.
 Modes 2 and 3: GATE low forces OUT high immediately (without waiting for a clock pulse)
and resets the counter (on the next clock falling edge). When GATE goes high again, counting
restarts from the beginning.

Mode 0 (000): Interrupt on terminal count

Mode 0 is used for the generation of accurate time delay under software control. In this mode, the
counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate
is equal to the input clock frequency.
The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after
the COUNT is programmed. OUT remains low until the counter reaches 0, at which point OUT
will be set high until the counter is reloaded or the Control Word is written. The counter wraps
around to 0xFFFF internally and continues counting, but the OUT pin never changes again. The
Gate signal should remain active high for normal counting. If Gate goes low, counting is
suspended, and resumes when it goes high again.
The first byte of the new count when loaded in the count register, stops the previous count.
Mode 1 (001): programmable one shot
In this mode 8253 can be used as a Mono-stable multi-vibrator. GATE input is used as trigger
input.
OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the
one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.

Mode 2 (X10): rate generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-
time clock interrupt.
Like other modes, the counting process will start the next clock cycle after COUNT is sent. OUT
will then remain high until the counter reaches 1, and will go low for one clock pulse. The
following cycle, the count is reloaded, OUT goes high again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is
calculated using the following formula:
∫ 𝑖𝑛𝑝𝑢𝑡
Value to be loaded into counter =
∫ 𝑜𝑢𝑡𝑝𝑢𝑡
Note that the values in the COUNT register range from 𝑛 to 1; the register never reaches zero.

Mode 3 (X11): square wave generator

This mode is similar to mode 2. However, the duration of the high and low clock pulses of the
output will be different from mode 2.
Suppose 𝑛 is the number loaded into the counter (the COUNT message), the output will be high
𝑛 𝑛
for ⌈ 2⌉ counts, and low for ⌊ 2⌋ counts. Thus, the period will be counts, and if is odd, the extra
half-cycle is spent with OUT high.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter reaches
zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output
will become high again.
GATE low suspends the count, which resumes when GATE goes high again.

Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
After receiving the Control Word and COUNT, the output will be set high. Once the device detects
a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will
go low for one clock cycle – after that it will become high again, to repeat the cycle on the next
rising edge of GATE.