NEW

TECHNOLOGY

COLOR TELEVISION SYSTEM

DX4P CHASSIS
DX4P TG
Central Processing Unit

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Figure 1. Central Processing Unit Block Diagram
 Signal Processing

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Figure 2. Signal Processing Block diagram

DX4P TG
Y/C Separator
The Importance of a Comb Filter
The luminance and chroma information are mixed in
the composite TV signal and must be separated so the
TV can properly use each portion. A color TV that does
not have a comb filter can separate the luminance from
the chroma by using a bandpass filter. However, a
Figure 3. Y/C Separation Block Diagram
The Y/C separator uses the configuration shown in
Fig. 3. After a non delayed signal, a 1H delayed signal,
and a 2H delayed signal pass through band pass filter
BPF1, they enter a 3 line comb filter. The 3 line comb
filter outputs a C signal called 3 line C. The output
signal of the dot canceller switches BPF-C which is the
C signal output from 3 line C and BPF-1 and outputs a
Y signal.
DX4P TG -3-
bandpass filter limits the amount of usable luminance
information and lowers the picture resolution.
A comb filter separates the luminance and chroma in a
different, more selective method which allows the TV to
use more of the luminance and maintain more detail.
The diagonal resolution improvement circuit improves
the diagonal resolution of the Y signal. Meanwhile, 3
line C passes through the cross color canceller and is
output as a C signal.
The C signal BPF and Y signal notch filter
characteristics can be switched between narrow band
and broad band. Both become broad band using 0 and
narrow band using 1.
 RGB Signal Processing

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Figure 4. RGB Signal Flow Block diagram

DX4P TG
RGB signal processing
White Character Correction Circuit
White character correction expresses clear white
characters by increasing the B-Y signal level of areas
where there is no color and the brightness level is high,
and converting to a whiter telop character.
Black Level Correction Circuit
The black level correction circuit detects the blackest
area (minimum value) in a screen, and when the
blackest area is above the pedestal level, the circuit
does expansion correction of the gradation area under
the black level correction start point in the black
direction so that the blackest area is at the pedestal
level.
Dynamic Gamma Correction Circuit
The dynamic gamma correction circuit detects the
whitest area in a screen after gamma correction, and
when the whitest area is greater than the blooming
level set, the circuit operates so that the whitest area
matches the blooming level.
R-Y Demodulation Axis Control Circuit
R-Y demodulation axis control is a function to control
the color reproducibility to its optimal level to match the
light emitting characteristics of the display device.
Control is done by turning the R-Y axis with the angle
of the B-Y signal fixed.
B-Y Demodulation Gain Control Circuit
B-Y demodulation axis control is also a function to
control the color reproducibility to its optimal level to
match the light emitting characteristics of the display
device. Control is done by changing the B-Y signal gain
from 0 to 2x with the R-Y signal gain fixed.
RGB Conversion Matrix Circuit
For all functions processed by a YUV signal, all signals
for which all processes have ended are converted to an
RGB signal, and ultimately are made into signals for
driving a CRT.
The conversion formula for this is as follows. For
NTSC, PAL SECAM, 525P, and 480P formats, RGB
signals are converted based on:
B = Y + Pb / 0.564
R = Y + Pr / 0.713
G = (Y - 0.114B - 0.299 R) / 0.587
RGB Matrix Processing
DX4P TG
OSD Insertion Circuit
1. Input signal
Color is displayed using three signals, 4 bit, R,G
and B. 4096 colors can be displayed. The OSD
signal can be inserted at a synthesis ratio with any
video signal according to the a blending signal (4
bits) from the microcontroller. The video signal is
output when the a blending signals are all low.
2. Contrast and brightness linking
The OSD contrast and brightness control is linked
to the contrast and brightness control of the main
video signal.
Brightness Control Circuit
Brightness control is a function that controls the offset
level of a signal. As data processing for this LSI, the
pedestal level of the Y image quality correction circuit
done with a YUV signal is set adding or subtracting the
offset control value of the Y signal.
Blanking Signal Generating Circuit
The blanking signal generating circuit and blanking
signal insertion circuit perform super blanking
processes on output RGB signals. Super blanking
makes the retrace line invisible even if the brightness
control is raised to the maximum by lowering the video
signal to a level of the pedestal level or lower during the
horizontal and vertical blanking period when driving a
video display device.
Drive and Cutoff Control Circuit
The drive control circuit has 12 bit drive control value
for each RGB, and 12-bit video signals undergo
amplitude control as is and are output as 12 bits.
The cutoff control circuit controls cutoff by adding and
subtracting 12-bit cutoff control data to a 12 bit video
signal.
VM Drive Signal Generator Circuit
VM (Velocity Modulation) signals clearly represent the
contours of a video image by changing the electron
beam speed in the contour areas. VM signals are
generated from a brightness signal with the edge
corrected by the horizontal contour correction circuit
standing. A VM signal is a brightness signal that has
undergone primary differentiation, but noise is not
highlighted, so coring processing and a limiter process
for controlling the effect are required.
Video image
brightness signal
VM Signal VM noise level control
VM Signal Generation
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ABL Voltage Control
The ABL voltage (beam current volume) undergoes A/D conversion and the following controls are performed.

1. DC transit level correction: This raises the
brightness level according to the increase in beam
current volume to prevent black fill in.
2. ACL control: When the beam current volume is
high because the FBT load is not raised a certain
degree according to the beam current level, this
performs control so that the total load is fixed by
lowering the contrast using feedback control.
3. White character correction ABL control: When the
beam current volume is high, this automatically
eliminates the white character correction effect and
prevents side effects.
4. Black level correction ABL control: When the beam
current volume is high, this increases the black
level correction effect and prevents black fading.
When the beam current volume is low, this lowers
the black level correction effect and prevents black
fill in. The Fig. 5 is a block diagram of ABL voltage
control.

Figure 5. ABL Voltage Control

ABL voltage

Voltage High

Voltage Low

0% 50% 100%

Input signal APL (%)

Figure 6. ABL Voltage Change Characteristics

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MPU Pin Location

Figure 7. MPU Pin Location

Note: Due to slight software upgrades, two different part numbers can be found on
the DX4P family for the IC4002, MN102H75KTF and MN102H75KTL.

DX4P TG -7-
MPU Pin Description Table
PIN NUMBER TYPE CONTROL FUNCTION DESCRIPTION
2 INPUT /VSYNC Main Picture Vertical Synchrony
5 INPUT /RST Reset
7 INPUT /TEST Test Pin
12 INPUT /HSYNC Main Picture Horizontal Sync
20 INPUT VCOI Internal VCO input (external LPF input)
28 INPUT VREF DAC Reference Voltage Connection
30 INPUT IREF Resistance connecion for DAC bias current setting
31 INPUT COMP DAC phase compensator connection
33 INPUT CLL Clamp Level Low Input
34 INPUT VREFLS CCd reference voltage input
35 INPUT CVBS1 Composite video signal input 1
38 INPUT CVBS0 Composite video signal input 2
39 INPUT VREFHS CCd reference voltage input
40 INPUT CLH Clamp Level High Input
56 INPUT HHS_DET HHS Level Detector
57 INPUT SOS Voltage from each protector circuit
61 INPUT AFC2 Automatic Frequency Control from Tuner 2
62 INPUT ACL1
64 INPUT ACL2
65 INPUT AFC1 Automatic Frequency Control from Tuner 1
66 INPUT KEYSCAN2 Key Scanning (action,shutdown)
67 INPUT KEYSCAN1 Key Scanning (power,ch,vol.)
68 INPUT WP
69 INPUT SOS_2 Voltage from each protector circuit
72 INPUT RMIN Remote Control Input
76 INPUT OSC1 Clock Pulse Signal
79 INPUT FA PORT Service Mode Input
PIN NUMBER TYPE CONTROL FUNCTION DESCRIPTION
1 OUTPUT MOMENT_B_DOWN Momentary Power Down
6 OUTPUT HFR Horizontal Freq.Reference
8 OUTPUT YS Video Signal Out
10 OUTPUT SYSCLK System Clock Output
15 OUTPUT VIDEO-MUTE Video Mute
17 OUTPUT WP
21 OUTPUT PDO Internal phase compare output (external LPF out).
23 OUTPUT YM
24 OUTPUT OSD_B Blue OSD
25 OUTPUT AUDIO-MUTE Audio Mute
26 OUTPUT OSD_G Green OSD
27 OUTPUT OSD_R Red OSD
29 OUTPUT LED SOS Led signal
42 OUTPUT HD/SD SW 1080i/480p switch
43 OUTPUT SERVICE SW Service Switch
44 OUTPUT AUDIO MUTE Mutes audio whe amp is used
45 OUTPUT AC_SW A.C. switch
46 OUTPUT SBD1 Serial interface
47 OUTPUT SBT1 Serial clock signal
48 OUTPUT ROTATION Landing Corr.Circuit
49 OUTPUT H_POSITION H-Raster position circuit
50 OUTPUT V_POSITION V-Center circuit
51 OUTPUT MOIRE_GAIN Tilt Correction circuit
52 OUTPUT HHS_REF HHS circuit
55 OUTPUT DEG_SW Activates Degauss relay
60 OUTPUT HDMIINT High Definition Miltimedia Interface
70 OUTPUT SCL1 I2C Bus Serial Clock 1
73 OUTPUT LPF_SEL Low Pass Filter Selector

-8- DX4P TG
 FUNCTIONAL
BLOCK DIAGRAMS

COLOR TELEVISION SYSTEM

DX4P CHASSIS
Boards Connections

DX4P TG - 11 -
- 12 - DX4P TG
DX4P TG - 13 -
- 14 - DX4P TG
Inter-Integrated Circuit Bus (I2C Bus)
DX4P incorporates an inter-integrated circuit (I2C) bus.
The I2C Bus is a double polarity bus that uses two
lines, the Serial Data (SDA) line and Serial Clock (SCL)
line, to carry information between devices connected to
the bus. Each device connected to the bus has a
unique address for data transfer called the slave
address.
MPU uses 8MHz oscillator, SCL frequency is 100KHz.
The devices on the bus are thus either a “master” or a
“slave” when data is transmitted or received. In this TV,
the “Master” device is the IC4002 microprocessor unit,
which initiates a data transfer on the bus line and
DX4P TG - 15 -
generates the clock signal which permits the data to be
sent. The “Slave” devices (i.e. EEPROM memory, tuner
etc.) are addressed by the MPU, receive the
transmitted data, and return an acknowledgment to the
MPU.
The I2C Bus system performs control functions which
replace many of the mechanical controls needed in a
television receiver. Instead of adjusting many individual
mechanical controls, electronic control functions can
be performed using the “on screen display menu” in
service mode.
Tuning and VIF

Figure 11. Tuner Block Diagram.

Tuner VIF Circuit

The tuner uses a voltage-variable capacitor (varactor), a The Video Intermediate Frequency (VIF) circuit is the
frequency synthesizer and a phase locked loop (PLL) second stage of the Intermediate Frequency (IF)
system to tune the local oscillator (LO) to the desired processing. The VIF circuit amplifies, detects and
channel frequency by digital control (see Fig. 11). separates the video signal from the other components in
the channel frequency band.
The LO frequency is divided by a programmable divider
to produce a frequency whose phase is compared to the
reference frequency generated by the 4MHz oscillator. General description
The BT (tuner) voltage is controlled by the output The IF signal has four components:
voltage of the phase comparison, which controls the LO • Luminance (Y)
frequency. The LO frequency varies according to the
• Color difference (C)
divided ratio of the frequency divider.
• Horizontal and vertical sync
The tuning MPU sends the divided ratio of the frequency • Composite audio
divider and the band switch data to the tuner.
The VIF signal is amplified about 50 dB before it is sent
to the video detector. The video detector uses the PLL
synchronous detection system to ensure a high fidelity
video signal.

- 16 - DX4P TG
VCO and APC
When the power is turned on, the VCO starts oscillating
at 45.75MHz via the tank circuit.
VCO
The APC circuit compares the VIF signal with the VCO Control VCO
signal. If the frequencies do not match, the VCO
frequency is modulated to synchronize with the VIF
PLL
Video
AMP Detector
incoming IF (see Fig. 12 and Fig. 13).
An R/C network predetermines the response Phase
Comparator
characteristics of the APC circuit. The smaller the time
constant of the R/C network, the faster the response.
Figure 13. PLL Video Detection
VIF
SC (color sub-carrier) (video intermediate
frequency) The rise-up point is determined in 64 steps by the MPU
IC4002 via the I2C bus. This adjustment can be made
via remote control in service mode.
SIF
(sound intermediate
frequency) Automatic Frequency Control (AFC)
Adjacent
sound
Adjacent The IF is set at 45.75MHz and the VCO center voltage
picture
is 2.5V.
f If the VIF fluctuates 500 kHz (leading in width), the
AFC voltage is about 3.7V.
Figure 12. Broadcast channel frequencies
The AFC voltage from the tuner is sent to MPU IC4002
pin 53.
IF and RF AGC MPU IC4002 monitors the AFC voltage and alters the
Detected video signal is applied to the IF AGC circuit. channel data to keep the video signal within the band
of the VIF circuit.
The IF AGC generates the AGC voltage according to
the amplitude of the synchronizing video signal. The
SIF
circuit can change the gain about 40 dB to keep the
amplitude of the video output signal constant. The IF passes through the video amp and the SIF filter
in the tuner, where its output (audio out) is passed to
RF AGC works as delayed AGC. To adjust gain, first
pin 14 of IC2201.
adjust IF gain, then RF gain.

DX4P TG - 17 -
MPU Control

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Power Supply
DX4P power supply operation is common to other
Panasonic families.
AC voltage supply is controlled by MPU via RL801, if
high level is present at Q802-Base, the relay will be
closed, turning ON the set. Rectified voltage from the
main input the B+ voltage transformer T801 and the
voltage controlled oscillator (IC801). This transformer
will provide AC voltage for the various power lines.

Figure 14. Main Voltage Flow Diagram

DX4P TG - 19 -
AUDIO
Audio processing is performed in A-Board. Audio
signal from main tuner TNR001 (mixed channels) input
the MTS (Multiplex Television Sound Decoder) IC2201,
signal is separated in left and right channels, these
signals input the A/V switch IC3003. Left and right
channels from A/V jacks and component audio jacks
Among DX4P main audio features and characteristics are:
• MTS -Multiplex Television Sound, allow separation
for stereo, left and right channels from input signal.
(IC2201)
• SAP Decoder -Second Audio Program, detects,
decode and allow to reproduce second audio
signal from broadcasters. (IC2201)
• Tone Control -Allow to change the Bass and Treble
levels to the output signal. (IC2451)
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are also input to this selector. Selected channels input
to the sound processor IC2451 for audio enhancement
processing where are the outputs for the final channels
that go to the audio amplifier and to the FAO/VAO
integrated circuit IC2331.
• AI Sound -Artificial Intelligence Sound,
compensates the level variation within a program
or signal, in order to avoid critical changes in
volume. (IC2451)
• Surround and BBE sound effect -To improve sound
quality. (IC2451)
• Audio Out, FAO (Fixed Audio Output) and VAO.
(Variable Audio Output) IC2331
DX4P TG
DX4P TG - 21 -
 Video - Synchrony

- 22 -
Figure 15. Video-Sync Path Diagram

DX4P TG
 Video switching
Video signals from tuners and video inputs are selected in IC3001. Selection is controlled by the MPU circuit
through I2C bus (SDA & SCL).

Figure 16. IC3001 Video Switch Block Diagram.

Main and sub selected picture input the second video switch IC3002, to be switched with the component and DVI
input.

DX4P TG - 23 -
 Figure 17. IC3002 Video Switch Block Diagram.

Second video switch outputs selected main and sub

video signals, those signals will enter the main global
core and sub global core for picture processing

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Main Picture Global Core
Output from video switch, IC3002, Pb, Pr and Y are conducted to Global Core IC4511. Global core converts to dig-
ital the input signals and performs the picture process.

Global Cores Block Diagram

Analog signals input the A/D converter, the output is a
10 Bit digital signal, which will be input to the 3 line dig-
ital Comb Filter block, the output are the color
(Chroma) and luminance signals. Color signal is pro-
cessed, global core features color AI (to adjust color
level) and noise reduction filter.
Luminance signal inputs the sync section, this way
main signal global core will provide the sync horizontal
and vertical pulses for the deflection circuit.
Difference color signals (ER-EY, EB-EY, ER-EY) enter the
matrix block in the RGB processor, in this block lumi-
nance (Y) is added to the difference-color signals. Final
color signals (R,G,B) are leveled and adjusted for cor-
rect bright level in the picture.
Pb and Pr signals enter to the chroma block, within this
block, G-Y is generated from R-Y (Pr) and B-Y (Pb).
The following section explains the basic concept for
this operation.
Equations and values will change from standard defini- Relative Visibility Curve.
tion to high definition.

DX4P TG - 25 -
Standard Definition High Definition

The percentage of visibility of the blue(11%), The percentage of visibility of the Blue(21.25%),
green(59%) and red(30%) describe the luminance as: Green(71.51%) and Red(.0721%) describe the lumi-
EY = .3ER + .59EG +.11EB (1) nance as:
Since for simplicity only two difference color signal EY = .2125ER + .7154EG +.0721EB (1)
(color signal without luminance signal) are transmitted: so we can obtain difference color signal:
ER-EY , EB-EY ER-EY , EB-EY
From the IRE level we have: ER-EY = .7ER - .59EG -.11EB
ER-EY = .7ER - .59EG -.11EB EB-EY = -.3ER - .59EG +.89EB
EB-EY = -.3ER - .59EG +.89EB and from:
PR= .6349(ER-EY)
In chroma block EG-EY is obtained from (1) PB= .5389(EB-EY)
Signals:
EG = (EY - .3EG -.11EB)/ (.59) PR= .6349 (7.9ER - 7.1EG - .7EB)
EG = 1.7EY - .51ER -.19EB PR= 5ER - 4.5EG - .4EB
EG=1.7EY -.51ER+(.51EY-.51EY) -.19EB + (.19EY - PB= .5389 (-2.1ER - 7.1EG + 9.3EB)
.19EY) PB= -1.1ER - 3.8EG + 5EB
EG = 1.7EY - .51(ER-EY) - .51EY - .19(EB-EY) -.19EY
EG = EY - .51(ER-EY) - .19(EB-EY)

So finally in terms of ER-EY, EB-EY:

EG-EY = - .51(ER-EY) - .19(EB-EY).

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 Signal processing
480i NTSC Standard Signal
If selected signal from component video switch IC3002
from IC3001 is in standad format (480 NTSC), the lumi-
nance (Y) and chroma (C) mixed signals input the main
global core IC4511, and are converted to 10 bits digital,
then input the Y/C separation block (3D comb filter)
and chroma decoding, then the signal enters the NR/
IP/JUST block to achieve a cleaner image reducing the
noise, improving picture quality and converting the
interlaced signal to a progressive signal using the scan
doubler algorithm; then the signal enters sub global
core IC4518 to the HScaler/Gain block to adjust the
gain of the video signal to a proper level (in case of a
lower voltage); once the signal is processed, it loops
back to the main global core and is input to the Y/C AI
block where it is adjusted by the artificial intelligence
circuit for a better luminance-chroma level to finally
input to the RGB color matrix where all of the difference
color signals are mixed together. After this process, this
IC converts the signal from digital to analog and the
color signals are input to the to the RGB driver for final
Simplified Global Core Block Diagram
480p Component Video Signal
(Y,Pb,Pr)
If selected signal from component video switch IC3002
is in 480p format, Y input the external 10 bit high speed
A/D converter(IC4506), digitalized signal Y inputs
directly to main global core IC4511 through the YUV I/
O bus, to the NR/IP/JUST block; the Pb and Pr sig-
nals enter to the main global core directly for analog to
DX4P TG - 27 -
contrast and brightness adjustment and to be mixed
with the OSD information.
480i S-Video Signal (Y/C)
If selected signal from video switch IC3002 from
IC3001 is in 480i S-Video format, the luminance (Y)
and chroma (C) already separated signals input the
main global core IC4511, and are converted to 10 bits
digital, then bypass the Y/C separation block (3D comb
filter) and then goes through chroma decoding, the sig-
nal enters the NR/IP/JUST block and follows the rest of
the adjustments.
Component Video Signal (Y, Pb,Pr)
If selected signal from component video switch IC3002
is in 480i Component format, the Pb, Pr and Y sepa-
rated signals input the main global core IC4011, and
are converted to 10 bits digital, then bypass the Y/C
separation block (3D Comb Filter) and chroma decod-
ing, the signal enters the NR/IP/JUST block and follows
the rest of the adjustments.
digital conversion, bypassing the comb filter/chroma
decoding and input to the NR/IP/JUST block where the
signal is mixed along with the external luminance sig-
nal; in this block the IP processor does not perform any
interlaced to progressive operation, just the picture
improvement process and the remaining adjustments.
The values of the RGB color matrix change when the
standard and high definition modes are selected (by
the user).
1080i High Definition Signal
If selected signal from component video switch IC3002
is in 1080i (HD) format, Y input the external 10 bit high
speed A/D converter(IC4506), digitalized signal Y
inputs directly to main global core IC4511 through the
YUV I/O bus, to the NR/IP/JUST block; the Pb and Pr
signals enter to the main global core directly for analog
to digital conversion, bypassing the comb filter/chroma
decoding and input to the NR/IP/JUST block where the
signal is mixed along with the external luminance sig-
nal; in this block the IP processor does not perform any
interlaced to progressive operation, just the picture
improvement process and the remaining adjustments.
The values of the RGB color matrix change for the
1080i resolution.
- 28 -
Picture in Picture (PIP), Split and
Window Search Mode
When PIP is activated, main picture signal enters glo-
bal core IC4511, is converted to 10 bits digital, (only if
the video signal is composite, input to the Y/C separa-
tion block in the 3D comb filter passing through the
chroma decoder) and enters the NR/IP/JUST block
and enters global core IC4518 to the horizontal scaler
circuit; the sub signal, inputs to the sub global core
IC4518 converting the signal to an 8 bit digital, (if the
signal is in composite video, pass through a 2D comb
filter and chroma decoding process), input to the hori-
zontal scaler to process the resolution and vector local-
ization for the PIP window, split window or window
search. In this section both the main and sub signal are
combined together so the scanning process can be
obtained by displaying the two signals. Once the two
signals are combined they pass trough the noise
reduction block to achieve a sharper image; once the
signal is filtered and mixed it goes back to the main glo-
bal core to follow the rest of the adjustments entering
the RGB matrix block for a proper color signal output.
DX4P TG
 AUDIO

COLOR TELEVISION SYSTEM

DX4P CHASSIS
 MTS Sound Detection And Separation
Composite Signal
The composite audio signal from the tuner inputs to
MTS Decoder IC2201 pin 14 (MPX in) (see Block
Diagram).
The signal is processed by a low pass Stereo Filter
which passes signals below 15.75kHz. The output from
the Stereo Filter contains the L+R signal (mono) and
may also contain the L-R signal (stereo) plus the
Stereo Pilot signal (stereo broadcast indicator). The
signal is then applied to four circuits:
• Pilot detector
• Stereo PLL
• L+R Demod (FM)
• L-R Demod (AM)
Mono or L+R Signal
The L+R signal is FM demodulated and then sent to
the L+R Filter. The high frequency components of the
signal are de-emphasized and sent to the Matrix circuit
for left and right channel simulation.
L–R Signal
When the 145.75kHz stereo pilot signal is detected at
pin 6, indicating AM stereo broadcast, the stereo PLL
switches on the L-R Demod to demodulate the AM
signal.
The signal is then passed to the L-R Filter which
removes the high frequency noise components.
The signal is then passed to the L-R/SAP switch, which
is controlled by I2C bus user input (Stereo or SAP), and
output to pin 15.
The signal from pin 15 is coupled via an external
capacitor to pin 16 and applied to the dbx circuit.
Secondary Audio Program (SAP) mode
The input signal applied at MTS IC2201 pin 14 (MPX
in) is fed to the SAP Filter and the Noise band pass
filter (BPF). The Noise BPF removes components
around 240 kHz.
If Stereo is selected, the signal is passed through the
SAP Noise Detector to the SAP Demod to mute the
SAP demodulator.
DX4P TG - 31 -
If SAP is selected, the SAP signal is demodulated,
filtered for noise components, output via pin 13, and
applied to the dbx circuit via pin 12.
dbx® Effect
dbx is a compression, expansion, pre-emphasis, de-
emphasis system that reduces the overall audio noise
level. As the overall level in the audio chain increases,
the noise level increases also. With dbx, the audio level
increases, but by only half as much.
Using a 2 to 1 compression ratio, the input signal is
compressed and a “shelving” filter is referenced to the
input level to set the pre-emphasis. A shelving filter is a
circuit with a flat frequency response that has two
bands of frequencies that are separated by a third
band. This third band has either a downward or upward
sloping frequency response.
The output signal is decompressed and the high
frequencies are rolled off by the de-emphasis filter. The
output audio signal now has a greater S/N than the
input signal. It has a flat frequency response and up to
30 dB less noise.
Note: MTS IC2201 pin 10 is the timing current
setting of the dbx rms value detection, and is
set at about 1.3V. Pin 6 is the reference
power supply stabilization voltage, and is set
at about 4.5V.
dbx is a registered trademark of Carillon Electronics
Corp.
Matrix Circuit
The matrix circuit switches the output audio signal
according to the selection received from MPU IC4002
through the I2C bus at pins 19 (SDA) and 18 (SCL).
The signals are output through pins 21 (L-out) and 22
(R-out) to the sound switching circuit.
Selection Matrix Effect
Mono L+R or mono to output to pins 21 & 22
( L + R ) + ( L – R ) to pin 22
--------------------------------------------
Stereo 2
(L + R) – (L – R)
------------------------------------------- to pin 21
2
SAP SAP to output to pins 21 & 22
- 32 -
DX4P TG
Figure 17. Multiplex Television Sound (MTS) Block Diagram
BBE SOUND*
BBE Sound is a feature in the DX4P chassis which pro-
vides clearer, natural and more detailed sounds.
To understand how BBE sound technology works, con-
sider the characteristics of a loudspeaker and what we
expect from one. Among a loudspeaker’s most impor-
tant requirements is the ability to reproduce transients -
the brief high-energy burst at the beginning of sound.
The transients then evolve into harmonics. It is the par-
ticular amplitudes and phase relationships of these
transients and harmonics which add the unique color
and character to each sound.
Varying either the amplitude or the phase of the tran-
sient and harmonics within signal causes distortion of
the sound’s characteristics.
A loudspeaker’s transient response is typically
expressed in terms of amplitude response (How
quickly it reacts to an incoming signal), with little or no
regard to phase response (Whether high and low fre-
quencies are reproduced at the proper time).
If a loudspeaker’s amplitude response curve were lin-
ear, then the relationship between the high and low fre-
quencies would be correct. And if a loudspeaker’s
phase response curve were linear then the low and
BBE TECHNOLOGY
The input signal is separated into three regions: Bass
(20Hz to 150Hz) Middle (150Hz to 2.4kHz) and treble
(2.4Khz to 20KHz). These regions are joined again with
the middle and treble regions phase shifted -180o and -
360o respectively with respect to the bass signal. This
phase shift adjusts the delay time characteristic for
each band and minimizes the distortion of the rising
section of the signal.
*BBE is a Registered Trademark of BBE Sound, Inc.
DX4P TG - 33 -
high frequencies would reach the listener’s ears in their
correct time order, but, this is not the normal case.
When we listen to live sounds, all the highs and lows
reach our ears in the same relationship to each other
as when they were created, but after recording and
played through a loudspeaker system, the loudspeaker
would introduce frequency-dependent shifting. The
inductance of the speaker’s voice coil creates a stron-
ger impedance as the signals frequency increases,
resulting in a time delay. Consequently, frequency com-
ponents with large negative phase shifts (High frequen-
cies), arrive at the listener’s ear later than signal
undergoing small phase shifts (low frequencies). The
resultant signal is distorted in the time domain to the
listener’s ear; the raise of sound is distorted and the
phase of playbacked sound is deviated.
In order to address the problems inherent in basic loud-
speaker design, the BBE technology has two primary
functions; adjust the phase relationships of low and
high frequencies (loudspeaker natural tendency to
delay higher frequencies) and augmentation of the
higher and lower frequencies (Loudspeakers tend to be
less efficient in their extreme treble and bass ranges).
 1 To maintain appropriate auditory balance for the treble
fC1 = Hz region that is made up of harmonic components, a high
2π x 21.5k x C1
-speed detector and high-performance VCA circuit are
1 Hz used for amplitude control of the treble component.
fC2 =
2π x 21.5k x C2 The amount of compensation is determined from a
1 calculation performed based on the DC level input to
fC3 = Hz
2π x 21.5k x C3 the control pin, and the DC level detected from the
input signal. The internal control signal obtained from
C1 = Capacity between pin 6&7 and pin this calculation compensates the amplitude of the
27&26. treble component input to the VCA. However, if treble
C2 = Capacity between pin 8&9 and pin is clear, it may seem that bass is insufficient. This can
24&25. be corrected applying the gain to bass.
This amplitude compensations recovers the harmonic
FC3 is internally fixed to 60.3KHz, C3=47pf
component, and improves the reproduction clarity
(definition level) of any sound (frequency).

BBE ViVA digital formats. Also offered will be BBE ViVA+™ which
adds the proprietary BBE Mach3Bass™ enhancement
system.
BBE ViVA™ is a new High Definition 3D Sound
technology which integrates a 3D enhancement effect
with BBE High Definition Sound. ViVA creates an
authentic and exciting 3D sound effect from stereo
speakers while preserving the clarity, definition,
presence and texture for which BBE High Definition
Sound is noted. BBE ViVA is now being offered to BBE
licensees in the consumer electronics industry.

An important feature of BBE ViVA is its ability to

maintain proper sound stage imaging. Ordinary 3D
sound effects often tear the stereo image down the
middle, resulting in centrally staged audio material,
such as diologue, becoming fuzzy or even
disappearing. BBE ViVA is different because it
maintains crystal clarity for solo vocals and movie
dialogue. BBE ViVA will be offered in both analog and

- 34 - DX4P TG
Function Overview
BBE ViVA High Definition 2-Speaker 3D Sound
• Musically accurate natural 3D image with Hi-Fi Sound.
• Increased width, depth and height of sound image keeping Clear Directionality.
• Rock solid Center Channel.

• Replaces conventional 3D sound process with more natural and clear sound.
• BBE ViVA is compatible with News, Dramas, Movies, Music, Sports and Games. (BBE ViVA can be left on all
the time. No need to switch the audio modes every time program changes.)
• Monaural program is kept in monaural to preserve the format.
• Analog and Digital

DX4P TG - 35 -
BBE ViVA (NJW1147A) IN DX4P
The NJW1147A is a TV audio processor with BBE ViVA High Definition 3D Sound process. BBE’s traditional sound
clarity enhancement technology is combined with the new ViVA 3D process to create an spatial effect. BBE ViVA is
compatible wit news,music and movie programs as well as video games. In DX4P, audio signal process is
performed in A-Board. Plainly speaking; audio signal from main tuner, with left and right channels mixed, inputs to
MTS integrated circuit (Sound Decoder).The outputs are independent left and right channels.Those signals input
the RF-AV switch. The selected channels are then input to an audio switch to select between component input
audio signal and AV/RF audio signal.Finally the selected channels are input to sound processor IC(IC2451) before
going to final amplification and speakers.

Figure 18. IC2451 BBE ViVA Sound Processor

- 36 - DX4P TG
 TERMINAL DESCRIPTION TABLE

TERMINAL TERMINAL
FUNCTION
NO. NAME

1 INa Ach Input

30 INb Bch Input

2 BBE1a Ach BBE Filter1 (Process)

29 BBE1b Bch BBE Filter1 (Lo Contour)

3 BBE 2a Ach BBE Filter2 (Lo Contour)

28 BBE 2b Bch BBE Filter2 (Process)

4 BBE OUTa Ach Output for the Other Accessories

27 BBE OUTb Bch Output for the Other Accessories

5 TONE INa Ach Input From the Other Accessories

26 TONE INb Bch Input From the Other Accesories

6 TONE-Ha Ach Treble Filter

25 TONE-Hb Bch Treble Filter

7 TONE-La Ach Bass Filter

24 TONE-Lb Bch Bass Filter

8 OUTa Ach Output

23 OUTb Bch Output

9 AGC AGC Filter

10 SS-FIL Simulated Stereo Filter

11 CVB DAC Output for Bch Volume and Balance

12 CVA DAC Output for Ach Volume and Balance

13 SDA SDA Data Input (IIC BUS)

14 SCL SCL Data Input (IIC BUS)

15 GND GND

16 Vcc Power Supply Pin

17 AUX1 Auxiliary Output 1

18 AUX0 Auxiliary Output 0

19 CTL DAC Output for Tone Low Frequency

20 CTH DAC Output for Tone High frequency

21 VREF Reference Voltage

22 SR-FIL Surround Filter

IC2451 performs the DX4P audio features: volume All functions are controlled by the MPU through the I2C
(main volume), tone (Bass/Treble) control, L&R
bus data in the format: (refer to I2C bus system section
balance, surround (mode and effect) and BBE (effect)
for more information)
sound.

DX4P TG - 37 -
 SIGNAL PROCESSING
Selected left and right channels from audio switch are
MSB LSB MSB LSB MSB LSB input to IC2451 pins 1 and 30. Internal processing for
S Slave Add A Select Add A Data A P both channels is the same.
AGC (Auto Gain Control)
1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit
In order to compensate the level (amplitude) of the
incoming audio signals, IC2451 includes an auto gain
control section, which will provide leveled signals to the
Start condition next section. AGC can be bypassed by MPU through
• S
Recognition of Start bit I2C bus, in that case input signal goes directly to pre-
Recognition of IC amplification section.
The AGC suppression level (GC) can be set by the
The High order 7 bits are
• Slave Add voltage of AGCADJ terminal (Pin 9) and will be
optional. The least significant bit expressed as:
is “L” for writing.
GC (mVrms) = -286 x AGCADJ(V) + 1186
Acknowledge bit Time constant for suppression and amplifying. This will
• A
Recognition of acknowledgment let the IC to set the attack (amplification response) and
recovery (suppression response) time for amplifying
Feature select
and suppression circuits separately.
Selection of 1ch volume, 2ch
• Select Add volume, BBE effect, bass+BBE, Capacitor connection terminal for AGC attack
treble+Mute and AGC+matrix and recovery time setting
surround.

• Data Data on volume and tone

Stop Bit
• P
Recognition of stop bit.

If the constant of capacitor C2 of LS2 decreases, the

starting point for amplification is lowered in order to
detect smaller signals. Making C2 smaller will change
the distortion rate, changing in extreme the circuit will
become more sensitive to noise influence.

After AGC section (or next if it was bypassed), the pre-

volume block amplifies the signal that will feed the BBE
Section, BBE can be also bypassed by the MPU
through I2C bus.See “BBE TECHNOLOGY” on
page 33 for BBE details.
Pins 6,7,24 and 25 are used to set the bass and treble
frequencies for both channels.

- 38 - DX4P TG
Next, signal goes to surround and pseudo stereo STEREO
(stereo enhanced) effect process.
LOUT = L+∆t1∆t2P1P2(L+R)E
SURROUND
∆t1xP1 ∆t2xP2 xE
This IC has an output terminal for surround signal. The
terminal can be used also to set the frequency
characteristic for the surround effect by adding the
appropriate filter.

Surround Signal Terminal ROUT = R-∆t1∆t2P1P2(L+R)E

The characteristic of surround and pseudo stereo can

be varied by changing the effect level.

Surround and stereo effect is then added to one

channel and substrates to the other.This operation
completes the effect to the listener.

After effects section, signal inputs tone control block.

Surround and Pseudo Stereo Operation

The surround and pseudo stereo effect (stereo
enhanced) works in blocks as follow:

Surround LOUT = L+∆t1∆t2P1P2(L-R)E

∆t1xP1 ∆t2xP2 xE

ROUT = R-∆t1∆t2P1P2(L-R)E

DX4P TG - 39 -
TONE:
Bass and treble levels are defined by user, IC2451
uses pins 10 & 23 to set bass frequency and pins 11 &
23 for treble frequency as follows:

Setting of Bass Frequency

Setting of Treble Frequency

Channels go through final pre-volume amplification an

output at pins 12 and 21.

- 40 - DX4P TG
Audio Switching
Audio signal is selected in IC3002 and IC3003. User AV1, AV2, AV3). Audio switch is controlled by MPU
selection in menu, defines signal source (RF tuner, through I2C bus (SCL & SDA).

Figure 19. IC3001 A/V Switch (Audio Inputs switching diagram).

DX4P TG - 41 -
 Figure 20. IC3002 A/V Switch (Audio Inputs switching diagram).

Audio Processing
DX4P features selectable status for BBE sound, this
means that this function may be disabled by user in the
roller-guide menu. If this is the case, the MPU will
bypass the section of the sound processing in IC2451,
for detailed information, refer to the “BBE sound”
section.

- 42 - DX4P TG
Amplification
Output amplification is performed by IC2301. Audio
output power is 15W (10%) per channel using 8Ω
speakers.

Figure 21. IC2301 Audio Amplifier Block Diagram

Main volume is controlled by MPU through I2C Bus
and is processed at IC2451.
MUTE
This function is controlled by MPU through I2C Bus, If
selected, IC2451 set output levels to zero.
If fixed audio output function is selected, speakers are
turned OFF in same way as in VAO mode. Volume is
now fixed by MPU and should be controlled by an
external amplifier.

VAO
If variable audio output function is selected by menu,
speakers are turned OFF, IC001-84 SPEAKER ON/
OFF goes from low (0V) to high (3V) activating Q2336,
this will set a high level to IC2301-8,mute input in audio
amplifier. This way audio output will be at AUDIO OUT
output jack. The variable audio output volume is
controlled by MPU through IC2451.

FAO

DX4P TG - 43 -
 Figure 22. VAO/FAO Audio Mute diagram

SOUND DEFEAT
This function is included in order to avoid noise at
receiver’s speakers or at external speakers while
receiver is being turned ON or OFF.
When receiver is turned ON/OFF Pin 84 goes from low
(0V) to high (3V) for a few seconds, this will mute the
audio amplificator output.
S-DEFEAT (IC001 pin 1) goes from low (0V) to high
(3V), this will mute any signal at the audio output jacks.

Figure 23. Sound Defeat operation diagram

- 44 - DX4P TG
 SYNCHRONY

COLOR TELEVISION SYSTEM

DX4P CHASSIS
Horizontal Deflection
General Description
The scanning procedure used in the United States and
many countries employs horizontal linear scanning in
an old-line interlaced pattern. The standard scanning
pattern for television systems includes a total of 525
horizontal scanning lines in a rectangular frame having
an aspect ratio of 4 to 3. The frames repeated at a rate
of 30 per second, with two fields interlaced in each
frame.
The first field in each frame consists of all odd-number
scanning lines, and the second field in each frame
consists of all even-number scanning lines. The field
repetition rate is thus 60 per second, and the vertical
scanning rate is 60 Hz.
The standard odd-line interlaced scanning pattern is
illustrated in Fig. 23. The scanning beam starts at the
upper left corner of the frame at point sweeps across
the frame with uniform velocity to cover all the picture
elements in one horizontal line, and ends at the bottom
middle of the frame. At the end of each trace, the beam
is rapidly returned to the left side of the frame, as
shown by the dashed speed.
The horizontal lines slope downward in the direction of
scanning because the vertical deflecting signal
simultaneously produces a vertical scanning motion,
which is very slow compared with the horizontal
scanning speed. The slope of the horizontal-line trace
from left to right is greater than the slope of the retrace
from right to left because the shorter time of the retrace
does not allow as much time for the vertical deflection
of the beam.
Thus, the beam is continuously and slowly deflected
downward as it scans the horizontal lines, and its
Figure 23. Scanning Frames.
DX4P TG - 47 -
position is successively lower as the horizontal
scanning proceeds.
At the bottom of the field, the vertical retrace begins,
and the beam is brought back to the top of the frame to
begin the second or even-number field. The vertical
“flyback” time is very fast compared to the trace, but is
slow compared to the horizontal scanning speed;
therefore, some horizontal lines are produced during
the vertical flyback.
All odd-number fields begin at point A, end at point B,
and are the same (see Fig. 23. All even-number fields
begin at point C, end at point D, and are the same.
Because the beginning of the even-field scanning of at
C is on the same horizontal level as A, with a
separation of one-half line, and the slope of all lines is
the same, the even-number lines in the even fields fall
exactly between the odd-number lines in the odd field,
and thus the even and odd-number fields are perfectly
interlaced.
Horizontal Deflection System
The main functions of the horizontal deflection system
in a television receiver are to deflect the electron beam
linearly (from left to right) across the picture tube
screen, return the beam rapidly to the left side of the
screen, and then repeat the process. The Fig. 23
shows an idealized waveform of the current that
passes through the horizontal deflection yoke windings
during one complete scanning cycle.
Vertical Output Circuit
Vertical sawtooth signal is generated and output from
main global core (IC4511 in DG-Board), then is pre-
amplified by the IC4010 to gain a proper vertical
sawtooth level signal then is output to D-Board to the
vertical driver circuit.
The vertical center sawtooth signal is input to an RC
circuit. The sawtooth enters to IC451 amplifying the
signal and converting it to the vertical pulse.
Once amplified the signal is conducted to the vertical
deflection coils and the vertical shape is input to a lin-
earity-simetry correction circuit to improve the vertical
output wave signal; the corrected wave is feed back to
IC451 through pin 1.

TO DY

V SAW
FROM
IC4511

Figure 24. Vertical drive circuit

Pincushion correction circuit (PCC)

The distance between the CRT phosphor screen and
the deflection point of the electron beam increases at
the periphery of the CRT. Deflection must therefore be
increased where that distance is the greatest, and
where pincushion distortion and focus error occur in
the raster.
To correct the pincushion distortion on the left and right
sides of the raster, it is necessary to perform amplitude
modulation in the form of a parabola on the amplitude
of the horizontal deflection current during the vertical
scan period.
Focus error is corrected in a similar way by sending
parabola waves to control the dynamic focus circuit.

- 48 - DX4P TG
Horizontal deflection circuit

TO DY

H DRIVE
FROM
IC4511

EW DRIVE
FROM
IC4511

Figure 25. Horizontal deflection circuit

Vertical drive circuit Vertical amplification

The vertical drive is made up of two PWM signals (V-
RASTER and V-OUT) that are output from the MPU.
Both signals are integrated by an RC circuit; the V-OUT
signal is first coupled and inverted by two transistors
(Q401 and Q402) to finally obtain a proper sawtooth
signal. A DC voltage level is obtained when the V-
Raster signal is integrated, which is going to be the DC
offset reference for the vertical sawtooth signal.
The vertical center sawtooth signal is input to an RC
circuit that corrects the DC center voltage for the
vertical sawtooth signal. The sawtooth enters to IC451
amplifying the signal and converting it to the vertical
pulse. Once amplified the signal is conducted to the
deflection yoke coil and the vertical shape is input to a
linearity-simetry correction circuit to improve the
vertical output wave signal; the corrected wave is feed
back to IC451 through pin 1.

DX4P TG - 49 -
Horizontal trapezoid circuit

The Horizontal trapezoid control is an adjustment that

can be performed on service mode in order to control
the shape of the trapezoid compensating the “yoke
defect”.
The IC4805 is a signal gain controller circuit that can
adjust two incoming signals to a certain level. The gain
is controlled directly from the MPU via I2C Bus.
The incoming vertical sawtooth wave signal is switched
to the Q4901 in order to obtain two signals, one is
output from the emitter and the other from the collector
in order to obtain a inverted sawtooth wave. Both
signals (left and right) enter to IC4805 and are adjusted
to a specific gain level (set by the balance adjustment).
When both signals are processed they output to the
resistors R4934 (right) and R4935 (left) to obtain a DC
voltage depending on the average summatory voltage
of both sawtooth signals. After this signal is obtained it
gets input to the tilt correction circuit for the proper
deflection signal adjustment on the DY coil.

- 50 - DX4P TG
Tilt correction and landing correction
The tilt correction is applied in the DX4P family to
correct the alignment of the deflection yoke in a 1cm
range of picture rotation. This adjustment can be
performed by the user without affecting any adjustment
of purity.
The landing correction or best known as “geomagnetic
correction” is an utility for degaussing the CRT
removing the decoloration caused by the different
magnetic fields on earth.
The tilt correction and landing correction processing
work in a similar way. Both signals from MPU are
output as a variable signal applying a pulse width
modulation (PWM), to get the reference voltage
needed to perform the adjustment.

Figure 26. Reference signal voltage level

The PWM signals (Tilt & Landing) are output from the
MPU (A). Then the voltage signal is drop down to a .8V
by a resistor array (B) in order to achieve the base
voltage that is going to be amplified by the transistors
(Q009, Q019). Then the signal amplified to a 7V level,
is output from the collector (C), and then is rectified by
an RC network in order to obtain a proper gain level of
DC voltage (D).
Once obtained the voltage level the signals enter to the
operational amplifiers (IC4804, IC4807) that perform a
comparison between a set voltage and the signal
voltage (Tilt or Landing).
The rectified voltage level (D) is achieved depending
on the PWM percentage from (A) (as shown in
Fig. 26).

Figure 27. PWM voltage level output

DX4P TG - 51 -
Horizontal and Vertical Dynamic Astigmatic Focus Circuit (DAF)

Figure 28. Dynamic Astigmatic Focus circuit

Large flat CRT tubes like the ones used in the DX4P
family have the tendency to display blurry images on
the corners of the screen compared with CRT tubes
with curved faces. This effect is caused because the
distance from the center of the screen to the electron
gun is shorter than the distance from the corner of the
screen to the electron gun, where the electron beam
appears more blurry.

The way to display a signal more flatter and sharper is

varying the voltage across the screen, being higher at
the corners and lowest in the center. If the electron
beam spot size is to be maintained over these varying
distances, the focus must be changed as the beam
sweeps across the screen varying the voltage in the
electron gun in a waveform of a parabola. This is called
the dynamic Astigmatic Focus Circuit.

The MPU has a reserved PWM output for the

horizontal dynamic focus correction application (pin
61). For the vertical scanning it uses the general
purpose V-SAW signal (pin 68). Both of these signals
are input to a parabola amplifier circuit (Q1551 and
Q1553) where the original signals are transformed into
parabola waveforms (vertical and horizontal) and are
fed into the T1551 transformer to obtain a high voltage
amplification.
In order to obtain the most possible clear image at the
edges of the CRT tube, the heater pulse and the
horizontal parabola peak voltage have to be in the
correct phase alignment.

- 52 - DX4P TG
 POWER
SUPPLY

COLOR TELEVISION SYSTEM

DX4P CHASSIS
Power supply voltages
DX4P Power supply and B+ voltages are similar as
other Panasonic CTV families.
AC voltage supply is controlled by MPU via RL801. If
high level is present at Q802-Base,the relay will be
closed, turning on the set. Rectified Voltage from D801
input the B+ voltage transformer T801 and the Voltage
Controlled Oscillator (IC801). This transformer will
provide AC voltage for te various power lines.
DX4P TG
Figure 31. Power supply voltages
FROM IC801
FROM IC801
When voltage is present at IC801 pin 7, IC801 starts
oscillation, output by pin 6 will feed 400 Vpp pulse to
FBT pins 4 and 5.
IC802 and opto coupler IC811 stabilize the B+140V.
Pin 1 monitors the 140V line.If the 140V increases at
pin 1, the output at Pin 2 decreases. This will cause the
light emittted by the LED in the Opto-coupler to
increase.
- 55 -
Switching Regulator
Incoming A.C. is rectified by bridge rectifier (D801, D802,
D803, D804) and filtered by C806, C811 and C804).

The D.C. start voltage appears across R814 and charges

C820.

The start voltage appears at pin 7 (Vcc) of IC801 and

starts the oscillation as shown at point a in Fig. 32.

When Q801 turns on, the oscillation is continued by the

discharge of capacitor C820.

Current flows through small bias coil T801, diode D806

and resistor R818 to continue the voltage oscillation.

If there is no voltage from diode D806, the discharge of

C820 will continue until oscillation ceases as shown at
point c in Fig. 32.

Figure 32. Start Waveform

Oscillating Circuit

Figure 33. Oscillating circuit

The oscillating circuit (Fig. 33) is formed by C803 tied to
IC801 pin 3 (t on) and C810 and R817 tied to pin 2 (T
OFF). It generates a pulse which turns Q801 on and off.
When the voltage at IC801 pin 7 reaches the starting
voltage, a high-voltage pulse is output to pin 6. At the
same time voltage is supplied to pin 3, gradually
charging C803. Once the voltage reaches 0.7V, the
oscillation current output pulse stops and Q801 is turned
off. Pin 3 voltage is discharged rapidly to 0V by the
internal discharge circuit.
When Q801 is turned on, C810 is charged to the
specified voltage (0.9V).
Once the T ON voltage reaches 0.7V, the 0.9 voltage
charged to C810 is discharged over a set period of time
through R817. When this voltage reaches 0.1V, the
oscillation output again inverts and a high voltage is
output to pin 6, turning Q801 on. Again, C810 is charged
to 0.9V. The normal Q801 on time is set by the TDL
terminal voltage.
The power supplied to T ON is controlled by the feed
back (FB) terminal of pin 9. When C803 is charging, the
on time for Q801 is controlled and used to stabilize the
B+ voltage.
C803.

- 56 - DX4P TG
Constant voltage control

Figure 34. Constant voltage control

IC802 and optoisolator IC811 stabilize the B+ 140V.

Pin 1 monitors the 140V line. If the 140V increases at
pin 1, the output at pin 2 decreases.

This will cause the light emitted by the LED in the

optoisolator to increase.

As the light emitted by IC811 is increased, the voltage

at IC801 pin 9 decreases, thereby raising the current
sent to IC801 pin 3 from the internal transistor. This
reduces the charge time for C803.

As the charging time for C803 becomes shorter, the on

time for Q801 is reduced and the oscillation frequency
is raised, causing the B+ voltage to decrease.

DX4P TG - 57 -
Power supply Stand-By voltage

AC_SW
FROM
MPU
IC4002

Figure 35. Stand-By voltage

- 58 - DX4P TG
 Protection circuits
The DX4P is designed with circuits that protect the
chassis from high-voltage, shorts and sudden losses of
power to the subsystems. If any of these situations
occur, SOS voltage output from each protector circuit
appears at MPU (IC4002) SOS.
When the voltage at MPU pin 56 goes high at about
3.2V (normally LOW at 1.5V), pin 45 (AC_SW), turns
off the A.C. relay (RL801 on A-Board) to shut down the
set.
140V Power supply
If the circuit connected to the 140V supply is broken,
the 140V line voltage drops, turning on Q854 (D-Board)
and sending SOS voltage to MPU to turn off the A.C.
relay (RL801).
25V Power supply
If the 25V power supply circuit is broken, Q804 turns on
Q804 (D-Board) and SOS voltage is sent to MPU to
disable the A.C. relay (RL801).
DX4P TG
15V Power supply (vertical)
If the vertical output circuit is broken, its 15V line
voltage drops, turning on Q405 (D-Board) and SOS
voltage is sent to MPU to disable the A.C. relay
(RL801).
Focus short protecter
The focus voltage from flyback transformer (T551 D-
Board) pin 15, enters to comparator IC1501 pin 5 (D-
Board.
This integrated circuit compares the voltage with a
reference voltage at pin 6.
If the focus circuit is shorted, the focus voltage output
from FBT pin 15 drops causing the voltage at IC1501
pin 5 to go lower than the pin 6 reference voltage. Then
IC1501 pin 7 causes the SOS voltage to go to MPU to
turn off A.C. relay RL801.
- 59 -
 75 OUTPUT OSC2 Clock Pulse Signal
78 OUTPUT SCL0 I2C Bus Serial Clock 0
81 OUTPUT 140V_SW +B On-Off
PIN NUMBER TYPE CONTROL FUNCTION DESCRIPTION
71 I/O SDA1 I2C Serial Data Bus 1
80 I/O SDA0 I2C Serial Data Bus 0

PIN NUMBER CONTROL FUNCTION DESCRIPTION

32 AVDD ANALOG VOLTAGE SUPPLY

37 VSS GROUND REFERENCE

41 VPP VOLTAGE SUPPLY

74 VSS GROUND REFERENCE

77 VDD VOLTAGE SUPPLY

DX4P TG -9-