956 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO.

2, FEBRUARY 2017

A Capacitor Voltage Balancing Strategy With

Minimized AC Circulating Current for the DC–DC
Modular Multilevel Converter
Heng Yang, Student Member, IEEE, and Maryam Saeedifard, Senior Member, IEEE

x,j
Abstract—The dc–dc modular multilevel converter Pac Fundamental ac component of the power of the x
(MMC), which has originated from the ac–dc MMC circuit arm of phase-leg j.
topology, is an attractive converter topology for intercon-
nection of medium-/high-voltage dc grids. Proper operation vCx,j SM capacitor voltage of the x arm of phase-leg j.
of the dc–dc MMC necessitates injection of an ac circulating vCΣx,j Sum SM capacitor voltage of the x arm of
current to maintain its submodule (SM) capacitor voltages
balanced. The ac circulating current, however, needs to be
phase-leg j.
minimized for efficiency improvement. In addition, a unique v x,j Voltage of the x arm of phase-leg j.
x,j
type of imbalance amongst the SM capacitor voltages that vdc DC component of the x arm voltage of phase-leg j.
x,j
is caused by dc power flow needs to be mitigated. This pa- ṽac Fundamental ac component of the x arm voltage of
per proposes a closed-loop control strategy for the dc–dc phase-leg j.
MMC to simultaneously regulate the dc-link currents, main- x,j
tain the SM capacitor voltages balanced, and minimize the
|ṽac | Amplitude of the fundamental ac component of the
ac circulating current. Performance and effectiveness of the x arm voltage of phase-leg j.
x,j
proposed control strategy are evaluated based on simula- |ṽac |m ax Maximum attainable amplitude of the fundamental
tion studies in the MATLAB Simulink and experimentally ac component of the x arm voltage of phase-leg j.
verified on a laboratory prototype. ix,j Current of the x arm of phase-leg j.
Index Terms—DC–DC power conversion, high-voltage dc ix,j
dc DC component of the x arm current of
(HVDC) converters, modular multilevel converter (MMC). phase-leg j.
ĩx,j
ac Fundamental ac component of the x arm current of
NOMENCLATURE phase-leg j.
ijo Phase current of phase-leg j.
L Arm inductor.
φ Phase angle of the fundamental ac component of the
Lo Phase filtering inductor.
upper arm voltage with respect to the lower one.
XL Inductive reactance of the arm inductor.
ω Operating frequency.
XL o Inductive reactance of the phase filtering inductor.
v x,j,ref Reference voltage of the x arm of phase-leg j.
CSM SM capacitance. x,j,ref
vdc Reference dc component of the x arm voltage of
N Number of SMs in each arm.
phase-leg j.
M Number of phase legs. x,j,ref
ṽac Reference ac component of the x arm voltage of
D Voltage conversion ratio of the converter.
phase-leg j.
j Phase-leg j = 1, 2, ..., M . x,j,ref
|ṽac | Reference amplitude of the ac component of the x
x = p, n Converter arm (p: upper arm, n: lower arm).
arm voltage of phase-leg j.
Vdc1 , Idc1 Low-voltage side voltage and current.
φref Reference phase angle of the ac component of the
Vdc2 , Idc2 High-voltage side voltage and current.
upper arm voltage with respect to the lower one.
P Power throughput of the converter.
x,j
Pdc DC component of the power of the x arm of phase-
leg j. I. INTRODUCTION
HE dc–ac modular multilevel converter (MMC) has
Manuscript received April 28, 2016; revised July 13, 2016; accepted
August 8, 2016. Date of publication September 23, 2016; date of current
T become the most attractive converter topology for high-
voltage applications because of its high efficiency, scalabil-
version January 10, 2017. This work was supported in part by the
National Science Foundation under Grant 1443814 and in part by the
ity/modularity, and superior harmonic performance [1]. Over
Office of Naval Research under Grant N00014-14-1-0615. the past few years, extensive research has been done to address
The authors are with the School of Electrical and Computer Engi- the technical challenges associated with the operation and con-
neering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA
(e-mail: hyang302@gatech.edu; maryam@ece.gatech.edu).
trol of the MMC and to improve its performance for various
Color versions of one or more of the figures in this paper are available applications [1]–[4]. Those applications mainly include high-
online at http://ieeexplore.ieee.org. voltage dc (HVDC) transmission systems [5], [6] and variable
Digital Object Identifier 10.1109/TIE.2016.2613059
speed drives [7]–[11].
0278-0046 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

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 YANG AND SAEEDIFARD: CAPACITOR VOLTAGE BALANCING STRATEGY WITH MINIMIZED AC CIRCULATING CURRENT FOR THE DC–DC MMC 957

The single-stage dc–dc MMC that inherits the salient fea-

tures of the dc–ac MMC is a potential converter topology
to replace the conventional front-to-front dc–ac–dc converter
configurations [12]–[15] for medium-/high-power dc–dc con-
version systems, e.g., interconnection of dc grids [16]–[18].
Although the circuit topology of the dc–dc MMC, which here-
after is referred as the dc MMC, is derived based on the dc–ac
MMC, its basics of operation and control are different [19]. One
of the major technical challenges associated with the control of
the dc MMC is its submodule (SM) capacitor voltage balancing
task. In the dc–ac MMC, an SM capacitor voltage sorting and
selection mechanism combined with an open-loop controller is
capable of maintaining the SM capacitor voltages balanced. In
the dc MMC, the power flow in each arm can be decomposed
into a dc and an ac component. The dc power component is con-
trolled to transfer the commanded power between the input and
output dc links. An ac circulating current needs to be injected
and controlled to exchange active ac power between the upper
and lower arms of each phase-leg such that the power balance
of each SM capacitor is maintained. Since the arm active ac
power needs to be actively regulated, in case of the dc MMC,
the conventional SM capacitor sorting and selection algorithm
combined with an open-loop controller [20], [21] employed for
dc–ac MMC can only guarantee the SM capacitor voltage bal- Fig. 1. Circuit diagram of an M -phase-leg dc MMC.
ancing within the same arm. To maintain the average voltage
of the SM capacitors of the upper and lower arms balanced in
each phase-leg of the dc MMC, a closed-loop control strategy voltage-side dc-link current combined with an inner-loop power
is required. balance controller to maintain the power balance of the upper
Operation of bipolar and unipolar dc MMCs has been in- and lower arms. A current control strategy is chosen to achieve
vestigated in [19], [22]–[25]. A dc MMC topology utilizing a quick and smooth changes in power transfer between the inter-
capacitive filter is proposed in [26]. The dynamic model of the connected dc grids. The proposed control strategy guarantees
dc MMC is presented in [27], [28]. A systematic framework of proper bidirectional operation of the dc MMC. Performance
designing the dc MMC is proposed in [29]. An ac circulating and effectiveness of the proposed control strategy are evalu-
current control strategy to maintain the power balance between ated based on simulation studies in the MATLAB Simulink. A
the upper and lower arms of each phase-leg of the dc MMC laboratory prototype is developed and built to experimentally
has been proposed in [19]. This control strategy preserves the validate the proposed control strategy.
amplitude of the ac voltage component of the upper arm and
actively controls the ac voltage component of the lower arm II. DC MMC
such that the power balance between the upper and lower arms
remains maintained and the phase angle of the circulating cur- A. Basics of Operation
rent is in phase with the upper arm ac voltage. The open-loop The circuit diagram of an M-phase-leg dc MMC is shown
control strategy proposed in [19] guarantees power balance of in Fig. 1, in which the dc-link 2 voltage Vdc2 is larger than the
the upper and lower arms. Nevertheless, it does not minimize the dc-link 1 voltage Vdc1 . The dc MMC consists of two arms per
ac circulating current since the minimum ac circulating current phase-leg, i.e., an upper arm (represented by superscript “p”) and
is not necessarily always in phase with the upper arm ac volt- a lower arm (represented by superscript “n”). Each arm consists
age. Kish and Lehn [25] propose an improved open-loop control of series connection of N nominally identical half-bridge SMs
strategy that achieves minimized ac circulating current by arbi- and an arm inductor L. The output terminal/midpoint of each
trarily splitting VAR generation between the upper and lower phase-leg is connected to the converter dc-link 1 terminal via
arms. However, this control strategy requires tuning of weight- the phase filtering inductor Lo . To facilitate effective active ac
ing parameters for different voltage conversion ratios and power power transfer between the upper and lower arms, Lo should be
throughput to achieve minimized ac circulating current. sufficiently large such that the ripple component of the phase
This paper proposes a closed-loop control strategy for the currents becomes negligible. In practice, coupled inductors will
dc MMC to simultaneously regulate the output dc-link volt- be installed to filter out the ac current components and to ensure
age/current, maintain the SM capacitor voltages balanced, and cancellation of the dc flux in the inductor core [19].
minimize the ac circulating current for arbitrary voltage conver- Each SM of the dc MMC of Fig. 1 can provide two voltage
sion ratio and power throughput. The control strategy consists levels across its output terminal, i.e., zero or vCxi,j , x ∈ {p, n};
of an outer-loop dc-link current controller to regulate the low- i ∈ {1, 2, ..., N }; j ∈ {1, 2, ..., M }, depending on the states of

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 958 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 2, FEBRUARY 2017

Fig. 3. Maximum attainable amplitude of the ac components of the arm

voltages versus the voltage conversion ratio.

3) The capacitor voltages of the SMs within the same arm

are maintained balanced by an active capacitor voltage
sorting and selection algorithm.
Fig. 2. Equivalent circuit of one phase-leg of the dc MMC. In the analysis presented in this paper, the voltage conversion
ratio is defined as D = VV dc1
dc2
and the converter power throughput
is defined as P = Vdc1 Idc1 , which is considered positive when
power flows from dc-link 1 to dc-link 2.
its complementary switches Sxi1,j and Sxi2,j . The two switch-
For proper operation of the converter, the following
ing states of SM-i in the x arm of phase-leg j are
constraints must be satisfied:
1) Sxi1,j = 1 and Sxi2,j = 0: ON-state or inserted,
1) the half-bridge SM can only insert a positive voltage in
2) Sxi1,j = 0 and Sxi2,j = 1: OFF-state or bypassed.
the ON-state, thus the instantaneous arm voltage must be greater
The number of phase legs of the dc MMC is chosen based
than zero, and 2) the maximum instantaneous arm voltage must
on the power rating requirement. For high-power applications,
be smaller than the dc-link 2 voltage.
multiple phase legs are required to increase the power rating
Therefore, the maximum amplitudes of the ac component of
of the converter. For the case of M = 1, a series LC filter is
the upper and lower arm voltages are determined by
inserted to establish a path for the ac circulating current [22].
p p p
For the case of M > 1, the phase legs operate in an interleaved |ṽac |m ax = Min[vdc , (Vdc2 − vdc )], (1)
manner, i.e., the gating signals among phase legs are identical n n n
|ṽac |m ax = Min[vdc , (Vdc2 − vdc )]. (2)
with a phase shift of 2π
M .
By controlling the switching states of the SMs, each arm Fig. 3 shows the maximum attainable amplitude of the ac
generates an ac and a dc voltage component. The dc voltage component of the upper and lower arm voltages versus D. As
component drives a dc current to bidirectionally transfer dc shown in Fig. 3, the ac components of the voltages of the upper
power between the dc links 1 and 2. The ac voltage component and lower arms have the same maximum attainable value for a
p n
drives an ac circulating current to exchange active ac power given D. |ṽac |m ax and |ṽac |m ax reach the maximum at D = 0.5.
p
between the upper and lower arms. The frequency of the arm As the conversion ratio moves away from 0.5, |ṽac |m ax and
ac voltages ω, which hereafter is referred as the operating n
|ṽac |m ax decrease linearly in both directions.
frequency, is a design/control parameter of the converter and By assuming a lossless conversion, the upper and lower arm
can be chosen arbitrarily. voltages can be represented by
v p = Vdc2 − Vdc1 + ṽac
p
, (3)
B. Mathematical Model n n
v = Vdc1 + ṽac . (4)
An equivalent circuit representing one phase-leg of the dc
MMC is shown in Fig. 2. In the equivalent circuit, the phase-leg Based on the superposition principle, the converter phase-leg
number is omitted for the sake of simplicity and the following equivalent circuit can be decomposed into dc and ac subcircuits.
assumptions are made. The upper and lower arm currents are derived based on the
1) The number of SMs of each arm is sufficiently large analysis of the dc and ac subcircuits [29]
x
such that ṽac and ĩxac only contain fundamental frequency Idc2 p
(XL + XL o )ṽac n
+ XL o ṽac
ip = − − , (5)
components. M j(XL2 + 2XL XL o )
2) The phase legs are identical such that the power   n p
n Idc2 Vdc2 (XL + XL o )ṽac + XL o ṽac
throughput of the converter is equally shared among i = −1 − . (6)
them. M Vdc1 j(XL2 + 2XL XL o )

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 YANG AND SAEEDIFARD: CAPACITOR VOLTAGE BALANCING STRATEGY WITH MINIMIZED AC CIRCULATING CURRENT FOR THE DC–DC MMC 959

C. SM Capacitor Voltage Balancing

The SM capacitor voltages need to be maintained balanced.
Two types of SM capacitor voltage imbalances exist:
1) Type I: the imbalance among the SM capacitor voltages
in the same arm;
2) Type II: the deviation of average SM capacitor voltages
between the upper and lower arms.
Type I imbalance, which also exists in the conventional dc–ac
MMC, is due to unequal charge/discharge of the SM capacitors
in the same arm. Extensive research effort has been made to
mitigate Type I imbalance. The most common method of miti-
gating Type I imbalance is the selection method that sorts and
selects SMs to be inserted/bypassed based on the arm current
direction [30].
In contrast, Type II imbalance that is caused by dc power
transfer between the dc links is unique to the dc MMC [25]. As
shown in Fig. 2, the dc power can be transfered bidirectionally
between the dc links. The energy stored in the SM capacitors
will quickly deplete in one arm and saturate in the other arm of
the same phase-leg, if each arm produces only a dc current. Con-
sequently, the average voltage of SM capacitors of the upper and
lower arms will deviate from the nominal value even though the
voltages of SM capacitors are maintained balanced within the Fig. 4. Impact of φ on (a) the amplitude of the arm voltages ac
same arm. To mitigate Type II imbalance, the dc MMC exploits component and (b) the ac circulating current for various D.
an ac circulating current to enable active ac power exchange
between the upper and lower arms and to offset the voltage de-
viation of the SM capacitors caused by the dc power transfer.
in the upper and lower arms. To control the arm active ac power,
The ac circulating current needs to be actively controlled to p n
ṽac , ṽac , and φ are controlled to inject an ac circulating current.
maintain the average capacitor voltages of the upper and lower
Based on (9), two control strategies can be applied to maintain
arms at the nominal value.
the power balance of each arm:
Under steady state, each arm produces an ac voltage to drive p n
1) Strategy 1: maintain φ constant and change |ṽac | and |ṽac |
active ac power and a dc voltage to drive dc power. The dc power
to accommodate changes in Vdc1 , Vdc2 , and P ;
of the upper and lower arms can be represented by p n
  2) Strategy 2: maintain |ṽac | and |ṽac | constants and change
p Vdc1 P φ to accommodate changes in Vdc1 , Vdc2 , and P .
Pdc = −1 , (7a)
Vdc2 M Both strategies are equally valid in maintaining the average
n p SM capacitor voltages balance of the arms. Nevertheless, Strat-
Pdc = −Pdc . (7b)
egy 2 is preferred for two reasons: 1) it is capable of minimizing
p n
The active ac power of the upper and lower arms are the injected ac circulating current by maintaining |ṽac | and |ṽac |
represented by at their maximum attainable values and 2) it avoids overmodula-
XL o tion by maintaining the peak value of arm voltages at constants.
p
Pac = |ṽ p ||ṽ n |sin(φ), (8a) From the power loss, device rating and cost perspectives, it is
(XL2 + 2XL XL o ) ac ac
essential to minimize the amplitude of the injected ac circulating
n p p n
Pac = −Pac . (8b) current. Fig. 4 illustrates the impact of φ on |ṽac |, |ṽac |, and the
ac circulating current. In Fig. 4, it is assumed that a positive 1
To maintain the power balance of the upper and lower arms
p.u. power is transferred. Based on Fig. 4, four important facts
such that the deviation of the average capacitor voltages between
are revealed, which are as follows:
the upper and lower arms is minimized, the sum of dc and active p n
1) required |ṽac | and |ṽac | to maintain the power balance is
ac powers of each arm must be equal to zero. By equating the
symmetric with respect to φ = π2 ;
arm dc and active ac powers, the power balance constraint is p n
2) required |ṽac | and |ṽac | increase as φ deviates from
represented as π
  2 in both directions and reach the maximum as φ
Vdc1 P XL o approaches 0 or π for various D;
−1 + |ṽ p ||ṽ n |sin(φ) = 0.
Vdc2 M (XL2 + 2XL XL o ) ac ac 3) amplitude of the ac circulating current to maintain the
(9) power balance decreases as φ increases and reaches the
x x
As shown in (7), the arm dc power is fixed by external vari- minimum at |ṽac | = |ṽac |m ax , x ∈ {p, n} for various D;
ables, i.e., Vdc1 , Vdc2 , and P . To satisfy (9), the arm active ac 4) required φ to drive the minimum ac circulating
power should be actively controlled to track the arm dc power current is different for various D.

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 960 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 2, FEBRUARY 2017

Consequently, for P > 0, to minimize the ac circulating current

while maintaining the power balance between the upper and
lower arm for various D, two conditions should be satisfied:
1) The converter operates in the region of φ ∈ [ π2 , π).
p n
2) |ṽac | and |ṽac | are maintained at their maximum attain-
able values, which are determined based on (1) and (2)
for various D.
Similarly, for P < 0, the converter should operate in the re-
gion of φ ∈ (π, 3π 2 ]. This analysis implies that Strategy 2 is
the preferred control strategy for the dc MMC as it can always
p n
maintain |ṽac | and |ṽac | at their maximum attainable values,
regardless of P and D. In contrast, although Strategy 1 can
also maintain the power balance of the arms, it lacks the abil-
ity to minimize the ac circulating current. As P changes, the
required φ to inject the minimized ac circulating current also
varies. Consequently, maintaining φ at a constant value does
not always produce the minimized ac circulating current.

III. PROPOSED CLOSED-LOOP CONTROL STRATEGY

The proposed closed-loop control strategy for the dc MMC
involves three tasks, which are as follows:
1) minimization of the voltage divergence between the SM
capacitors of the upper and lower arms;
2) minimization of the ac circulating current required to
maintain power balance of the upper and lower arms; and
3) regulation of dc-link 1 current. The modulation signals for Fig. 5. Overall block diagram of the proposed closed-loop control
the upper and lower arms of each phase-leg are expressed by strategy.

p,ref
v p,ref = vdc p,ref
+ |ṽac |cos(ωt + φref ),
n ,ref n ,ref n ,ref
v = vdc + |ṽac |cos(ωt).
Fig. 5 shows the overall block diagram of the proposed con-
trol strategy that consists of a dc-link current regulator combined
p,ref n ,ref
with an arm power balance controller. vdc and vdc are gen-
p,ref n ,ref
erated by the dc-link current regulator while |ṽac |, |ṽac
φref are generated by the arm power balance controller to main-
tain the SM capacitor voltages balanced. The control strategy
shown in Fig. 5 is designed for interconnecting two dc power
grids. Consequently, dc-link current regulation is applied as the
outer-loop controller to achieve a fast and smooth control in the
power throughput of the converter. Nevertheless, the outer-loop
dc-link current regulator can be replaced by a dc-link voltage
regulator in applications where voltage regulation is more de-
sired. Since the proposed control strategy controls the phase
current of each phase-leg independently, it can be easily scaled
up for an arbitrary number of phase legs. In case of M > 1,
the dc-link current is equally split amongst M phase legs. One
additional advantage of the proposed control strategy is that the
core saturation of the coupled inductor is avoided by ensuring
effective dc flux cancellation.
To regulate the dc-link current at its reference value, the
dc-link current regulator employs a proportional-integral (PI)
controller that acts on the difference between the reference and
n ,ref
measured io generating vdc to facilitate bidirectional dc power
p,ref n ,ref
transfer. vdc is determined by subtracting vdc from Vdc2 to
p n
satisfy the KVL in the dc loop formed by Vdc2 , vdc , and vdc
(10)
As shown in Fig. 5, the arm power balance controller main-
(11) tains the power balance between the upper and lower arms such
that the deviation of the average SM capacitor voltages is min-
imized. To this end, a voltage error is generated by comparing
the average of the sum of the SM capacitor voltages between
the upper and lower arms. This error indicates the magnitude of
|, and Type II imbalance between the upper and lower arms. Since the
ripple component of each SM capacitor voltage in a dc MMC
mainly consists of fundamental and second-order harmonic fre-
quency terms, two notch filters are utilized to remove the ripple
components from the measured sum of SM capacitor voltage.
A PI controller acts on the error to generate φref that drives an
active ac power to minimize the deviation of the SM capacitor
voltages of the upper and lower arms.
p,ref n ,ref
To minimize the ac circulating current, vdc and vdc gener-
ated by the dc-link current regulator are substituted into (1)
p n
and (2) to determine |ṽac |m ax and |ṽac |m ax . The maximum
attainable ac components of the arm voltages are applied by
the power balance controller, such that |ṽac p,ref p
| = |ṽac |m ax and
n ,ref n
|ṽac | = |ṽac |m ax . In this way, the maximum attainable values
p n
of |ṽac | and |ṽac | are always applied for arbitrary D and P .
Fig. 6 demonstrates P versus φ for various D. In Fig. 6, it is
assumed that the maximum attainable arm voltages are applied
to achieve minimized ac current. Based on the commanded P
(by controlling Idc1 ref
), a unique φ is required to maintain the
power balance of the upper and lower arms. As shown in Fig. 6,
the dc MMC operates in the region of φ ∈ [ π2 , π) for P > 0 and
. in the region of φ ∈ (π, 3π 2 ] for P < 0. The maximum positive

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 YANG AND SAEEDIFARD: CAPACITOR VOLTAGE BALANCING STRATEGY WITH MINIMIZED AC CIRCULATING CURRENT FOR THE DC–DC MMC 961

Fig. 6. Normalized converter power throughput versus φ.

TABLE I
PARAMETERS OF THE STUDY SYSTEM

Converter Parameters Value

Number of phase legs, M 2

Number of SMs per arm, N 4
SM capacitor, C S M 4.2 mF
Arm inductor, L 0.8 mH
Phase filtering inductor, L o 260 mH
Operating frequency, ω 360 Hz
Rated power throughput, |P | 5 MW
DC-link 1 voltage, V dc1 5.28 kV
DC-link 2 voltage, V dc2 8.8 kV
Control Parameters Value
Proportional gain of the current regulator 2
Integral gain of the current regulator 150
Proportional gain of the power balance controller 0.6
Integral gain of the power balance controller 8

Fig. 7. Simulated converter waveforms : (a) dc links 1 and 2 voltages,

power is delivered at φ = π2 , while the maximum negative power
is delivered at φ = 3π 2 . It should be noted that, due to the fact that
p n
|ṽac |m ax and |ṽac |m ax are reduced as D increases, the maximum
P decreases as D increases.
IV. SIMULATION RESULTS
To demonstrate performance and effectiveness of the pro-
posed control strategy, a two-phase-leg dc MMC is simulated
in the MATLAB Simulink. The parameters of the study system
are listed in Table I.
The low-voltage and high-voltage sides of the dc MMC are
modeled by two voltage sources to mimic interconnection of
two dc grids at different voltage levels. The converter operates
at D = 0.6 and is controlled to exchange commanded power
between its two dc links. The SPWM strategy in conjunction
with the sorting algorithm is adopted to generate the gating sig-
nals while maintaining the voltage balance of the SM capacitors
within the same arm.
The simulated waveforms for the study system are shown in
Fig. 7. Initially, the dc MMC system of Fig. 1 is in steady state
and Idc1
ref
is set to −0.95 kA such that P = −5 MW is transferred.
As shown in Fig. 7(b), at t = 0.03 s, Idc1 is ramped up from
−0.95 to +0.95 kA within 20 ms. This change corresponds to
a power flow reversal from −5 to 5 MW from dc-link 1 to
dc-link 2.
(b) dc links 1 and 2 currents, (c) SM capacitor voltages of the upper and
lower arms of phase legs 1 and 2, (d) arm currents of phase legs 1 and 2,
(e) arm voltage reference of phase-leg 1, and (f) arm voltage reference
of phase-leg 2.
Fig. 7(c) illustrates the SM capacitor voltages of both phase
legs. The average voltages of the SM capacitor are maintained
balanced under steady state. As the dc power command changes,
the active ac power of the upper and lower arms required to
maintain the SM capacitor voltage balancing also changes. Con-
sequently, subsequent to the power flow reversal command, the
average voltages of the SMs in the upper and lower arms diverge
from each other. This deviation caused by the sudden change of
the dc power flow is quickly mitigated by the arm power bal-
ance controller within less than 40 ms as shown in Fig. 7(c). It
should be noted that the magnitude of the SM capacitor voltage
ripple is a function of D. Consequently, the ripple magnitude of
the SM capacitor voltages varies as P changes due to the fact
that the voltage conversion ratio of the dc MMC is adjusted to
accommodate the change in P.
Figs. 7(e) and (f) illustrate the reference voltages of the upper
and lower arms of phase legs 1 and 2, respectively, in which
the actions of the closed-loop controller is demonstrated. The
controller performs the following functions.
1) The dc components of v p,ref and v n ,ref are controlled to
regulate Idc1 . Between t = 0 s and t = 0.03 s when the

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 962 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 2, FEBRUARY 2017
Fig. 8. Simulated converter waveforms using the proposed control
strategy: (a) dc links 1 and 2 voltages, (b) dc links 1 and 2 currents,
(c) SM capacitor voltages of the upper and lower arms of phase legs 1
and 2, (d) arm currents of phase legs 1 and 2, (e) arm voltage reference
of phase-leg 1, and (f) arm voltage reference of phase-leg 2.
converter operates in steady state and P = −5 MW, the
dc component of v n ,ref is greater than Vdc1 to facilitate
negative power flow. After t = 0.03 s when the direction
of Idc1
ref
is reversed, the dc component of v n ,ref is reduced
to reverse the direction of Idc1 as shown in Fig. 7(e)
and (f). The dc-link currents are well regulated by the
closed-loop control strategy as illustrated in Fig. 7(b).
2) The amplitude of the ac components of v p,ref and v n ,ref are
maintained at their maximum values. As demonstrated in
Fig. 7(e) and (f), the peak voltages of the upper arms
are maintained at 8.8 kV while the minimum voltage of
the lower arms is maintained at 0 V. Consequently, the
magnitude of the ac circulating current is minimized as
demonstrated in Section II-C. It should be noted that since
the amplitudes of the arm voltages are maintained at their
maximum values, overmodulation of the arm voltages
is avoided regardless of the operating condition of the
converter.
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Fig. 9. Simulated converter waveforms using traditional control strat-
egy: (a) dc links 1 and 2 voltages, (b) dc links 1 and 2 currents, (c) SM
capacitor voltages of the upper and lower arms of phase legs 1 and 2,
(d) arm currents of phase legs 1 and 2, (e) arm voltage reference of
phase-leg 1, and (f) arm voltage reference of phase-leg 2.
3) φ is controlled to minimize capacitor voltage deviation of
the SM capacitors of the upper and lower arms. Between
t = 0 s and t = 0.03 s, the ac component of v p,ref leads
that of v n ,ref to facilitate active ac power flow from the
upper arm to the lower arm. φ is reduced during the
transient to accommodate the change of direction of P.
As the direction of P is reversed, the active ac power flow
between the arms is reversed as well. Once the converter
reaches steady state, the ac component of v p,ref lags that
of v p,ref to facilitate active ac power flow from the lower
arm to the upper arm.
The steady-state performance of the proposed control strategy
is compared with the traditional control strategy in which φref
is maintained at 3π 2 to maximize power transfer capability and
p,ref n ,ref
|ṽac | and |ṽac | are controlled to maintain the SM capacitor
voltages balanced. Figs. 8 and 9 present the simulated steady-
state waveforms of the dc MMC system using the proposed
and the traditional control strategies, respectively. Although
 YANG AND SAEEDIFARD: CAPACITOR VOLTAGE BALANCING STRATEGY WITH MINIMIZED AC CIRCULATING CURRENT FOR THE DC–DC MMC 963

TABLE II
PARAMETERS OF THE DC MMC PROTOTYPE

Converter Parameters Value

Number of phase legs, M 2

Number of SMs per arm, N 4
SM capacitor, C S M 2.6 mF
Arm inductor, L 2.2 mH
Phase filtering inductor, L o 400 mH
Operating frequency, ω 250 Hz
Rated power, P 5 kW
DC-link 1 voltage, V dc1 180 V
DC-link 2 voltage, V dc2 240 V
Switch model IXYS FII40-06D

Fig. 10. Experimental setup.

both control strategies enable the dc MMC system to transfer

−2.5 MW as shown in Figs. 8(b) and 9(b), the proposed control
strategy produces much less ac circulating currents as shown
in Figs. 8(d) and 9(d). The proposed control strategy produces
0.26 kA RMS current in the upper arm and 0.24 kA RMS current
in the lower arm. In contrast, the traditional control strategy pro-
duces 0.55 kA RMS current in the upper arm and 0.52 kA RMS
current in the lower arm. Compared to the traditional control
strategy, the proposed strategy reduces the arm RMS current by
around 50% in this case. In addition, compared to the traditional
control strategy, the SM capacitor voltage ripple produced by
the proposed control strategy is smaller, which is due to the
reduced ac circulating current.
The reduction in the ac circulating current stems from the fact
that the proposed control strategy applies the maximum attain-
able amplitude of the arm ac voltage, as depicted in Figs. 8(e)
and (f). In contrast, as shown in Figs. 9(e) and (f), since the
traditional control strategy maintains φref at 3π2 , only a portion
of the maximum attainable amplitude of the arm ac voltage is
utilized.
V. EXPERIMENTAL RESULTS
Performance of the proposed control strategy is experimen-
tally evaluated on a two-phase dc MMC, shown in Fig. 10.
The control strategy is implemented in the RT-Lab and OPAL-
RT rapid control prototyping tool with an integrated field-
programmable gate array. Fig. 11. Experimental waveforms of the dc MMC in boost mode of
operation for (a) power step-up and (b) power step-down scenarios.
A programmable dc electronic load that operates in constant
voltage mode is used to mimic a dc power grid with a constant
voltage. A programmable dc power supply is used to provide
is 60 V. Under boost mode of operation, the dc power supply
input power to the converter. The parameters of the prototype
is connected to dc-link 1 to provide constant voltage. The dc
are provided in Table II. The experiments include both buck and
electronic load is connected to dc-link 2 to sink power while
boost modes of operation to validate the bidirectional operation
maintaining a constant bus voltage.
of the dc MMC. In both modes of operation, the voltages of dc
The experimental waveforms for power step-up and step-
links 1 and 2 are maintained at 180 and 240 V, respectively.
down scenarios are shown in Figs. 11(a) and (b), respectively.
As shown in Fig. 11(a), initially, the dc MMC system is in
A. Boost Mode of Operation the steady state and Idc1
ref
is set to 3 A while P = 540 W is
The experimental waveforms of boost mode of operation are transferred from dc-link 1 to dc-link 2. At t = 100 ms, Idc1
ref
is
shown in Fig. 11, in which the nominal SM capacitor voltage changed to 5.5 A corresponding to 1 kW power throughput. To

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 964
Fig. 12. Experimental waveforms of the dc MMC in buck mode of
operation for (a) power step-up and (b) power step-down scenarios.
accommodate the step-up change of the dc-link 1 current, the
dc component of the lower arm voltage is reduced. Similar to
the simulation results illustrated in Section IV, the peak val-
ues of voltage references of both arms are maintained at their
maximums to minimize the ac circulating current. The SM ca-
pacitor voltages in the upper and lower arms are maintained
balanced by the closed-loop control strategy. It should be noted
that under boost mode of operation, φ is limited within the range
of [ π2 , π). Similarly, the experimental waveforms of the power
step-down test shown in Fig. 11(b) confirm that the proposed
control strategy is capable of controlling the converter power
throughput, maintaining the SM capacitor voltages balanced,
and minimizing the ac circulating current.
B. Buck Mode of Operation
The experimental waveforms of buck mode of operation that
include both power step-up and step-down scenarios are shown
in Fig. 12(a) and (b), respectively. In the power step-up sce-
nario, initially, Idc1
ref
is set at -3 A to transfer -540 W power.
At t = 100 ms, Idc1 ref
is changed to −5.5 A to facilitate the
power transfer of −1 kW as shown in Fig. 12(a). Similarly,
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 2, FEBRUARY 2017
in the power step-down scenario, a power step-down occurs at
t = 100 ms from −1 kW to −540 W. As demonstrated in Fig. 12,
in both scenarios, the capacitor voltages of the SMs of the up-
per and lower arms are maintained balanced. The ac circulating
current is minimized by maintaining the ac component of the
arm voltages at their maximums. The converter operates in the
region of φ ∈ (π, 3π
2 ] in buck mode of operation.
VI. CONCLUSION
In this paper, a closed-loop control strategy for the dc MMC
was proposed. The proposed control strategy guarantees proper
bidirectional operation of the converter in buck and boost modes
of operation. Simulation and experimental results confirm the
capability of the proposed control strategy to simultaneously
regulate the dc-link current, maintain the SM capacitor voltages
balanced, and minimize the ac circulating current.
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Heng Yang (S 10) received the Bachelor’s
degree in electrical engineering from Purdue
University, Indianapolis, IN, USA, in 2012. He
is currently working toward the Ph.D. degree
in the Department of Electrical and Computer
Engineering, Georgia Institute of Technology,
Atlanta, GA, USA.
His research interests include optimal de-
sign and control of power electronic sys-
tems and their applications in high-voltage dc
transmission.
Maryam Saeedifard (SM 11) received the
Ph.D. degree in electrical engineering from the
University of Toronto, Toronto, ON, Canada,
in 2008.
She is currently an Assistant Professor in
the School of Electrical and Computer Engi-
neering, Georgia Institute of Technology (Geor-
gia Tech), Atlanta, GA, USA. Prior joining Geor-
gia Tech, she was an Assistant Professor in
the School of Electrical and Computer En-
gineering, Purdue University, West Lafayette,
IN, USA. Her research interests include power electronics and
applications of power electronics in power systems.