National University of Computer and Emerging Sciences, Lahore Campus

Course: Computer Architecture Course Code: EE204

Program: BS(Computer Science) Semester: Spring 2018
Due Date: 20-02-2018 Total Marks: 80
Section: A, B Weight 3.3
Exam: Assignment 1 Page(s): 2

Note: Submit assignment in the hard farm during the class.

Q1: Number Representations (2+2+2+2+4) 12 marks

a) Convert (234.125)10 to Binary.

b) Write down 2’s complement signed representation of -115 using 8 bits

c) Perform the addition of following 8-bit signed binary numbers

i. 01110101
ii. 11011011

d) Perform the subtraction of following 8-bit signed binary numbers

01110101 – 11011011

e) The 8 bit registers, AR and BR initially have the following values.

AR = 10101010
BR = 11010000
Determine the 8 bit values in each register after the execution of the following sequence of
micro operations. Next instruction uses the result of previous instruction if the register is
same.
AR ← sar AR
BR ← rcl BR
BR←shl BR
AR←AR and BR

Q2: Convert the following to 32-bit IEEE 754 floating point representations.
(2+2+1+1+1+1) 8marks
i. 300.375
ii. -20.0
iii. +inf
iv. –inf
v. 0
vi. NAN
Q3: Bits have no inherent meaning. Given the bit patterns (2*(1+1+1+2)) 10 marks

a. 1010 1110 0000 1011 0000 0000 0000 0100

b. 1000 1101 0000 1000 0000 0000 0100 0000

What does these represent, assuming that they are

a. A two’s complement integer

b. An unsigned integer
c. A MIPS instruction
d. A single precision floating-point number in IEEE 754 format

Q4: Given the following values (10 marks)

A = (121)10 B = (13)10

a) Draw the circuit diagram of a 4-bit divider circuit. (Optimized version of the Divider)
b) Use your circuit in part (a) to compute A / B. Show the binary values of all the registers at
every step.

Q5: Design a 3-bit binary up and down counter with parallel load and synchronous clear. Make
Function table and draw the circuit diagram. (20 marks)

Q6: Design 2 bit Arithmetic Logic Shift Unit according to the given function table.
(20 marks)

Function Table for Arithmetic Logic Shift Unit

Operation Select
S0 S1 S2 S3 Cin Operation Function
0 0 0 0 X F = Ai XOR Bi XOR
0 0 0 1 X F = Ai’ Complement
0 0 1 0 X F = Ai NAND Bi NAND
0 0 1 1 X F = Ai NOR Bi NOR
0 1 0 0 0 F= Ai + Bi’ Subtract with borrow
0 1 0 0 1 F = Ai + Bi’ + 1 Subtract
0 1 0 1 0 F = Ai – 1 Decrement A
0 1 0 1 1 F = Ai Transfer A
0 1 1 0 0 F = Ai + Bi ADD
0 1 1 0 1 F = Ai Transfer A
0 1 1 1 0 F = Ai + 1 Increment A
0 1 1 1 1 F = Ai + Bi + 1 ADD with carry
1 0 X X X F = SAR Ai Shift Arithmetic Right A into F
1 1 X X X F = SAL Ai Shift Arithmetic left A into F