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+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
General Description ____________________________Features
MAX1112/MAX1113
The MAX1112/MAX1113 low-power, 8-bit, 8-channel ♦ 4.5V to 5.5V Single Supply
analog-to-digital converters (ADCs) feature an internal
track/hold, voltage reference, clock, and serial inter- ♦ Low Power: 135µA at 50ksps
face. They operate from a single 4.5V to 5.5V supply 13µA at 1ksps
and consume only 135µA while sampling at rates up to ♦ 8-Channel Single-Ended or 4-Channel Differential
50ksps. The MAX1112’s 8 analog inputs and the
Inputs (MAX1112)
MAX1113’s 4 analog inputs are software-configurable,
allowing unipolar/bipolar and single-ended/differential ♦ 4-Channel Single-Ended or 2-Channel Differential
operation. Inputs (MAX1113)
Successive-approximation conversions are performed ♦ Internal Track/Hold; 50kHz Sampling Rate
using either the internal clock or an external serial-inter-
face clock. The full-scale analog input range is deter- ♦ Internal 4.096V Reference
mined by the 4.096V internal reference, or by an ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface
externally applied reference ranging from 1V to VDD.
The 4-wire serial interface is compatible with the SPI™, ♦ Software-Configurable Unipolar or Bipolar Inputs
QSPI™, and MICROWIRE™ serial-interface standards. ♦ Total Unadjusted Error: ±1 LSB (max)
A serial-strobe output provides the end-of-conversion ±0.3 LSB (typ)
signal for interrupt-driven processors.
The MAX1112/MAX1113 have a software-program-
Ordering Information continued at end of data sheet.
mable, 2µA automatic power-down mode to minimize
power consumption. Using power-down, the supply
current is reduced to 13µA at 1ksps, and only 82µA at
10ksps. Power-down can also be controlled using the Functional Diagram
SHDN input pin. Accessing the serial interface automat-
ically powers up the device.
The MAX1112 is available in a 20-pin SSOP package. CS
The MAX1113 is available in a small 16-pin QSOP SCLK
*MAX1112 ONLY
Pin Configurations appear at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
MAX1112/MAX1113
ELECTRICAL CHARACTERISTICS
(VDD = 4.5V to 5.5V; unipolar input mode; VCOM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 8 Bits
Relative Accuracy (Note 1) INL ±0.1 ±0.5 LSB
Differential Nonlinearity DNL No missing codes over temperature ±1 LSB
Offset Error ±0.3 ±1 LSB
Gain Error (Note 2) Internal or external reference ±1 LSB
Gain Temperature Coefficient External reference, 4.096V ±0.8 ppm/°C
Total Unadjusted Error TUE ±0.3 ±1 LSB
Channel-to-Channel
±0.1 LSB
Offset Matching
DYNAMIC SPECIFICATIONS (10.034kHz sine-wave input, 4.096VP-P, 50ksps, 500kHz external clock)
Signal-to-Noise
SINAD 49 dB
and Distortion Ratio
Total Harmonic Distortion
THD -70 dB
(Up to the 5th Harmonic)
Spurious-Free Dynamic Range SFDR 68 dB
Channel-to-Channel Crosstalk VCH_ = 4.096VP-P, 25kHz (Note 3) -75 dB
Small-Signal Bandwidth -3dB rolloff 1.5 MHz
Full-Power Bandwidth 800 kHz
2 _______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4.5V to 5.5V; unipolar input mode; VCOM = 0V; fSCLK = 500kHz, external clock (50% duty cycle); 10 clocks/conversion cycle
(50ksps); 1µF capacitor at REFOUT; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CONVERSION RATE
Internal clock 25 55
Conversion Time (Note 4) tCONV µs
External clock, 500kHz, 10 clocks/conversion 20
Track/Hold Acquisition Time tACQ External clock, 2MHz 1 µs
Aperture Delay 10 ns
Aperture Jitter < 50 ps
Internal Clock Frequency 400 kHz
(Note 5) 50 500 kHz
External Clock-Frequency Range
Used for data transfer only 2 MHz
ANALOG INPUT
Unipolar input, VCOM = 0V 0 VREFIN
Input Voltage Range, Single-
COM ± V
Ended and Differential (Note 6) Bipolar input, VCOM = VREFIN/2
VREFIN/2
Multiplexer Leakage Current On/off leakage current, VCH_ = 0V or VDD ±0.01 ±1 µA
Input Capacitance 18 pF
INTERNAL REFERENCE
REFOUT Voltage 3.936 4.096 4.256 V
REFOUT Short-Circuit Current 6 mA
REFOUT Temperature Coefficient ±50 ppm/°C
Load Regulation (Note 7) 0 to 0.5mA output load 4.5 mV
Capacitive Bypass at REFOUT 1 µF
EXTERNAL REFERENCE AT REFIN
VDD +
Input Voltage Range 1 V
50
Input Current (Note 8) 1 20 µA
POWER REQUIREMENTS
Supply Voltage VDD 4.5 5.5 V
Full-scale input Operating mode 135 250
CLOAD = 10pF Reference disabled 95 µA
Supply Current IDD µA
Software 2
Power-down
SHDN at DGND 3.2 10
Power-Supply Rejection VDD = 4.5V to 5.5V; external reference,
PSR ±0.4 ±4 mV
(Note 9) 4.096V; full-scale input
_______________________________________________________________________________________ 3
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
4 _______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
TIMING CHARACTERISTICS (Figures 8 and 9)
(VDD = 4.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Track/Hold Acquisition Time tACQ 1 µs
DIN to SCLK Setup tDS 100 ns
DIN to SCLK Hold tDH 0 ns
SCLK Fall to Output Data Valid tDO Figure 1, CLOAD = 100pF 20 200 ns
CS Fall to Output Enable tDV Figure 1, CLOAD = 100pF 240 ns
CS Rise to Output Disable tTR Figure 2, CLOAD = 100pF 240 ns
CS to SCLK Rise Setup tCSS 100 ns
CS to SCLK Rise Hold tCSH 0 ns
SCLK Pulse Width High tCH 200 ns
SCLK Pulse Width Low tCL 200 ns
SCLK Fall to SSTRB tSSTRB CLOAD = 100pF 240 ns
CS Fall to SSTRB Output Enable Figure 1, external clock mode only,
tSDV 240 ns
(Note 5) CLOAD = 100pF
CS Rise to SSTRB Output Figure 2, external clock mode only,
tSTR 240 ns
Disable (Note 5) CLOAD = 100pF
SSTRB Rise to SCLK Rise
tSCK Figure 11, internal clock mode only 0 ns
(Note 5)
External reference 20 µs
Wakeup Time tWAKE
Internal reference (Note 10) 24 ms
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: VREFIN = 4.096V, offset nulled.
Note 3: On-channel grounded; sine wave applied to all off-channels.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: Guaranteed by design. Not subject to production testing.
Note 6: Common-mode range for the analog inputs is from AGND to VDD.
Note 7: External load should not change during the conversion for specified accuracy.
Note 8: External reference at 4.096V, full-scale input, 500kHz external clock.
Note 9: Measured as | VFS (4.5V) - VFS (5.5V) |.
Note 10: 1µF at REFOUT; internal reference settling to 0.5 LSB.
_______________________________________________________________________________________ 5
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
MAX1112/13-02
MAX1112/13-03
OUTPUT CODE = FULL SCALE MAX1112/13-01
SHDN = DGND
SHUTDOWN SUPPLY CURRENT (µA)
CLOAD = 10pF 0.2
8
160
SUPPLY CURRENT (µA)
0.1
VDD = 5.5V 6
DNL (LSB)
140 0
VDD = 4.5V 4
-0.1
120
2
-0.2
100 0 -0.3
-60 -20 20 60 100 140 -60 -20 20 60 100 140 0 64 128 192 256
TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL CODE
INTEGRAL NONLINEARITY
OFFSET ERROR vs. TEMPERATURE vs. CODE FFT PLOT
0.6 0.20 20
MAX1112/13-05
MAX1112/13-04
MAX1112/13-06
0.15 fCH_ = 10.034kHz, 4VP-P
0.5 0 fSAMPLE = 50ksps
0.10
OFFSET ERROR (LSB)
0.4 -20
AMPLITUDE (dB)
0.05
INL (LSB)
0.3 0 -40
-0.05
0.2 -60
-0.10
0.1 -80
-0.15
0 -0.20 -100
-60 -20 20 60 100 140 0 64 128 192 256 0 5 10 15 20 25
TEMPERATURE (°C) DIGITAL CODE FREQUENCY (kHz)
6 _______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Pin Description
MAX1112/MAX1113
PIN
NAME FUNCTION
MAX1112 MAX1113
1–4 1–4 CH0–CH3 Sampling Analog Inputs
5–8 — CH4–CH7 Sampling Analog Inputs
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode.
9 5 COM
Must be stable to ±0.5 LSB.
Three-Level Shutdown Input. Normally high impedance. Pulling SHDN low shuts the
10 6 SHDN MAX1112/MAX1113 down to 10µA (max) supply current; otherwise, the devices are
fully operational. Pulling SHDN high shuts down the internal reference.
Reference Voltage Input for Analog-to-Digital Conversion. Connect to REFOUT to use
11 7 REFIN
the internal reference.
12 8 REFOUT Internal Reference Generator Output. Bypass with a 1µF capacitor to AGND.
13 9 AGND Analog Ground
14 10 DGND Digital Ground
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when
15 11 DOUT
CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1112/
MAX1113 begin the A/D conversion and goes high when the conversion is complete.
16 12 SSTRB
In external clock mode, SSTRB pulses high for two clock periods before the MSB is
shifted out. High impedance when CS is high (external clock mode only).
17 13 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is
18 14 CS
high, DOUT is high impedance.
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode,
19 15 SCLK
SCLK also sets the conversion speed (duty cycle must be 45% to 55%).
Positive Supply Voltage, 4.5V to 5.5V. Bypass to AGND with 0.1µF and 1µF capacitor
20 16 VDD
as close as possible to the device. Place the 0.1µF capacitor closer to VP-P.
+5V +5V
3kΩ 3kΩ
DOUT DOUT DOUT DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
_______________________________________________________________________________________ 7
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
_______________Detailed Description acquisition interval spans two SCLK cycles and ends
MAX1112/MAX1113
on the falling SCLK edge after the last bit of the input
The MAX1112/MAX1113 analog-to-digital converters
control word has been entered. At the end of the acqui-
(ADCs) use a successive-approximation conversion
sition interval, the T/H switch opens, retaining charge
technique and input track/hold (T/H) circuitry to convert
on CHOLD as a sample of the signal at IN+.
an analog signal to an 8-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors The conversion interval begins with the input multiplex-
(µPs). Figure 3 shows the Typical Operating Circuit. er switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
Pseudo-Differential Input ply COM. This unbalances node ZERO at the input of
The sampling architecture of the ADC’s analog com- the comparator. The capacitive DAC adjusts during the
parator is illustrated in Figure 4, the equivalent input cir- remainder of the conversion cycle to restore node
cuit. In single-ended mode, IN+ is internally switched to ZERO to 0V within the limits of 8-bit resolution. This
the selected input channel, CH_, and IN- is switched to action is equivalent to transferring a charge of 18pF x
COM. In differential mode, IN+ and IN- are selected (VIN+ - VIN-) from CHOLD to the binary-weighted capac-
from the following pairs: CH0/CH1, CH2/CH3, itive DAC, which in turn forms a digital representation of
CH4/CH5, and CH6/CH7. Configure the MAX1112 the analog input signal.
channels with Table 1 and the MAX1113 channels with
Table 2. Track/Hold
The T/H enters its tracking mode on the falling clock
In differential mode, IN- and IN+ are internally switched
edge after the sixth bit of the 8-bit control byte has
to either of the analog inputs. This configuration is
been shifted in. It enters its hold mode on the falling
pseudo-differential to the effect that only the signal at
clock edge after the eighth bit of the control byte has
IN+ is sampled. The return side (IN-) must remain sta-
been shifted in. If the converter is set up for single-
ble within ±0.5 LSB (±0.1 LSB for best results) with
ended inputs, IN- is connected to COM, and the con-
respect to AGND during a conversion. To accomplish
verter samples the “+” input; if it is set up for differential
this, connect a 0.1µF capacitor from IN- (the selected
inputs, IN- connects to the “-” input, and the difference
analog input) to AGND if necessary.
(IN+ - IN-) is sampled. At the end of the conversion, the
During the acquisition interval, the channel selected as positive input connects back to IN+, and C HOLD
the positive input (IN+) charges capacitor CHOLD. The charges to the input signal.
8 _______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
Table 1a. MAX1112 Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0 0 0 + –
1 0 0 + –
0 0 1 + –
1 0 1 + –
0 1 0 + –
1 1 0 + –
0 1 1 + –
1 1 1 + –
_______________________________________________________________________________________ 9
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
The time required for the T/H to acquire an input signal age. However, for accurate conversions near full scale,
MAX1112/MAX1113
is a function of how quickly its input capacitance is the inputs must not exceed VDD by more than 50mV or
charged. If the input signal’s source impedance is high, be lower than AGND by 50mV.
the acquisition time lengthens, and more time must be If the analog input exceeds 50mV beyond the sup-
allowed between conversions. The acquisition time, plies, do not forward bias the protection diodes of
tACQ, is the minimum time needed for the signal to be off channels over 2mA.
acquired. It is calculated by:
The MAX1112/MAX1113 can be configured for differen-
tACQ = 6 x (RS + RIN) x 18pF tial or single-ended inputs with bits 2 and 3 of the con-
where RIN = 6.5kΩ, RS = the source impedance of the trol byte (Table 3). In single-ended mode, analog inputs
input signal, and tACQ is never less than 1µs. Note that are internally referenced to COM with a full-scale input
source impedances below 2.4kΩ do not significantly range from COM to VREFIN + COM. For bipolar opera-
affect the AC performance of the ADC. tion, set COM to VREFIN/2.
Input Bandwidth In differential mode, choosing unipolar mode sets the
The ADC’s input tracking circuitry has a 1.5MHz small- differential input range at 0V to V REFIN. In unipolar
signal bandwidth, so it is possible to digitize high- mode, the output code is invalid (code zero) when a
speed transient events and measure periodic signals negative differential input voltage is applied. Bipolar
with bandwidths exceeding the ADC’s sampling rate by mode sets the differential input range to ±VREFIN/2.
using undersampling techniques. To avoid high- Note that in this mode, the common-mode input range
frequency signals being aliased into the frequency includes both supply rails. See Table 4 for input voltage
band of interest, anti-alias filtering is recommended. ranges.
10 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
Table 4. Full-Scale and Zero-Scale Voltages
UNIPOLAR MODE BIPOLAR MODE
Positive Zero Negative
Full Scale Zero Scale
Full Scale Scale Full Scale
+VREFIN/2 -VREFIN/2
VREFIN + COM COM COM
+ COM + COM
in control bytes of $FF (hex), which trigger single- from DIN into the MAX1112/MAX1113’s internal shift reg-
ended, unipolar conversions on CH7 (MAX1112) or ister. After CS falls, the first arriving logic “1” bit at DIN
CH3 (MAX1113) in external clock mode without power- defines the MSB of the control byte. Until this first start bit
ing down between conversions. In external clock mode, arrives, any number of logic “0” bits can be clocked into
the SSTRB output pulses high for two clock periods DIN with no effect. Table 3 shows the control-byte format.
before the most significant bit (MSB) of the 8-bit con- The MAX1112/MAX1113 are compatible with
version result is shifted out of DOUT. Varying the ana- MICROWIRE, SPI, and QSPI devices. For SPI, select the
log input alters the output code. A total of 10 clock correct clock polarity and sampling edge in the SPI con-
cycles is required per conversion. All transitions of the trol registers: set CPOL = 0 and CPHA = 0. MICROWIRE,
SSTRB and DOUT outputs occur on SCLK’s falling SPI, and QSPI all transmit a byte and receive a byte at the
edge. same time. Using the Typical Operating Circuit (Figure 3),
How to Start a Conversion the simplest software interface requires three 8-bit trans-
A conversion is started by clocking a control byte into fers to perform a conversion (one 8-bit transfer to config-
DIN. With CS low, each rising edge on SCLK clocks a bit ure the ADC, and two more 8-bit transfers to clock out the
0.1µF 1µF
DGND
SCLK
MAX1112 AGND
SSTRB
0V TO MAX1113
+4.096V CH7 (CH3) CS
ANALOG 0.01µF DOUT*
INPUT
SCLK
REFOUT DOUT
______________________________________________________________________________________ 11
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
8-bit conversion result). Figure 6 shows the MAX1112/
MAX1112/MAX1113
b) QSPI
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
I/O CS 6) Pull CS high.
SK SCLK
Figure 7 shows the timing for this sequence. Bytes RB2
SI DOUT
and RB3 contain the result of the conversion padded
with two leading zeros and six trailing zeros. The total
conversion time is a function of the serial-clock
MAX1112
MAX1113
frequency and the amount of idle time between 8-bit
transfers. Make sure that the total conversion time does
c) MICROWIRE not exceed 1ms, to avoid excessive T/H droop.
CS
tACQ
1 4 8 12 16 20 24
SCLK
ACQUISITION
A/D STATE IDLE 4μs CONVERSION IDLE
(fSCLK = 500kHz)
12 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Digital Output conversion steps. SSTRB pulses high for two clock
MAX1112/MAX1113
In unipolar input mode, the output is straight binary periods after the last bit of the control byte. Successive-
(Figure 15). For bipolar inputs, the output is two’s-com- approximation bit decisions are made and appear at
plement (Figure 16). Data is clocked out at SCLK’s DOUT on each of the next eight SCLK falling edges
falling edge in MSB-first format. (Figure 7). After the eight data bits are clocked out,
subsequent clock pulses clock out zeros from the
Clock Modes DOUT pin.
The MAX1112/MAX1113 can use either an external ser-
ial clock or the internal clock to perform the successive- SSTRB and DOUT go into a high-impedance state
approximation conversion. In both clock modes, the when CS goes high; after the next CS falling edge,
external clock shifts data in and out of the devices. Bit SSTRB outputs a logic low. Figure 9 shows the SSTRB
PD0 of the control byte programs the clock mode. timing in external clock mode.
Figures 8–11 show the timing characteristics common The conversion must complete in 1ms, or droop on the
to both modes. sample-and-hold capacitors can degrade conversion
results. Use internal clock mode if the serial-clock fre-
External Clock quency is less than 50kHz, or if serial-clock interruptions
In external clock mode, the external clock not only could cause the conversion interval to exceed 1ms.
shifts data in and out, it also drives the analog-to-digital
CS
•••
SCLK •••
tDS
tDH
DIN •••
DOUT •••
CS
••• •••
tSDV tSTR
tSSTRB
tSSTRB
SCLK
•••• ••••
PD0 CLOCKED IN
______________________________________________________________________________________ 13
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
CS
1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18
SCLK
tCONV
FILLED WITH
DOUT B7 B6 B1 B0 ZEROS
CONVERSION
A/D STATE IDLE 25µs TYP IDLE
tACQ
4µs (fSCLK = 500kHz)
CS
tCONV tCSS
tCSH tSCK
SSTRB
tSSTRB
SCLK
PD0 CLOCK IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
14 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
CS
1 8 10 1 8 10 1 8 10 1
SCLK
DOUT B7 B0 B7 B0 B7
CONVERSION RESULT 0 CONVERSION RESULT 1 CONVERSION RESULT 2
SSTRB
CS
SCLK
DOUT B7 B0 B7
CONVERSION RESULT 0 CONVERSION RESULT 1
______________________________________________________________________________________ 15
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
__________Applications Information Hard-Wired Power-Down
MAX1112/MAX1113
MAX1112/13-fig13
power down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion CLOAD = 60pF
results can be clocked out after the MAX1112/ CODE = 10101010
SUPPLY CURRENT (μA)
VDD = VREFIN = 5V
Table 5. Hard-Wired Power-Down and CLOAD AT DOUT + SSTRB
Internal Reference State 10
0 10 20 30 40 50
SHDN DEVICE INTERNAL SAMPLING RATE (ksps)
STATE MODE REFERENCE
1 Enabled Disabled
High Impedance Enabled Enabled
Figure 13. Average Supply Current vs. Sampling Rate
0 Power-Down Disabled
16 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
CLOCK INTERNAL EXTERNAL EXTERNAL
MODE
SHDN
SETS EXTERNAL SETS POWER- SETS EXTERNAL
CLOCK MODE DOWN MODE CLOCK MODE
S X X X X X 1 1 S X X X X X 0 1 S X X X X X 1 1
DIN
S X X X X X 1 0 S X X X X X 0 0 S
DIN
SSTRB
CONVERSION CONVERSION
______________________________________________________________________________________ 17
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
MAX1112/MAX1113
OUTPUT CODE
FULL-SCALE
TRANSITION SUPPLIES
11111111
11111110
+5V GND
11111101
00000011
VDD AGND DGND +5V DGND
00000010
00000001
00000000 DIGITAL
MAX1112
CIRCUITRY
0 1 2 3 FS MAX1113
(COM) INPUT VOLTAGE (LSB) FS - 1 LSB *OPTIONAL
Figure 15. Unipolar Transfer Function Figure 17. Power-Supply Grounding Connections
18 ______________________________________________________________________________________
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Pin Configurations
MAX1112/MAX1113
TOP VIEW
CH0 1 20 VDD
CH1 2 19 SCLK CH0 1 16 VDD
CH2 3 18 CS CH1 2 15 SCLK
CH3 4 17 DIN CH2 3 14 CS
CH4 5 MAX1112 16 SSTRB CH3 4 MAX1113 13 DIN
SHDN 10 11 REFIN
QSOP
SSOP
______________________________________________________________________________________ 19
+5V, Low-Power, Multi-Channel,
Serial 8-Bit ADCs
Revision History
MAX1112/MAX1113
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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