ES2C0 ANALOGUE SYSTEM DESIGN – ASSIGNMENT DRAFT

School of Engineering

ES2C0 Analogue Electronic Design

LABORATORY WORKBOOK

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Experiment 1 Measuring the I-V characteristics of a Zener diode
E1.1 What forward and reverse breakdown voltages did you measure for your Zener diode? Show your plots of the 9
forward and reverse bias I-V characteristics for your Zener diode.
-Zener (reverse) voltage range is typically 1.8V to 9.0V (at 5.0mA ±0.25mA).
- Zener (reverse) voltage higher than 7.0V may be tested at a lower test current.
- Zener voltage accuracy is typically ±1% ±0.006V.
- Forward voltage drop is tested at a current of 5.0mA ±0.25mA.
- Forward voltage drop accuracy is typically ±1% ±0.006V.
- High power Zener diodes (>1W) will require a higher current to obtain the rated reverse voltage. Therefore high
power Zener diodes may yield a lower Zener voltage at the test current used by the DCA Pro.

E1.2 What current through and voltage across did you measure for your Zener diode with Vs = 20 V? 4

Current across the Zener diode is 15.40mA, V2=4.66V for Vs=20V

E1.3 Show your plot of the current through and voltage across your Zener as a function of Vs on a single graph 6
with voltage scale [0 – 5] V.

E1.4 Show how you calculated your circuit’s line regulation? 4

∆𝑽𝒐𝒖𝒕
∆𝑽𝒊𝒏
x 100%

Picking two points from Vout (Vz) and Vin (Vs) respectively:
𝟒. 𝟓𝟖 − 𝟒. 𝟐𝟑
× 𝟏𝟎𝟎% = 𝟓%
𝟏𝟑 − 𝟔
 E1.5 Show your plot of output voltage as a function of load current. Show how you calculated your circuit’s 7
load regulation?

Voltage Regulation:
𝑽𝒐𝒖𝒕(𝟓𝟎𝒌Ω) − 𝑽𝒐𝒖𝒕(𝟓𝟎𝟎Ω)
× 𝟏𝟎𝟎%
𝑽𝒐𝒖𝒕(𝟓𝟎𝟎Ω)
𝟒.𝟓𝟏−𝟑.𝟑𝟎
× 𝟏𝟎𝟎% = 𝟑𝟔. 𝟔𝟕%
𝟑.𝟑𝟎

Experiment 2 Integrated Circuit voltage regulator LM317

E2.1 What output voltage did you measure on LM317 output pin? 2
Vin=20V , Vout=5.95V

E2.2 Show your plot of the output voltage 𝑉𝑜𝑢𝑡 as a function of the input voltage 𝑉𝑖𝑛 . 4

E2.3 What is the minimum drop-out voltage for LM317. Compare with modern LDO regulator. 4
The minimum drop-out voltage for LM317 is 3V. A modern LDO regulator has a minimum drop-out voltage
of range around 100mV to 200mV: Dropout voltages at rated load are approximately 150 mV for the
ADP1710 and ADP1711; and 170 mV for the ADP1712, ADP1713, and ADP1714.

Experiment 3 Sine wave oscillator

E3.2 Display saved output waveform. Describe waveform shape. What is the peak to peak amplitude? What 7
is the frequency?

The display saved output waveform is shown below.

 The frequency is 943.608Hz
The waveform is not perfectly sinusoidal, it has a slight square shape at maximum and minimum points.

E3.3 What was the measured value of the potentiometer resistance? 2

19.34kΩ

E3.4 Show how you calculated the expected frequency of oscillation and compare with the measured 6
frequency of oscillation.

The formula used is:

Using the formula above and the following parameters:

C=47µ𝑭, R=3.9kΩ
𝟏
𝒇𝟎 = = 𝟎. 𝟖𝟔𝟑𝒌𝑯𝒛
𝟐𝝅(𝟒𝟕µ𝑭)(𝟑. 𝟗𝒌Ω)
The measured frequency of oscillation is 943.608z while theoretical value is 0.863kHz

E3.5 Show how you calculated the non-inverting gain of the circuit. 3
𝑹𝒇 𝟏𝟗.𝟑𝟒𝒌Ω
Non inverting gain= 1 + 𝑹𝒔
= 1+ 𝟏𝟎𝒌Ω = 2.934

Experiment 4 A square wave oscillator

E4.1 Show how you calculated the expected frequency of oscillation. Display saved output waveform. What 10
is the frequency? What is the rise time? Compare theoretical and measured frequencies. How good is your
square wave output?

𝟏 𝟏
𝑓 = 𝟐.𝟐𝑹𝑪 = 𝟐.𝟐(𝟒.𝟕×𝟏𝟎𝟎𝟎)(𝟒𝟕×𝟏𝟎−𝟗 ) = 𝟐𝟎𝟓𝟕. 𝟕𝑯𝒛 = 𝟐. 𝟎𝟓𝟕𝒌𝑯𝒛

Expected frequency of oscillation is 2.057kHz. And the output waveform is shown in the figure below.
The circuit rise time is 126.0µs and the frequency is 2.4888kHz

The theoretical and measured frequency of oscillations are not too big of a difference from each other
with only a 20.9% discrepancy as shown in the calculation below:
𝑨𝒄𝒕𝒖𝒂𝒍 − 𝑻𝒉𝒆𝒐𝒓𝒆𝒕𝒊𝒄𝒂𝒍 𝟐. 𝟒𝟖𝟖 − 𝟐. 𝟎𝟓𝟕
× 𝟏𝟎𝟎% = × 𝟏𝟎𝟎% = 𝟐𝟎. 𝟗𝟓%
𝑻𝒉𝒆𝒐𝒓𝒆𝒕𝒊𝒄𝒂𝒍 𝟐. 𝟎𝟓𝟕

The square wave output is not perfectly square, slightly triangular.

E4.3 Display saved output waveform. What is the frequency? What is the rise time? Compare theoretical 8
and measured frequencies. How good is your square wave output?

𝟏 𝟏
𝑓 = 𝟐.𝟐𝑹𝑪 = 𝟐.𝟐(𝟒.𝟕×𝟏𝟎𝟎𝟎)(𝟒𝟕×𝟏𝟎−𝟗 ) = 𝟐𝟎𝟓𝟕. 𝟕𝑯𝒛 = 𝟐. 𝟎𝟓𝟕𝒌𝑯𝒛

Expected frequency of oscillation is 2.057kHz. And the output waveform is shown in the figure below.

The circuit rise time is 152.0µs, the frequency is 3.345kHz

The square wave output is perfectly square.
The theoretical and measured frequency of oscillations differ much greatly now by a 62.6% discrepancy as
shown in the calculation below:
𝑨𝒄𝒕𝒖𝒂𝒍 − 𝑻𝒉𝒆𝒐𝒓𝒆𝒕𝒊𝒄𝒂𝒍 𝟑. 𝟑𝟒𝟓 − 𝟐. 𝟎𝟓𝟕
× 𝟏𝟎𝟎% = × 𝟏𝟎𝟎% = 𝟔𝟐. 𝟔%
𝑻𝒉𝒆𝒐𝒓𝒆𝒕𝒊𝒄𝒂𝒍 𝟐. 𝟎𝟓𝟕
 E4.4 Compare the rise times of the OP177 with that of the LF411. What do the datasheets say about the 4
respective slew rates?
The rise time of OP177(126.0µs) is lower than that of LF411(152.0µs). OP177 has a slew rate of
0.1V/µs(min) and 0.3V/µs(Typ) while LF411 has a high slew rate of 10V/µs(min).

Experiment 5 Operational amplifier as buffer.

E5.2 What was the maximum amplitude sinusoid that you could apply to the input? How is this related to 5
the op-amp’s power supplies?
The maximum amplitude sinusoid before distortion is 9.75V.
According to the datasheet, an opamp’s maximum power supply is 32V, minimum is 3V. All amplifiers has
a specified range of input voltage that allows it to produce a reasonable output. The power, voltage and
current gain calculated by the peak output/peak input. The opamp can only provided a limited gain hence
there is a limit to how much amplitude sinusoid could be applied before it is limited by supply voltage and
distorts.

Thus, too large of an input results in the output waveform signal to exceed the power supply voltage rails
with the top and bottom half parts of the waveform signal becoming clipped/flattened.

E5.3 Show scope traces of the input and output sinusoids that includes the measurement ribbon showing 4
pk-pk measurements for both channels. What happens to the output?

The output becomes distorted and not perfectly sinusoidal. The output has flat tops at the peak of the
sinusoid due to overdrive of the input amplitude as mentioned above, this reduces the efficiency of the
operational amplifier.

E5.4 What was the maximum input amplitude for the which the output was sinusoidal with a 100 kHz input? 4
Explain how this relates to the op amp’s slew rate.
Maximum input amplitude is 750mV.

The slew rate of an op amp or any amplifier circuit is the maximum rate of change in the output
voltage caused by a step change on the input.

The formula is given by Slew rate = 2 π f V

Thus, the higher the input amplitude, the higher the slew rate.
E5.5 With the input signal a.c. coupled, explain what happened to the sine wave output when the temporary 4
short-circuit was removed from across the capacitor.

At 2 V pk-pk, 1 kHz sinusoid:

The sine wave output decreased in the amplitude.

AC coupled with the input signal using a 10 nF capacitor:

The output signal experiences distortion.

Short-circuit was removed from across the capacitor:

 The distortion is no longer present in the sinusoidal
output waveform and the amplitude increased.

E5.6 What happens to the output sinusoid when a 100 kΩ resistor is connected between the non-inverting 2
terminal and ground?

The sinusoid output increases in its amplitude.

E5.8 Show your scope traces of the input and output sinusoids. Explain how the output has changed 4
compared with E5.7

5.7 5.8
The difference lies in the output which has become distorted in 5.8 while in 5.7 the output was similar to
the input.

E5.9 Show your scope traces (dc coupled) of the input and output sinusoids of your circuit solution. Explain 6
why your solution solves the problem encountered in E5.8.
Unable to complete due to COVID-19 Lab closure. A Multisim approach was used instead to answer this
question.

Proposed circuit:
 Changing the DC levels to +/- 3 and using a signal ground instead solved the issue as it was previously too
high causing over driving of the input signal that caused clipping of the output signals.

Experiment 6 Bipolar Junction Transistor (BJT) parameters

E6.1 Record the value of current gain 𝛽 for your device. Record the value of base-emitter volt-drop 𝑉𝐵𝐸 , and =5
measurement base current 𝐼𝐵 .
(i) Hfe(β)=173 at Ic= 5.00mA
(ii) 𝑽𝑩𝑬 =0.758V at 𝑰𝑩 =5.00mA
(iii) 𝑽𝑪𝑬 𝑺𝒂𝒕 = 𝟎. 𝟎𝟔𝟐𝑽 at Ic=5.0mA and 𝑰𝑩 = 𝟏. 𝟎𝟎𝒎𝑨

E6.2 Show how you calculated a value for the base resistor R1. 56
(i) Ic=5V/330Ω=0.0151A=15.15mA
𝟏𝟓.𝟏𝟓𝒎𝑨
(ii) 𝑰𝑩 = 𝟏𝟕𝟑 = 𝟎. 𝟎𝟖𝟕𝟓𝟕𝒎𝑨, 5x𝑰𝑩 =5(0.08757mA)=0.43785mA
Using Ohm’s law:
(Vcc-𝑽𝑩𝑬 )/ 𝑰𝑩 =R1
(5-0.758)/0.43785 = 9.688kΩ≈10kΩ

E6.3 State your measurements for the following: 10

(i)Collector current 𝑰𝑪 = 𝟏𝟒. 𝟔𝟑𝒎𝑨

(ii)Emitter current 𝑰𝑬 = 𝟏𝟒. 𝟔𝟑𝒎𝑨
(iii)Base current 𝑰𝑩 = 𝟎. 𝟒𝟏𝒎𝑨
(iv)Base-emitter voltage 𝑽𝑩𝑬 = 𝟎. 𝟕𝟔𝟕𝑽
(v)Collector-emitter voltage 𝑽𝑪𝑬 = 𝟎. 𝟏𝟐𝟕𝑽

E6.4 What value of current gain β did you calculate for your circuit? What value of base-emitter voltage did 6
you measure for your circuit? Account for any discrepancies with the values measured using the DCA Pro.
Calculated: β =14.63/0.41 =35.683
Base-emitter voltage 𝑽𝑩𝑬 = 𝟎. 𝟕𝟔𝟕𝑽
 There is power loss to the surroundings, there is error within the device (instrumental error), BJT
connected to the DCA Pro could also have some damaged to it from prolonged use/wear and tear thus the
measured and calculated value differed as the properties of the BJT were changed overtime.

E6.5 What voltage did you measure across the ‘load’ (collector) resistor? If not 5 V explain why. 5
It was not 5V. The voltage decreased because of noise in the circuit

E6.6 Show how you calculated a value for the base resistor R2. 5
Hfe(β)=222 at Ic= 5.00mA

𝑽𝑩𝑬 =0.777V at 𝑰𝑩 =5.00Ma

𝑽𝑪𝑬 𝑺𝒂𝒕 = 𝟎. 𝟎𝟓𝟎𝑽 at Ic=5.0mA and 𝑰𝑩 = 𝟏. 𝟎𝟎𝒎𝑨

Ic=5V/330Ω=0.0151A=15.15mA

𝟏𝟓.𝟏𝟓𝒎𝑨
𝑰𝑩 = 𝟐𝟐𝟐
= 𝟎. 𝟎𝟔𝟖𝟐𝟒𝒎𝑨, 5x𝑰𝑩 =5(0.06824mA)=0.34122mA

Using Ohm’s law:

(Vcc-𝑽𝑩𝑬 )/ 𝑰𝑩 =R2
R2=(5-0.777)/0.34122 = 12.376kΩ≈12kΩ

E6.7 State your measurements for the following: 10

(i)Collector current 𝑰𝑪 = 𝟏𝟒. 𝟗𝟖𝒎𝑨

(ii)Emitter current 𝑰𝑬 = 𝟔𝟎. 𝟕𝒎𝑨
(iii)Base current 𝑰𝑩 = 𝟎. 𝟑𝟒𝒎𝑨
(iv)Base-emitter voltage 𝑽𝑩𝑬 = 𝟎. 𝟔𝟐𝟕𝑽
(v)Collector-emitter voltage 𝑽𝑪𝑬 = 𝟎. 𝟏𝟐𝟑𝑽

E6.8 What value of current gain β did you calculate for your circuit? What value of base-emitter voltage did 6
you measure for your circuit? Account for any discrepancies with the values measured using the DCA Pro.
Β=14.98/0.34 =44.0588
Base-emitter voltage 𝑽𝑩𝑬 = 𝟎. 𝟔𝟐𝟕𝑽
There could have been instrumental error in the DCA Pro i.e probs not working as well due to wear and
tear or it is operating on an estimated/nearest value of measurement.

Experiment 7 Metal Oxide Semiconductor Field Effect Transistor (MOSFET) parameters

E7.1 What value of transconductance 𝑔𝑚 did you measure for your device? What was the value of the gate 6
‘turn-on’ voltage 𝑉𝐺𝑆(𝑜𝑛) (including measurement current value)?
Gm value=26.4mA/V at Id=3.0mA to 5.0mA
Vgs(on)=2.423V at Id=5.05mA and Ig=1µA
Vgs(off)=1.728V at Id=4.8µA
Rds(on)=1.5Ω at Id=5.0mA and Vgs=8.0V

E7.2 Explain why a MOSFET does not need a gate current limiting resistor. 3
MOSFETS do not have bases and their gates have very high impedance. Thus you do not need a gate
current limiting resistor.
 E7.3 For a drain current 𝐼𝐷 = 5 mA what was the value of 𝑉𝐺𝑆 ? Compare with values measured using DCA 4
Pro Analyzer.
Vgs=2.630V

E7.4 For drain current 𝐼𝐷 = 10 mA what were the values of 𝑉𝐺𝑆 , 𝑉𝐷𝑆 ? 4
Vgs=2.504V
Vds=1.685V

E7.5 For 𝑉𝐺𝑆 = 5 V, what were the values of 𝐼𝐷 , 𝑉𝐷𝑆 ? 4

Id=30.03A Vds=0.052V

Experiment 8 Transistor I-V characteristics

E8.1 Show your graphs for the following characteristics of your NPN BJT: 9
𝐼𝐶 vs 𝑉𝐶𝐸 , ℎ𝐹𝐸 vs 𝐼𝐶 , 𝐼𝐶 vs 𝑉𝐵𝐸
E8.2 Show your graphs for the following characteristics of your PNP BJT: 9
𝐼𝐶 vs 𝑉𝐶𝐸 , ℎ𝐹𝐸 vs 𝐼𝐶 , 𝐼𝐶 vs 𝑉𝐸𝐵
 E8.3 Show your graphs for the following characteristics of your MOSFET: 6

Experiment 9 Common-emitter amplifier

E9.1 What values did you measure for your transistor’s base-emitter voltage and current gain? 3
Hfe=164, Vbe= 0.769V at Ib=5mA
E9.2 Show your calculations for the common-emitter bias circuit components including the emitter and 10
collector resistors. What value did you predict for the amplifier’s voltage gain?
Vcc=9V, Vc=4.5, 𝑉𝐸 = 𝟎.𝟗 𝐕
𝑽𝑬 𝟎. 𝟗
𝑹𝑬 = = = 𝟗𝟎𝟎𝜴
𝑰𝑪𝑸 𝟏 × 𝟏𝟎−𝟑
𝟗 − 𝟒. 𝟓
𝑹𝑪 = = 𝟒. 𝟓𝒌Ω
𝟏 × 𝟏𝟎−𝟑
𝜷𝑹𝑬 𝟏𝟔𝟒(𝟗𝟎𝟎)
𝑹𝑻𝑯 = = = 𝟏𝟒𝟕𝟔𝟎Ω
𝟏𝟎 𝟏𝟎
−𝟑
𝑰𝑪 𝟏 × 𝟏𝟎
𝑰𝑩 = = = 𝟓. 𝟖𝟏𝟑𝟗 × 𝟏𝟎−𝟔 𝑨
𝜷 𝟏𝟔𝟒
𝑽𝒕𝒉 = 𝑰𝑩 𝑹𝑻𝑯 + 𝑽𝑩𝑬 + (𝟏 + 𝜷)𝑰𝑩 𝑹𝑬 = (𝟓. 𝟖𝟏𝟑𝟗 × 𝟏𝟎−𝟔 )( 𝟏𝟒𝟕𝟔𝟎)+0.7+(1+164)( 𝟓. 𝟖𝟏𝟑𝟗 × 𝟏𝟎−𝟔)(900)
= 1.6952V
RB1=VccRth/Vth=(9)(14760)/(1.6952)=𝟕. 𝟖𝟑𝟒𝟗 × 𝟏𝟎𝟒 Ω
RB2=(RB1)(Rth)/(RB1-Rth)=( 𝟕. 𝟖𝟑𝟒𝟗 × 𝟏𝟎𝟒 )( 𝟏𝟒𝟕𝟔𝟎)/( 𝟕. 𝟖𝟑𝟒𝟗 × 𝟏𝟎𝟒 -(𝟏𝟒𝟕𝟔𝟎))=1.8186× 𝟏𝟎𝟒 Ω

Resistors used:

𝑹𝑩𝟏 ≈ 𝟖𝟐𝒌Ω

𝑹𝑩𝟐 ≈ 𝟏𝟖𝒌Ω

𝑹𝑬 ≈ 𝟏𝒌

Av=-Rc/Re= -0.2

E9.3 What values did you measure for the amplifier’s Q-point? Include all relevant voltages and currents. 6
Icq=1mA
Ibq=6.3µA
Vcq= 4.5V

E9.4 Show your calculation for the amplifier’s measured voltage gain. Express in decibels. 4
Vout=5.6, Vin=1.04
𝟓.𝟔
Voltage gain(db)=20lg =14.623dB
𝟏.𝟎𝟒

E9.5 Show your measured plot for the amplifier’s frequency response (gain & phase) from 10 Hz to 10 MHz. 8

E9.6 Show your calculation for the measured voltage gain of the emitter-bypassed common-emitter 4
amplifier. Express in decibels.
𝟒.𝟎𝟐
Voltage gain(db)=20lg −𝟑 =42.34dB
𝟑𝟎.𝟕×𝟏𝟎
Experiment 10 Common-source amplifier
E10.1 What values of gate to source ON voltage and transconductance did you measure for your MOSFET? 4
Vgs(on)=2.443V at Id=5.03mA and Ig=1µA
Vgs(off)=1.761V at Id=4.9µA
Gm=26.5Ma/v at Id=3.0mA to 5.0mA
Rds(on)=1.5Ω at Id=5.0mA and Vgs=8.0V

E10.2 Show your calculations for the common-source bias circuit components including the drain and source 10
resistors. What value did you predict for the amplifier’s voltage gain?
𝑽𝑫𝑫 = 𝟗, 𝑽𝑮 = 𝟑. 𝟒𝟒𝟑𝟎, 𝑽𝑮𝑺 = 𝟐. 𝟒𝟒𝟑𝟎, 𝑽𝑺 = 𝟏, 𝑽𝑻𝑯 = 𝟑. 𝟒𝟒𝟑𝟎 , 𝑽𝑻𝑵 = 𝟏. 𝟑
𝑹𝑻𝑯 = 𝟏. 𝟑 𝑴𝜴
𝑽𝑫𝑫 − 𝑽𝑫 𝟗 − 𝟒. 𝟓
𝑹𝑫 = = = 𝟒. 𝟓𝒌Ω
𝑰𝑫𝑸 𝟏 × 𝟏𝟎−𝟑
𝑽𝑺 𝟏
𝑹𝑺 = = = 𝟏𝒌Ω
𝑰𝑫𝑸 𝟏 × 𝟏𝟎−𝟑
𝑽𝑫𝑫 𝑹𝑻𝑯 (𝟗)(𝟏. 𝟑𝑴)
𝑹𝑮𝟏 = = = 𝟑. 𝟑𝟗𝟖 × 𝟏𝟎𝟔 Ω
𝑽𝑮 𝟑. 𝟒𝟒𝟑𝟎
𝑹𝟏 𝑹𝑻𝑯 (𝟑. 𝟑𝟗𝟖 × 𝟏𝟎𝟔 )(𝟏. 𝟑𝑴)
𝑹𝑮𝟐 = ; 𝑹𝑻𝑯 𝒈𝒊𝒗𝒆𝒏 = = 𝟐. 𝟏𝟎𝟓𝟓 × 𝟏𝟎𝟔 Ω
𝑹𝟏 − 𝑹𝑻𝑯 (𝟑. 𝟑𝟗𝟖 × 𝟏𝟎𝟔 ) − 𝟏. 𝟑𝑴

Resistors used:
𝑹𝑮𝟏 ≈ 𝟑. 𝟑𝑴Ω
𝑹𝑮𝟐 ≈ 𝟐. 𝟐𝑴Ω
𝑹𝑫 ≈ 𝟒. 𝟕𝒌Ω

E10.3 What values did you measure for the amplifier’s Q-point? Include all relevant voltages and currents. 6
Vdd=9V
𝑰𝑫𝑸 = 𝟏. 𝟑𝟏𝒎𝑨
𝑰𝑩𝑸 = 𝟎𝑨
𝑽𝑫 = 𝟔. 𝟑𝟏𝟕𝑽
𝑽𝟏 = 𝟔. 𝟑𝟏𝟕𝑽

𝑽𝟐 = 𝟒. 𝟕𝟔𝑽

𝑽𝑺 = 𝟏. 𝟑𝟒𝟎𝑽

E10.4 Show your calculation for the amplifier’s measured voltage gain at 50 kHz without the source 4
capacitor in circuit. Express in decibels.
Vin pk-pk=1.70V
Vout pk-pk=64.0mV
𝟔𝟒.𝟎𝒎𝑽
Voltage gain(db)=20lg 𝟏.𝟕𝟎 =-28.48dB

E10.5 Show your calculation for the amplifier’s measured voltage gain at 50 kHz with the source capacitor in 4
circuit. Express in decibels.
Vin pk-pk=1.70V
Vout pk-pk=32.0mV
𝟑𝟐.𝟎𝒎𝑽
Voltage gain(db)=20lg 𝟏.𝟕𝟎 =-34.51dB
 E10.6 Show your measured plot for the amplifier’s frequency response (gain & phase) from 10 Hz to 10 8
MHz.

Experiment 11 BJT Emitter-follower (Common-collector) amplifier

E11.1 Show how you calculated a value for the emitter resistor. 2
𝜷×𝑹𝑬 (𝟏𝟔𝟒)(𝟐𝟐𝟓𝟎)
Vcc=9V, Ic=2× 𝟏𝟎−𝟑 , Rth = = = 𝟑6900Ω
𝟏𝟎 𝟏𝟎
𝑽𝑬 𝟒.𝟓
𝑹𝑬 = = = 𝟐𝟐𝟓𝟎Ω
𝑰𝑪 𝟐×𝟏𝟎−𝟑

E11.2 Show how you calculated the required base current for 2 mA collector current. Show your calculations 4
for the best choices of base biasing resistors.
𝑽𝑪𝑪 = 𝟗𝑽
𝑽𝑬 = 𝟒. 𝟓𝑽
𝑽𝒕𝒉 = 𝑰𝑩 𝑹𝒕𝒉 + 𝟎. 𝟕 + 𝑽𝒆

𝑽𝒄𝒄𝑹𝒕𝒉 (𝟗)(𝟑𝟔𝟗𝟎𝟎)
𝑹𝑩𝟏 = = = 𝟓. 𝟖𝟒𝟗𝟓 × 𝟏𝟎𝟒
𝑽𝒕𝒉 (𝟓. 𝟔𝟕𝟕𝟒)
𝑹𝑩𝟏 × 𝑹𝒕𝒉 (𝟓. 𝟖𝟒𝟗𝟓 × 𝟏𝟎𝟒 )(𝟑𝟔𝟗𝟎𝟎)
𝑹𝑩𝟐 = = = 𝟗. 𝟗𝟗𝟓 × 𝟏𝟎𝟒
𝑹𝑩𝟏 − 𝑹𝒕𝒉 (𝟓. 𝟖𝟒𝟗𝟓 × 𝟏𝟎𝟒 )(𝟑𝟔𝟗𝟎𝟎)
𝑰𝒄
𝑰𝑩 = = 𝟏. 𝟐𝟏𝟗𝟓 × 𝟏𝟎−𝟓
𝜷
Resistors used:
𝑹𝑩𝟏 ≈ 𝟓𝟔. 𝟐𝒌Ω
𝑹𝑩𝟐 ≈ 𝟏𝟎𝟎𝒌Ω
𝑹𝑬 ≈ 𝟐. 𝟐𝒌Ω

E11.3 What values did you measure for the amplifier’s Q-point? Include all relevant voltages and currents. 4
𝑰𝑪𝑸 = 𝟐. 𝟎𝟒𝒎𝑨
𝑽𝑬 = 𝟒. 𝟓𝟑𝑽
𝑰𝑩𝑸 = 𝟏𝟓. 𝟓𝝁𝑨
𝑽𝟏 = 𝟑. 𝟖𝟐𝟐𝑽
𝑽𝟐 = 𝟓. 𝟐𝟏𝑽

E11.4 Show your calculations for the amplifier’s input and output impedances. 6
(𝑹𝑻𝑯 )(𝜷𝑹𝑬 ) (𝟑𝟔𝟗𝟎𝟎)(𝟏𝟔𝟒)(𝟐𝟐𝟓𝟎)
Input impedance: 𝑹𝑻𝑯 //𝜷𝑹𝑬 = =
𝑹𝑻𝑯 +𝜷𝑹𝑬 (𝟑𝟔𝟗𝟎𝟎)+(𝟏𝟔𝟒)(𝟐𝟐𝟓𝟎)
= 𝟑𝟑𝟓𝟒𝟓. 𝟒Ω
 𝜷 ∗ 𝑽𝑻 (𝟏𝟔𝟒)(𝟎. 𝟎𝟐𝟓)
𝒓𝝅 = = = 𝟐𝟎𝟓𝟎
𝑰𝑪𝑸 (𝟐 × 𝟏𝟎−𝟑 )
𝑰𝑪𝑸 𝟐 × 𝟏𝟎−𝟑
𝒈𝒎 = = = 𝟎. 𝟎𝟖
𝑽𝑻 𝟎. 𝟎𝟐𝟓

𝒓𝝅 𝟐𝟎𝟓𝟎
Output impedance: = = 𝟏𝟐. 𝟒𝟐𝟒Ω
(𝜷+𝟏) 𝟏𝟔𝟒+𝟏
𝟏 𝟏
= = 𝟏𝟐. 𝟓Ω
𝒈𝒎 𝟎. 𝟎𝟖

E11.5 What was the measured maximum peak to peak input voltage? What did you measure for the 6
amplifier’s voltage gain? What was the measured phase shift?
Pk to pk input voltage:
Vin = 9.80V
Vout=9.04V

Phase shift= -2.16deg

𝑽𝒐𝒖𝒕 𝟗.𝟎𝟒
Voltage gain= = = 𝟎. 𝟗𝟐𝟐
𝑽𝒊𝒏 𝟗.𝟖𝟎

Amplitude: 9.05V

E11.6 Show scope trace of the amplifier’s output for a 12 V p-p input. Describe how the output has changed. 6

The output has become a half sine wave as the bottom(negative half) has been clipped due to the input
signal being too high, from an input of a full sine wave.

E11.7 What was the measured maximum peak to peak input voltage with 47 Ω load? What did you measure 4
for the amplifier’s voltage gain? What was the measured phase shift? How has the load resistance affected
the maximum useable input signal?
Measured Phase shift was 28.6°
The maximum useable input signal, Vin amp= 322.0mVp
Vin=1.14V
Vout=800mV
𝑽𝒐𝒖𝒕 𝟖𝟎𝟎𝒎𝑽
Voltage gain= 𝑽𝒊𝒏 = 𝟏.𝟏𝟒𝑽 = 𝟎. 𝟕𝟎𝟏
 E11.8 Suggest how the circuit might be modified to increase the maximum output amplitude with no 8
distortion. Test your suggestion, build the new circuit, predict and then measure and record the maximum
output power that your new circuit can deliver into a 47 Ω load.
I did not manage to build and test this circuit as the extra lab session was cancelled due to covid 19. Thus I
have used a multisim model instead to answer this question.

Reduce 𝑹𝑬 𝒕𝒐 𝟒𝟕Ω

VCC

9V

R1
56.2Ω

C2 Q1
PR1 2N3904
V
100nF C1 V
V1 RE2
5Vpk 100kΩ 100nF RL
50kHz RE
1MΩ
0° V 47Ω
V

The distortion has been alleviated significantly.

Vin (peak to peak)=10.717V
Vout (peak to peak)=839.9mV
𝟖𝟑𝟗.𝟗𝒎𝑽
The voltage gain is: = 𝟎. 𝟎𝟕𝟖𝟒
𝟏𝟎.𝟕𝟏𝟕𝑽
Voltage gain in dB = 20log(0.0784) =-22.117dB

Experiment 12 Multi-stage Amplifier Design, Simulate and Build

E12.1 Provide stage and circuit schematics and a detailed explanation of your designed amplifier topology 20
including your rationale for all chosen Q-points. Show detailed calculations for all the biasing components in
each stage of your amplifier.

Stage 1
Common Collector Amplifier
CC Amplifier was chosen as it results in high input impedance and low output impedance.
Vcc=9V, 𝑽𝑩𝑬 = 𝟎. 𝟕
𝑹𝟐 𝟑. 𝟗 × 𝟏𝟎𝟔
𝑽𝑩 = ( ) 𝑽𝒄𝒄 = ( ) × 𝟗 = 𝟒. 𝟎𝟖𝟏𝑽
𝑹𝟐 + 𝑹𝟏 (𝟒. 𝟕 × 𝟏𝟎𝟔 ) + (𝟑. 𝟗 × 𝟏𝟎𝟔 )
𝑽𝑬 = 𝑽𝑩 − 𝟎. 𝟕=3.381V
𝑽𝑬 𝟑. 𝟑𝟖𝟏
𝑰𝑬 ≅ 𝑰𝑪𝑸 = = = 𝟏. 𝟓𝟑𝟔𝟖 × 𝟏𝟎−𝟒 𝑨
𝑹𝑬𝟏 𝟐𝟐𝟎𝟎𝟎
𝑽𝑪𝑬𝑸 = 𝑽𝒄𝒄 − 𝑽𝑬 = 𝟗 − 𝟑. 𝟑𝟖𝟏 = 𝟓. 𝟔𝟏𝟗𝑽
Cutoff≈𝑽𝒄𝒄
Saturation= Vcc/𝑹𝑬𝟏

𝟐𝟓 × 𝟏𝟎−𝟑
𝒓𝝅 = = 𝟏𝟔𝟐. 𝟔𝟕𝟔
𝑰𝑬
𝒛𝒃𝒂𝒔𝒆 = 𝜷(𝑹𝑬𝟏 + 𝒓𝝅 )=3634678
𝑹 (𝑹 )
𝑹𝑻𝑯 = (𝑹𝟐 𝟏 )= 2131395Ω
𝟐 +𝑹𝟏
𝒛𝒊𝒏 = 𝑹𝑻𝑯 ||𝒛𝒃𝒂𝒔𝒆 = 𝟏. 𝟑𝟒𝑴Ω
(𝑹𝟏 //𝑹𝟐 )
𝒁𝒐𝒖𝒕 = 𝑹𝑬𝟏 ||(𝒓𝝅 + )= 8203.05Ω
𝜷+𝟏

Stage 2
Common Emitter Amplifier

Vcc=9V, 𝑽𝑩𝑬 = 𝟎. 𝟕
𝑹𝟐 𝟑. 𝟑 × 𝟏𝟎𝟔
𝑽𝑩 = ( ) 𝑽𝒄𝒄 = ( ) × 𝟗 = 𝟓. 𝟒𝑽
𝑹𝟐 + 𝑹𝟏 (𝟐. 𝟐 × 𝟏𝟎𝟔 ) + (𝟑𝟑. 𝟑 × 𝟏𝟎𝟔 )
𝑽𝑪 = 𝑰𝑪 × 𝑹𝒄 = 𝟎. 𝟕𝟗𝟎𝟕𝑽
𝑽𝑬 𝟓. 𝟒
𝑰𝑬 ≅ 𝑰𝑪𝑸 = = = 𝟗. 𝟔𝟒 × 𝟏𝟎−𝟑 𝑨
𝑹𝑬𝟏 𝟓𝟔𝟎
𝑽𝑪𝑬𝑸 = 𝑽𝒄𝒄 − (𝑽𝑬 + 𝑽𝑪 ) = 𝟗 − (𝟎. 𝟕𝟗𝟎𝟕 + 𝟓. 𝟒) = 𝟐. 𝟖𝟎𝟗𝑽
Cutoff≈𝑽𝒄𝒄
Saturation= Vcc/𝑹𝑬𝟏

𝟐𝟓 × 𝟏𝟎−𝟑
𝒓𝝅𝟐 = = 𝟐. 𝟓𝟗𝟐𝟔
𝑰𝑬
Stage 3:
Common Collector Amplifier

Vcc=9V, 𝑽𝑩𝑬 = 𝟎. 𝟕
𝑹𝟐 𝟑𝟗𝟎𝟎𝟎
𝑽𝑩 = ( ) 𝑽𝒄𝒄 = ( ) × 𝟗 = 𝟒. 𝟎𝟖𝟏𝑽
𝑹𝟐 + 𝑹𝟏 𝟒𝟕𝟎𝟎𝟎 + (𝟑𝟗𝟎𝟎𝟎)
𝑽𝑬 = 𝑽𝑩 − 𝟎. 𝟕=3.381V
𝑽𝑬 𝟑. 𝟑𝟖𝟏
𝑰𝑬 ≅ 𝑰𝑪𝑸 = = = 𝟏. 𝟓𝟑𝟔𝟖 × 𝟏𝟎−𝟒 𝑨
𝑹𝑬𝟏 𝟐𝟐𝟎𝟎𝟎
𝑽𝑪𝑬 = 𝑽𝒄𝒄 − 𝑽𝑬 = 𝟗 − 𝟑. 𝟑𝟖𝟏 = 𝟓. 𝟔𝟏𝟗𝑽
Cutoff≈𝑽𝒄𝒄
Saturation= Vcc/𝑹𝑬𝟏

𝟐𝟓 × 𝟏𝟎−𝟑
𝒓𝝅𝟑 = = 𝟏𝟔𝟐. 𝟔𝟕𝟔
𝑰𝑬

Overall Schematic
𝑹
AV3= 𝟏+𝒓𝑬 ≈ 𝟏
𝝅𝟑
𝑹𝒊𝒏𝟏(𝒃𝒂𝒔𝒆) = 𝜷(𝑹𝑬𝟐 + 𝒓𝝅𝟐 )=(164)(560+2.5926)=92265.1864
(𝟒𝟕𝒌)(𝟑𝟗𝒌)
𝒁𝒊𝒏𝟏 = 𝑹𝟓||𝑹𝟔||𝑹𝒊𝒏𝟏(𝒃𝒂𝒔𝒆) = ||𝟗𝟐𝟐𝟔𝟓. 𝟏𝟖𝟔𝟒 = 𝟏𝟕𝟑𝟏𝟒. 𝟐𝟑
𝟒𝟕𝒌 + 𝟑𝟗𝒌
𝒁𝒊𝒏𝟏 𝟏𝟕𝟑𝟏𝟒.𝟐𝟑
AV2=𝑹 +𝒓 = 𝟓𝟔𝟎+𝟐.𝟓𝟗𝟐𝟔 = 𝟑𝟎. 𝟕𝟕𝟓
𝑬𝟐 𝝅𝟐
𝑹𝒊𝒏𝟐(𝒃𝒂𝒔𝒆) = 𝜷(𝑹𝑬𝟏 + 𝒓𝝅𝟏 )=(164)(22000+162.676)=3634678
(𝟐𝟐𝒌)(𝟑𝟑𝒌)
𝒁𝒊𝒏𝟐 = 𝑹𝟑||𝑹𝟒||𝑹𝒊𝒏𝟐(𝒃𝒂𝒔𝒆) = ||𝟑𝟔𝟑𝟒𝟔𝟕𝟖 = 𝟏𝟑𝟏𝟓𝟐. 𝟐𝟑
𝟐𝟐𝒌 + 𝟑𝟑𝒌
𝒁𝒊𝒏𝟐
AV1=𝑹 +𝒓 = 𝟎. 𝟓𝟗𝟑𝟒𝟒
𝑬𝟐 𝝅𝟐

Av=AV1*AV2*AV3=18.263=20log(18.263)=25.3dB
E12.2 Provide an explanation of your submitted Multisim File which should contain schematics for each 2
individually designed stage and a complete amplifier. All generated simulation plots must include the circuit 0
schematic from which it was generated. Show that the simulated Q-points of each stage are close to the
designed values stipulated in E12.1.

Stage 1:

Icq= 80.3µA
Vceq=1.77V

Logarithmic Gain plot for Stage 1

dB Gain plot for Stage 1

Stage 2
Icq=448µA
Vceq=251mV

Logarithmic Gain Plot

dB Gain Plot

Stage 3

Icq=156µA
Vceq=3.44V
Logarithmic Gain plot of Stage 3

dB Gain plot of Stage 3

3 Stage Amplifier

Transient Response for Rload(R7) = 1MΩ

The distortion at the output can be attributed to inaccurate bias and q-point values generated in the
simulation as a result the top positive half resembles a near flat top.

E12.3 Simulate and show your Multisim plots of the unloaded gain and phase response of your complete 8
amplifier over the frequency range 1 Hz to 10 MHz, plotting the gain in decibels and phase in degrees.
E12.4 Simulate and show your Multisim plots of the unloaded input impedance over the same range as above. 4
Does your design meet the specification?

Yes it meets the design specification only to a certain extent as the magnitude of the Rin is generally large
enough i.e more than 1M Ω up until frequency of about 100Hz after which it falls below 1M Ω

E12.5 Simulate and show your Multisim plots of the output impedance over the same range as above. 4
Assume zero source impedance. Does your design meet the specification?

It does not meet the design specification as Rout was more than 100 Ω .
E12.6 Repeat E12.3 & E12.4 with a 600 Ω load impedance, and critically evaluate the performance of your 10
amplifier against the design specification.

The performance of the amplifier does not entirely meet the design requirement as the output gain was
lesser than the design specification of 20 dB < 𝐴𝑣 < 30 dB . However, the Rin did meet the requirement of
more than 1MΩ.

E12.7 Detail any significant changes that have taken place when using nearest preferred value components 9
in all of your simulation models. Give estimates for the changes in the operating points compared with exact
calculated values.
Using the nearest preferred value components significantly changed the gain, Rin and Q points achieved
because for a simulation it works based on logical manipulation, initial conditions/parameters would
need to be specified whereas for calculations and lab experiments it is difficult to set such parameters
hence resulting in the varying results. All parameters have to be properly modelled and calculated with no
errors however the software also makes assumptions that we cannot specify or control thus the results
vary significantly as shown below.

Stage 1 Amplifier:
Icq(simulation)= 80.3µA
Icq(calculated)= 1.5368 x 10^-4 A
Difference of 47%

Vceq(simulation)= 1.77V
Vceq(calculated)=5.619V
Difference of 68.5%

Stage2 Amplifier:
Icq(simulation)= 448µA
Icq(calculated)= 9.64 x 10^-3 A
Difference of 95%

Vceq(simulation)= 251mV
Vceq(calculated)=2.809V
Difference of 91%
Stage 3 Amplifier :
Icq(simulation)= 156µA
Icq(calculated)= 1.536 x 10^-4 A
Difference of 1.56%

Vceq(simulation)= 3.44V
Vceq(calculated)=5.619V
Difference of 39%

E12.12 Write a summary of your design rationale, why you have designed your amplifier with this particular 15
topology, giving any possible strengths and weakness you feel that your circuit design possesses. State how
your design meets, or does not meet, the design specification. You must be objectively critical here of your
amplifier’s overall performance.

The rationale for my 3 stage amplifier design is to ensure that there was high input impedance, low input
impedance while having a high gain. The strengths of having a 3 stage CC-CE-CC amplifier is that the input
impedance will be high and the output impedance will be low. I also theorized with calculations that the
gain will be reasonably high as CE which is second stage results in high voltage gain.

However, my weakness was, in an attempt to meet the criteria for low output voltage, I sacrificed the
performance of the amplifier by resulting in a very small gain as CC produces a voltage gain of less than
one.

I was not able to come to a compromise between amplifier performance and meeting the design criteria.
What could be considered in the future instead would be to use CB amplifier as they produce high voltage
gain or use a different combination of amplifiers: CC-CE instead. This way, the main function of an
amplifier which is to increase the voltage gain could be met even though there will be high impedance. If
the input resistance is high, it will draw little current and then will only be amplifying voltage; low output
impedance will mean little loading effect.

The distortion at the output can be attributed to inaccurate bias and q-point values generated in the
simulation as a result the top positive half resembles a near flat top, in this case a dome like shape at the
top. The arrangement of the circuit could have been an issue as well.

The circuit could alternatively look like this instead:

VCC
9V

R1 RC1
R3
4.7MΩ 82Ω
2.2MΩ

V
Vin A Cin1 Q1
PR1 Q2
2N3904
2N3904
10F C1
V1
R2 Cout2 V
50mVpk Vout A
PR2
10kHz 3.9MΩ 4.7µF R4 RE2
0° RE1 R7
3.3MΩ 560Ω 100µF
22kΩ 600Ω

It could also have been an issue of the transistor that was used, perhaps a different model would have
suited better and well to fit the criteria of the set up as it would have provided different parameter values
such as the β, which would have greatly impacted the other biasing components and Q point calculations.
Total Possible Marks 444