EE 312: Embedded Systems

Assignment 2

Name: Animesh Renanse

Roll No: 180108048
Group: 46

Question 1
Code:
XRA A // clear the accumulator
ADI 47H
SUI 92H
ADI 64H
STA 0020H // store answer in memory location 0020H
HLT

T-states: Total T-States = 36

Instruction T-States Explanation

XRA A 4 OPCODE Fetch (4)

7 OPCODE Fetch + Memory

SUI 92H READ
ADI 64H 4+3

STA 0020H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt

Flag Register:
Value S Z AC P CY

0100 0111 0 0 0 0 1

** Because of the subtraction operation earlier the Carry flag is set.

 Question 2
Code:
MVI C,A8H // load A8H into reg C
MVI A,0FH // load 0FH = 0000 1111 into A
ANA C // AND contents of A and C to mask D7 to D4
STA 5040H // store the result in 5040H
HLT

T-states: Total T-States = 36

Instruction T-States Explanation

MVI C,A8H 7 OPCODE Fetch + Memory

MVI A,0FH READ = 4 + 3

ANA C 4 OPCODE Fetch (4)

STA 5040H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt

Flag Register:
Value S Z AC P CY

0000 1000 0 0 1 0 0

** Because of the AND operation Aux Carry is set.

 Question 3
Code:
MVI D,8EH // load 8EH into reg D
MVI E,F7H // load F7H into reg E
MVI A,F0H // load F0H = 1111 0000 into A
ANA D // AND contents of accumulator and D to mask D3 to D0
MOV D,A // move result back in reg D
MVI A,F0H // load F0H = 1111 0000 into accumulator
ANA E // AND contents of accumulator and E to mask D3 to D0
XRA D // XOR with contents of D
STA 5040H // store result in 5040H
HLT

T-states: Total T-States = 62

Instruction T-States Explanation

MVI D, 8EH 7 OPCODE Fetch + Memory

MVI E, F7H READ = 4 + 3
MVI A, F0H

ANA D 4 OPCODE Fetch (4)

MOV D, A

MVI A,F0H 7 OPCODE Fetch + Memory

READ = 4 + 3

ANA E 4 OPCODE Fetch (4)

XRA D

STA 5040H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt

Flag Register:
Value S Z AC P CY

0000 1000 0 0 0 0 0
 Question 4
Code:
LHLD 0010H // load X1 and X2 from addresses 0010H and 0011H into H and L MOV
A,H //move X2 to A
ORA L // X1 or X2
CMA //gives X1 nor X2
MOV B,A //store nor result in B
LHLD 0020H //load X3 and X4 from addresses 0020H and 0021H into H and L MOV
A,H //move X4 to accumulator
ANA L //X3 and X4
CMA //gives X3 nand X4
ORA B //(X1 nor X2) or (X3 nand X4)
STA 2100H //store result in 2100H
HLT

T-states: Total T-States = 82

Instruction T-States Explanation

LHLD 0010H 16 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory READ +
Memory READ 4
+ (3+3) + 3 + 3

MOV A,H 4 OPCODE Fetch (4)

ORA L
CMA
MOV B,A

LHLD 0020H 16 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory READ +
Memory READ 4
+ (3+3) + 3 + 3

MOV A,H 4 OPCODE Fetch (4)

ANA L
CMA
ORA B

STA 5040H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt
Flag Register:
Value S Z AC P CY

1100 1011 1 0 0 0 0

** Here, X1 = 2AH, X2 = 5FH, X3 = 36H, X4 = 74H

(X1 nor X2) or (X3 nand X4) gives FFH = 1100 1011
As OR is the last logical instruction so carry and aux carry are unaffected

Question 5
Code:
LXI B,1040H // load B & C with 1040H (16-Bit)
LXI D,2311H // load D & E with 2311H (16-Bit)
MOV A,C // move contents of C into A
ADD E // add contents of E with A
MOV H,A // move contents of A into H
MOV A,B // move contents of B into A
ADC D // adding A and D with prev carry
MOV L,A // move contents of A into L
SHLD 511F // store content from H & L registers at 511FH
HLT

T-states: Total T-States = 65

Instruction T-States Explanation

LXI B,1040H 10 OPCODE Fetch + (Memory

LXI D,2311H READ + Memory READ)
4 + (3+3)

MOV A,C 4 OPCODE Fetch (4)

ADD E
MOV H,A
MOV A,B
ADC D
MOV L,A

SHLD 511F 16 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory READ +
Memory READ 4
+ (3+3) + 3 + 3

HLT 5 Halt
Flag Register:
Value S Z AC P CY

0011 0011 0 0 0 1 0

Question 6(a)
Code:
MVI B,00H // A=00H is stored in reg B
MVI C,01H // B=01H is stored in reg C
MVI D,01H // C=01H is stored in reg D
MOV A,B // move contents of reg B into A
ANA C // AND operator with contents of reg C and A
MOV E,A // store contents of A in reg E
MOV A,C // move contents of reg C into A
ANA D // AND operator with contents of reg D and A
CMA // NOT operator on contents of A
ORA E // OR perator with contents of reg E and A
STA 2100H // store contents of A at 2100H
HLT

T-states: Total T-States = 67

Instruction T-States Explanation

MVI B,00H 7 OPCODE Fetch + Memory

MVI C,01H READ = 4 + 3
MVI D,01H

MOV A,B 4 OPCODE Fetch (4)

ANA C
MOV E,A
MOV A,C
ANA D
CMD
ORA E

STA 2100H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt
Flag Register:
Value S Z AC P CY

0000 0000 0 1 0 1 0

Question 6(b)
Code:
MVI B,00H // A=00H is stored in reg B
MVI C,01H // B=01H is stored in reg C
MVI D,01H // C=01H is stored in reg D
MOV A,B // move contents of reg B into A
ANA C // AND operator with contents of reg C and A
MOV E,A // store contents of A in reg E
MOV A,B // move contents of reg C into A
ORA C // OR perator with contents of reg C and A
ANA D // AND operator with contents of reg D and A
ORA E // OR perator with contents of reg E and A
STA 2100H // store contents of A at 2100H
HLT

T-states: Total T-States = 67

Instruction T-States Explanation

MVI B,00H 7 OPCODE Fetch + Memory

MVI C,01H READ = 4 + 3
MVI D,01H

MOV A,B 4 OPCODE Fetch (4)

ANA C
MOV E,A
MOV A,C
ORA C
ANA D
ORA E

STA 2100H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt
Flag Register:
Value S Z AC P CY

0000 0001 0 0 0 0 0

Question 7
Code:
LDA 0100H //8-bit data at 0100H is loaded into accumulator
MOV B,A // move contents of A into reg B
ANI F0H //masking lower order bits (D7D6D5D40000)
RRC
RRC // right rotating twice for (00D7D6D5D400)
MOV C,A //store contents of A at reg C
MOV A,B // move contents of reg B into A
ANI 0FH //masking higher order bits (0000D3D2D1D0 )
RRC
RRC //right rotating twice for (D1D00000D3D2 )
MOV D,A //store contents of A at reg D
ANI F0H //masking lower order bits (D1D0000000)
RRC
RRC //right rotating twice for (00D1D00000)
MOV E,A //store contents of A at reg E
MOV A,D // move contents of reg D into A
ANI 0FH //masking higher order bits (000000D3D2 )
RLC
RLC // left rotating twice for (0000D3D200)
ORA E // Contents of reg E OR contents of A = (00D1D0D3D200)
ANA C // Contents of reg C OR contents of A = (00D7.D1D6.D0D5.D3D4.D200)
STA 2100H
HLT

T-states: Total T-States = 123

Instruction T-States Explanation

LDA 0020H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

MOV B,A 4 OPCODE Fetch (4)

ANI F0H 7 OPCODE Fetch + Memory

 READ = 4 + 3

RRC 4 OPCODE Fetch (4)

RRC

MOV C,A 4 OPCODE Fetch (4)

MOV A,B

ANI 0FH 7 OPCODE Fetch + Memory

READ = 4 + 3

RRC RRC 4 OPCODE Fetch (4)

MOV D,A

ANI F0H 7 OPCODE Fetch + Memory

READ = 4 + 3

RRC RRC 4 OPCODE Fetch (4)

MOV E,A
MOV A,D

ANI 0FH 7 OPCODE Fetch + Memory

READ = 4 + 3

RLC 4 OPCODE Fetch (4)

RLC
ORA E
ANA C

STA 2100H 13 OPCODE Fetch + (Memory

READ + Memory READ) +
Memory WRITE 4 + (3+3) +
3

HLT 5 Halt

Flag Register:

For 8-bit input B5H (1011 0101), output bit sequence is 04H (0000 0100).
Value S Z AC P CY

0000 0100 0 0 1 0 0

** Because of ANA C, Aux Carry is in set