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CA3140, CA3140A
Pinout
CA3140 (PDIP, SOIC)
TOP VIEW
OFFSET
1 8 STROBE
NULL
INV. INPUT 2 7 V+
-
NON-INV. +
3 6 OUTPUT
INPUT
OFFSET
V- 4 5
NULL
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1998, Copyright Intersil Americas Inc. 2002, 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA3140, CA3140A
Ordering Information
PART NUMBER TEMP. PKG.
(BRAND) RANGE (°C) PACKAGE DWG. #
2 FN957.10
July 11, 2005
CA3140, CA3140A
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
2. Short circuit may be applied to ground or to either supply.
TYPICAL VALUES
Output Resistance RO 60 60 Ω
Equivalent Input Noise Voltage (See Figure 35) eN RS = 100Ω f = 1kHz 40 40 nV/√Hz
f = 10kHz 12 12 nV/√Hz
IOM- Sink 18 18 mA
Transient Response (See Figure 28) tr RL = 2kΩ Rise Time 0.08 0.08 µs
CL = 100pF
OS Overshoot 10 10 %
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified
CA3140 CA3140A
3 FN957.10
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CA3140, CA3140A
Electrical Specifications For Equipment Design, at VSUPPLY = ±15V, TA = 25oC, Unless Otherwise Specified (Continued)
CA3140 CA3140A
Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V
NOTES:
3. At VO = 26VP-P , +12V, -14V and RL = 2kΩ.
4. At RL = 2kΩ.
TYPICAL VALUES
PARAMETER SYMBOL CA3140 CA3140A UNITS
Input Offset Voltage |VIO| 5 2 mV
Input Offset Current |IIO| 0.1 0.1 pA
Input Current II 2 2 pA
Input Resistance RI 1 1 TΩ
Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V
100 100 dB
Common Mode Rejection Ratio CMRR 32 32 µV/V
90 90 dB
Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V
2.6 2.6 V
Power Supply Rejection Ratio PSRR 100 100 µV/V
∆VIO/∆VS
80 80 dB
Maximum Output Voltage (See Figures 2, 8) VOM+ 3 3 V
VOM- 0.13 0.13 V
Maximum Output Current: Source IOM+ 10 10 mA
Sink I
OM- 1 1 mA
Slew Rate (See Figure 31) SR 7 7 V/µs
Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz
Supply Current (See Figure 32) I+ 1.6 1.6 mA
Device Dissipation PD 8 8 mW
Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 µA
4 FN957.10
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CA3140, CA3140A
Block Diagram
2mA 4mA
7 V+
BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
12pF
4 V-
5 1 8 STROBE
OFFSET
NULL
Schematic Diagram
BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK
7 V+
D1 D7
R13
5K
Q3 R9 Q20
Q1 Q2
50Ω
D8
R10
Q4 1K
Q6 Q5 R14
R12 20K
Q19 R11
20Ω 12K
Q7
Q21
Q17
R1
Q8 R8
8K
1K Q
18
6 OUTPUT
D2 D3 D4
D5
INVERTING
2
INPUT
- Q9 Q10
+
NON-INVERTING 3
INPUT C1
R2 R3
500Ω 500Ω 12pF
Q14 Q15 Q16
Q13
Q11 Q12 D6
R4 R5 R6 R7
500Ω 500Ω 50Ω 30Ω
5 1 8 4
OFFSET NULL STROBE V-
5 FN957.10
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CA3140, CA3140A
Application Information When the CA3140 is operating such that output Terminal 6 is
sinking current to the V- bus, transistor Q16 is the current
Circuit Description
sinking element. Transistor Q16 is mirror connected to D6, R7,
As shown in the block diagram, the input terminals may be with current fed by way of Q21, R12, and Q20. Transistor Q20, in
operated down to 0.5V below the negative supply rail. Two turn, is biased by current flow through R13, zener D8, and R14.
class A amplifier stages provide the voltage gain, and a The dynamic current sink is controlled by voltage level sensing.
unique class AB amplifier stage provides the current gain For purposes of explanation, it is assumed that output Terminal
necessary to drive low-impedance loads. 6 is quiescently established at the potential midpoint between
A biasing circuit provides control of cascoded constant current the V+ and V- supply rails. When output current sinking mode
flow circuits in the first and second stages. The CA3140 operation is required, the collector potential of transistor Q13 is
includes an on chip phase compensating capacitor that is driven below its quiescent level, thereby causing Q17, Q18 to
sufficient for the unity gain voltage follower configuration. decrease the output voltage at Terminal 6. Thus, the gate
terminal of PMOS transistor Q21 is displaced toward the V- bus,
Input Stage
thereby reducing the channel resistance of Q21. As a
The schematic diagram consists of a differential input stage consequence, there is an incremental increase in current flow
using PMOS field-effect transistors (Q9, Q10) working into a through Q20, R12, Q21, D6, R7, and the base of Q16. As a
mirror pair of bipolar transistors (Q11, Q12) functioning as load result, Q16 sinks current from Terminal 6 in direct response to
resistors together with resistors R2 through R5. The mirror pair the incremental change in output voltage caused by Q18. This
transistors also function as a differential-to-single-ended sink current flows regardless of load; any excess current is
converter to provide base current drive to the second stage internally supplied by the emitter-follower Q18. Short circuit
bipolar transistor (Q13). Offset nulling, when desired, can be protection of the output circuit is provided by Q19, which is
effected with a 10kΩ potentiometer connected across driven into conduction by the high voltage drop developed
Terminals 1 and 5 and with its slider arm connected to Terminal across R11 under output short circuit conditions. Under these
4. Cascode-connected bipolar transistors Q2, Q5 are the conditions, the collector of Q19 diverts current from Q4 so as to
constant current source for the input stage. The base biasing reduce the base current drive from Q17, thereby limiting current
circuit for the constant current source is described flow in Q18 to the short circuited load terminal.
subsequently. The small diodes D3, D4, D5 provide gate oxide
protection against high voltage transients, e.g., static electricity. Bias Circuit
Quiescent current in all stages (except the dynamic current
Second Stage
sink) of the CA3140 is dependent upon bias current flow in R1.
Most of the voltage gain in the CA3140 is provided by the
The function of the bias circuit is to establish and maintain
second amplifier stage, consisting of bipolar transistor Q13
constant current flow through D1, Q6, Q8 and D2. D1 is a diode
and its cascode connected load resistance provided by
connected transistor mirror connected in parallel with the base
bipolar transistors Q3, Q4. On-chip phase compensation,
emitter junctions of Q1, Q2, and Q3. D1 may be considered as a
sufficient for a majority of the applications is provided by C1.
current sampling diode that senses the emitter current of Q6
Additional Miller-Effect compensation (roll off) can be
and automatically adjusts the base current of Q6 (via Q1) to
accomplished, when desired, by simply connecting a small
maintain a constant current through Q6, Q8, D2. The base
capacitor between Terminals 1 and 8. Terminal 8 is also
currents in Q2, Q3 are also determined by constant current flow
used to strobe the output stage into quiescence. When
D1. Furthermore, current in diode connected transistor Q2
terminal 8 is tied to the negative supply rail (Terminal 4) by
establishes the currents in transistors Q14 and Q15.
mechanical or electrical means, the output Terminal 6
swings low, i.e., approximately to Terminal 4 potential. Typical Applications
Output Stage Wide dynamic range of input and output characteristics with
The CA3140 Series circuits employ a broad band output stage the most desirable high input impedance characteristics is
that can sink loads to the negative supply to complement the achieved in the CA3140 by the use of an unique design based
capability of the PMOS input stage when operating near the upon the PMOS Bipolar process. Input common mode voltage
negative rail. Quiescent current in the emitter-follower cascade range and output swing capabilities are complementary,
circuit (Q17, Q18) is established by transistors (Q14, Q15) allowing operation with the single supply down to 4V.
whose base currents are “mirrored” to current flowing through
The wide dynamic range of these parameters also means
diode D2 in the bias circuit section. When the CA3140 is
that this device is suitable for many single supply
operating such that output Terminal 6 is sourcing current,
applications, such as, for example, where one input is driven
transistor Q18 functions as an emitter-follower to source current
below the potential of Terminal 4 and the phase sense of the
from the V+ bus (Terminal 7), via D7, R9, and R11. Under these
output signal must be maintained – a most important
conditions, the collector potential of Q13 is sufficiently high to
consideration in comparator applications.
permit the necessary flow of base current to emitter follower
Q17 which, in turn, drives Q18.
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CA3140, CA3140A
Output Circuit Considerations level shifting circuitry usually associated with the 741 series
Excellent interfacing with TTL circuitry is easily achieved with of operational amplifiers.
a single 6.2V zener diode connected to Terminal 8 as shown Figure 4 shows some typical configurations. Note that a
in Figure 1. This connection assures that the maximum series resistor, RL, is used in both cases to limit the drive
output signal swing will not go more positive than the zener available to the driven device. Moreover, it is recommended
voltage minus two base-to-emitter voltage drops within the that a series diode and shunt diode be used at the thyristor
CA3140. These voltages are independent of the operating input to prevent large negative transient surges that can
supply voltage. appear at the gate of thyristors, from damaging the
integrated circuit.
V+
5V TO 36V
LOGIC Offset Voltage Nulling
7
SUPPLY
2 8 6.2V 5V
The input offset voltage can be nulled by connecting a 10kΩ
potentiometer between Terminals 1 and 5 and returning its
CA3140 6 TYPICAL wiper arm to terminal 4, see Figure 3A. This technique,
TTL GATE
3 ≈ 5V however, gives more adjustment range than required and
4 therefore, a considerable portion of the potentiometer
rotation is not fully utilized. Typical values of series resistors
(R) that may be placed at either end of the potentiometer,
FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO
see Figure 3B, to optimize its utilization range are given in
TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT the Electrical Specifications table.
SWING TO TTL LEVELS
An alternate system is shown in Figure 3C. This circuit uses
1000 only one additional resistor of approximately the value
OUTPUT STAGE TRANSISTOR (Q15, Q16)
V+
V+ V+
2 7
2 7 2 7
CA3140 6
CA3140 6 CA3140 6
3 4
3 4 5 3 4
5 1 5
1 R R 1
10kΩ 10kΩ 10kΩ
R
V- V- V-
FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION
FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS
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CA3140, CA3140A
RS V+ +HV
7 LOAD
LOAD 2
30V
NO LOAD MT2 CA3140 6
120VAC 7
RL
2
3
CA3140 6 4
MT1
RL
3
4
FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES
FOLLOWER
+15V
7
3 0.1µF
SIMULATED
10kΩ LOAD
CA3140 6
2 100pF 2kΩ
4
0.1µF
LOAD RESISTANCE (RL) = 2kΩ -15V
LOAD CAPACITANCE (CL) = 100pF 2kΩ
4
2 7
2 0.1µF
FOLLOWER SIMULATED
0 5kΩ LOAD
INVERTING
-2 CA3140 6
200Ω
-4 3 100pF 2kΩ
4
-6 1mV 1mV
0.1µF 5.11kΩ
4.99kΩ
-8 10mV 10mV -15V
-10
0.1 1.0 10 SETTLING POINT
SETTLING TIME (µs) D1 D2
1N914 1N914
Bandwidth and Slew Rate The exceptionally fast settling time characteristics are largely
For those cases where bandwidth reduction is desired, for due to the high combination of high gain and wide bandwidth
example, broadband noise reduction, an external capacitor of the CA3140; as shown in Figure 6.
connected between Terminals 1 and 8 can reduce the open Input Circuit Considerations
loop -3dB bandwidth. The slew rate will, however, also be
As mentioned previously, the amplifier inputs can be driven
proportionally reduced by using this additional capacitor.
below the Terminal 4 potential, but a series current limiting
Thus, a 20% reduction in bandwidth by this technique will
resistor is recommended to limit the maximum input terminal
also reduce the slew rate by about 20%.
current to less than 1mA to prevent damage to the input
Figure 5 shows the typical settling time required to reach protection circuitry.
1mV or 10mV of the final value for various levels of large
Moreover, some current limiting resistance should be
signal inputs for the voltage follower and inverting unity gain
provided between the inverting input and the output when
amplifiers.
8 FN957.10
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CA3140, CA3140A
the CA3140 is used as a unity gain voltage follower. This input offset voltage) due to the application of large
resistance prevents the possibility of extremely large input differential input voltages that are sustained over long
signal transients from forcing a signal through the input periods at elevated temperatures.
protection network and directly driving the internal constant
Both applied voltage and temperature accelerate these
current source which could result in positive feedback via the
changes. The process is reversible and offset voltage shifts of
output terminal. A 3.9kΩ resistor is sufficient.
the opposite polarity reverse the offset. Figure 9 shows the
The typical input current is on the order of 10pA when the typical offset voltage change as a function of various stress
inputs are centered at nominal device dissipation. As the voltages at the maximum rating of 125oC (for metal can); at
output supplies load current, device dissipation will increase, lower temperatures (metal can and plastic), for example, at
raising the chip temperature and resulting in increased input 85oC, this change in voltage is considerably less. In typical
current. Figure 7 shows typical input terminal current versus linear applications, where the differential voltage is small and
ambient temperature for the CA3140. symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
It is well known that MOSFET devices can exhibit slight
amplifier employing a bipolar transistor input stage.
changes in characteristics (for example, small changes in
RL = 2kΩ,
100 -105
φOL CL = 0pF
-120 1K
10
20
0 1
101 102 103 104 105 106 107 108 -60 -40 -20 0 20 40 60 80 100 120 140
FREQUENCY (Hz) TEMPERATURE (oC)
FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 7. INPUT CURRENT vs TEMPERATURE
FREQUENCY
INPUT AND OUTPUT VOLTAGE EXCURSIONS
RL = ∞
0 1.5
-2.0 -0.5
-2.5 -1.0
-3.0 -1.5
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-)
FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
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CA3140, CA3140A
10 FN957.10
July 11, 2005
CA3140, CA3140A
CENTERING
-15V 10kΩ +15V
HIGH
7.5kΩ +15V +15V FREQUENCY
LEVEL 62kΩ 10kΩ
360Ω 0.1 910kΩ
7 µF 7-60pF
3 + 7
15kΩ 5 EXTERNAL
360Ω CA3080A 6 3 + 7
51 OUTPUT
2 - 7-60 CA3140 6 2 -
4 pF
pF 2 - 11kΩ CA3080 6
5 10kΩ 11kΩ 3 +
2MΩ HIGH 4
4 2.7kΩ
SYMMETRY -15V FREQ. 0.1
-15V EXTERNAL
+15V SHAPE -15V µF -15V
OUTPUT 13kΩ TO OUTPUT
2kΩ
100kΩ
AMPLIFIER
FROM BUFFER METER FREQUENCY
DRIVER (OPTIONAL) ADJUSTMENT 5.1kΩ TO
39kΩ 120Ω 10kΩ SINE WAVE
SHAPER 1N914
-15V +15V OUTPUT
AMPLIFIER
THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT USED
FREQUENCY
ADJUSTMENT
Top Trace: Output at junction of 2.7Ω and 51Ω resistors;
5V/Div., 500ms/Div.
+15V
Center Trace: External output of triangular function generator; METER DRIVER
POWER
2V/Div., 500ms/Div. AND BUFFER
SUPPLY ±15V
AMPLIFIER M
Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div. -15V
WIDEBAND
LINE DRIVER
SINE WAVE
SHAPER
51Ω
GATE DC LEVEL
FINE SWEEP
SWEEP ADJUST
RATE GENERATOR
OFF INT.
EXTERNAL
COARSE V- EXT. INPUT
RATE
11 FN957.10
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CA3140, CA3140A
FREQUENCY
500kΩ CALIBRATION
MAXIMUM
FREQUENCY 620kΩ
51kΩ 7
ADJUSTMENT TO CA3080A +15V -15V
10kΩ 3 + OF FUNCTION CA3080A
0.1µF
CA3140 6 GENERATOR
SWEEP IN (FIGURE 10) 7 5.6kΩ
3MΩ 2 - 4.7kΩ 4 3 +
7.5kΩ
5.1kΩ CA3140 6
4 5
TO
+15V 2 - 4 SUBSTRATE WIDEBAND
2kΩ METER 620Ω
0.1µF OF CA3019 OUTPUT
SENSITIVITY
12kΩ ADJUSTMENT 0.1µF AMPLIFIER
1kΩ 7
FREQUENCY 2.4kΩ -15V 10kΩ
CALIBRATION 200µA +15V
M METER R3 10kΩ
MINIMUM EXTERNAL
2.5 100 1MΩ
kΩ 11 OUTPUT
kΩ D1 D4
9 9.1kΩ
510Ω -15V
510Ω 6 5 8 2
R1
8 10 14 10kΩ
2kΩ D3 D6 D2 430Ω
6 12 9 1
METER R2
7 POSITION 3.6kΩ 13 1kΩ
ADJUSTMENT 3 4
3/ OF CA3086 D
5 CA3019 5
-15V DIODE ARRAY
FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER
750kΩ
“LOG”
100kΩ
SAWTOOTH 18MΩ
1N914
1MΩ 100kΩ FINE
RATE
22MΩ
470pF 75kΩ
SAWTOOTH 51kΩ
+15V
0.1
µF “LOG”+15V
+15V
7
2 - TRIANGLE 36kΩ 7
CA3140 6 3 - 10kΩ GATE
3 + 100kΩ CA3140 6 PULSE
4 30kΩ OUTPUT
0.1 TO OUTPUT 2 +
4
µF 50kΩ AMPLIFIER
LOG -15V
-15V 10kΩ
RATE
ADJUST EXTERNAL OUTPUT
43kΩ
10kΩ TO FUNCTION GENERATOR “SWEEP IN”
SWEEP WIDTH
-15V
7 +15V
3 +
CA3140 6
2 - 4 51kΩ 6.8kΩ 91kΩ 10kΩ
LOGVIO 5
1 TRIANGLE
25kΩ
5 1
3.9Ω TRANSISTORS SAWTOOTH
4 2 FROM CA3086
-15V ARRAY
100Ω “LOG”
390Ω 3
12 FN957.10
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CA3140, CA3140A
Sweeping Generator
Figure 13 shows a sweeping generator. Three CA3140s are FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR
SHOWING VOLTAGE FOLLOWER CONFIGURATION
used in this circuit. One CA3140 is used as an integrator, a
second device is used as a hysteresis switch that determines Essentially, the regulators, shown in Figures 16 and 17, are
the starting and stopping points of the sweep. A third connected as non inverting power operational amplifiers with a
CA3140 is used as a logarithmic shaping network for the log gain of 3.2. An 8V reference input yields a maximum output
function. Rates and slopes, as well as sawtooth, triangle, voltage slightly greater than 25V. As a voltage follower, when
and logarithmic sweeps are generated by this circuit. the reference input goes to 0V the output will be 0V. Because
the offset voltage is also multiplied by the 3.2 gain factor, a
Wideband Output Amplifier
potentiometer is needed to null the offset voltage.
Figure 14 shows a high slew rate, wideband amplifier
Series pass transistors with high ICBO levels will also
suitable for use as a 50Ω transmission line driver. This
prevent the output voltage from reaching zero because there
circuit, when used in conjunction with the function generator
is a finite voltage drop (VCESAT) across the output of the
and sine wave shaper circuits shown in Figures 10 and 12
CA3140 (see Figure 2). This saturation voltage level may
provides 18VP-P output open circuited, or 9VP-P output
indeed set the lowest voltage obtainable.
when terminated in 50Ω. The slew rate required of this
amplifier is 28V/µs (18VP-P x π x 0.5MHz). The high impedance presented by Terminal 8 is
+15V advantageous in effecting current limiting. Thus, only a small
+ 50µF 2.2 signal transistor is required for the current-limit sensing
SIGNAL
LEVEL - 25V kΩ 2N3053
ADJUSTMENT
amplifier. Resistive decoupling is provided for this transistor
to minimize damage to it or the CA3140 in the event of
2.5kΩ 3 + 7 1N914 2.7Ω OUT
51Ω unusual input or output transients on the supply rail.
CA3140 6
200Ω 1N914 2.7Ω 2W
2 - 4 Figures 16 and 17, show circuits in which a D2201 high speed
8
1 - 50µF diode is used for the current sensor. This diode was chosen
+ 25V 2.2
OUTPUT
kΩ
2N4037 for its slightly higher forward voltage drop characteristic, thus
DC LEVEL +15V 2.4pF
ADJUSTMENT 3kΩ 2pF giving greater sensitivity. It must be emphasized that heat
-15V
sinking of this diode is essential to minimize variation of the
-15V
1.8kΩ NOMINAL BANDWIDTH = 10MHz
current trip point due to internal heating of the diode. That is,
200Ω tr = 35ns 1A at 1V forward drop represents one watt which can result in
significant regenerative changes in the current trip point as the
diode temperature rises. Placing the small signal reference
FIGURE 14. WIDEBAND OUTPUT AMPLIFIER amplifier in the proximity of the current sensing diode also
Power Supplies helps minimize the variability in the trip level due to the
negative temperature coefficient of the diode. In spite of those
High input impedance, common mode capability down to the limitations, the current limiting point can easily be adjusted
negative supply and high output drive current capability are over the range from 10mA to 1A with a single adjustment
key factors in the design of wide range output voltage potentiometer. If the temperature stability of the current
supplies that use a single input voltage to provide a limiting system is a serious consideration, the more usual
regulated output voltage that can be adjusted from current sampling resistor type of circuitry should be employed.
essentially 0V to 24V.
A power Darlington transistor (in a metal can with heatsink),
Unlike many regulator systems using comparators having a is used as the series pass element for the conventional
bipolar transistor input stage, a high impedance reference current limiting system, Figure 16, because high power
voltage divider from a single supply can be used in Darlington dissipation will be encountered at low output
connection with the CA3140 (see Figure 15). voltage and high currents.
13 FN957.10
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CA3140, CA3140A
A small heat sink VERSAWATT transistor is used as the regulation also remains constant. Line regulation is 0.1% per
series pass element in the fold back current system, Figure volt. Hum and noise voltage is less than 200µV as read with a
17, since dissipation levels will only approach 10W. In this meter having a 10MHz bandwidth.
system, the D2201 diode is used for current sampling.
Figure 18A shows the turn ON and turn OFF characteristics
Foldback is provided by the 3kΩ and 100kΩ divider network
of both regulators. The slow turn on rise is due to the slow
connected to the base of the current sensing transistor.
rate of rise of the reference voltage. Figure 18B shows the
Both regulators provide better than 0.02% load regulation. transient response of the regulator with the switching of a
Because there is constant loop gain at all voltage settings, the 20Ω load at 20V output.
6 4 CA3086
6 4 CA3086
1kΩ
1kΩ
62kΩ
62kΩ
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION
HUM AND NOISE OUTPUT <200µVRMS LOAD REGULATION (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD)
(MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) LINE REGULATION 0.1%/V <0.02%
LINE REGULATION 0.1%/V <0.02%
FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK”
CURRENT LIMITING
14 FN957.10
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CA3140, CA3140A
Tone Control Circuits Bass treble boost and cut are ±15dB at 100Hz and 10kHz,
High slew rate, wide bandwidth, high output voltage respectively. Full peak-to-peak output is available up to at
capability and high input impedance are all characteristics least 20kHz due to the high slew rate of the CA3140. The
required of tone control amplifiers. Two tone control circuits amplifier gain is 3dB down from its “flat” position at 70kHz.
that exploit these characteristics of the CA3140 are shown in Figure 19 shows another tone control circuit with similar
Figures 19 and 20. boost and cut specifications. The wideband gain of this
The first circuit, shown in Figure 20, is the Baxandall tone circuit is equal to the ultimate boost or cut plus one, which in
control circuit which provides unity gain at midband and this case is a gain of eleven. For 20dB boost and cut, the
uses standard linear potentiometers. The high input input loading of this circuit is essentially equal to the value of
impedance of the CA3140 makes possible the use of low- the resistance from Terminal No. 3 to ground. A detailed
cost, low-value, small size capacitors, as well as reduced analysis of this circuit is given in “An IC Operational
load of the driving stage. Transconductance Amplifier (OTA) With Power Capability” by
L. Kaplan and H. Wittlinger, IEEE Transactions on Broadcast
and Television Receivers, Vol. BTR-18, No. 3, August, 1972.
FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)
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16 FN957.10
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CA3140, CA3140A
Pulse “droop” during the hold interval is 170pA/200pF which is Current Amplifier
0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA represents The low input terminal current needed to drive the CA3140
the typical leakage current of the CA3080A when strobed off. If makes it ideal for use in current amplifier applications such
C1 were increased to 2000pF, the “hold-droop” rate will as the one shown in Figure 25 (see Note 14). In this circuit,
decrease to 0.085µV/µs, but the slew rate would decrease to low current is supplied at the input potential as the power
0.25V/µs. The parallel diode network connected between supply to load resistor RL. This load current is increased by
Terminal 3 of the CA3080A and Terminal 6 of the CA3140 the multiplication factor R2/R1, when the load current is
prevents large input signal feedthrough across the input monitored by the power supply meter M. Thus, if the load
terminals of the CA3080A to the 200pF storage capacitor when current is 100nA, with values shown, the load current
the CA3080A is strobed off. Figure 24 shows dynamic presented to the supply will be 100µA; a much easier current
characteristic waveforms of this sample-and-hold system. to measure in many systems.
R1
10kΩ
+15V
R2
IL x 0.1µF
R1
7
3 + R2
M CA3140 6
10MΩ IL
2 - 4
0.1µF
POWER 1
SUPPLY 5 RL
100kΩ
Note that the input and output voltages are transferred at the
same potential and only the output current is multiplied by
the scale factor.
17 FN957.10
July 11, 2005
CA3140, CA3140A
R2 +15V
5kΩ +15V
0.1µF
10kΩ 7 SIMULATED
R1 0.1µF INPUT LOAD
3 +
2 - 7
10kΩ CA3140 6
CA3140 6
2 -
3 + 1N914 100pF 2kΩ
4 4
5 10kΩ
1
8 R3 0.1µF
PEAK
ADJUST
100kΩ -15V
10kΩ BW (-3dB) = 4.5MHz
OFFSET
SR = 9V/µs
ADJUST 2kΩ
R R3
GAIN = ------2- = X = ----------------------------
- 0.05µF
R1 R1 R2 + R3
2 FIGURE 28A. TEST CIRCUIT
R 3 = ----------------- R 1
X+X
1–X
5kΩ R
FOR X = 0.5 --------------- = ------2-
10kΩ R1
OUTPUT
0 Top Trace: Output; 50mV/Div., 200ns/Div.
Bottom Trace: Input; 50mV/Div., 200ns/Div.
INPUT FIGURE 28B. SMALL SIGNAL RESPONSE
0
+15V
0.01µF
RS 7
3 +
1MΩ NOISE VOLTAGE
CA3140 6
OUTPUT
2 -
4
(Measurement made with Tektronix 7A13 differential amplifier.)
30.1kΩ
0.01µF
-15V Top Trace: Output Signal; 5V/Div., 5µs/Div.
Center Trace: Difference Signal; 5mV/Div., 5µs/Div.
BW (-3dB) = 140kHz Bottom Trace: Input Signal; 5V/Div., 5µs/Div.
1kΩ
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48µV (TYP)
FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING
SETTLING TIME
FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR
WIDEBAND NOISE MEASUREMENT FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST
CIRCUIT AND ASSOCIATED WAVEFORMS
18 FN957.10
July 11, 2005
CA3140, CA3140A
10
TA = -55oC
OPEN-LOOP VOLTAGE GAIN (dB)
25oC 25oC
125
125oC 125oC
TA = -55oC
100
75
50
25
0 1
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY
VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE
RL = 2kΩ RL = ∞
CL = 100pF 7
QUIESCENT SUPPLY CURRENT (mA)
6
TA = -55oC
25oC 5 25oC
125oC
20 TA = -55oC 4 125oC
SLEW RATE (V/µs)
15 3
10 2
5 1
0 0
0 5 10 15 20 25 0 5 10 15 20 25
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY
TEMPERATURE VOLTAGE AND TEMPERATURE
TA = 25oC TA = 25oC
25 100
OUTPUT SWING (VP-P)
20 80
15 60
10 40
5 20
0 0
10K 100K 1M 4M 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY
FREQUENCY
19 FN957.10
July 11, 2005
CA3140, CA3140A
1000
SUPPLY VOLTAGE: VS = ±15V SUPPLY VOLTAGE: VS = ±15V
EQUIVALENT INPUT NOISE VOLTAGE (nV/√Hz)
TA = 25oC TA = 25oC
100
60
10 40 -PSRR
20
POWER SUPPLY REJECTION RATIO
(PSRR) = ∆VIO/∆VS
1 0
1 101 102 103 104 105 101 102 103 104 105 106 107
FREQUENCY (Hz) FREQUENCY (Hz)
FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FREQUENCY
20 FN957.10
July 11, 2005
CA3140, CA3140A
0 10 20 30 40 50 60 65
61
60
50
40
58-66
30 (1.473-1.676)
20
10
0
4-10
(0.102-0.254)
62-70
(1.575-1.778)
21 FN957.10
July 11, 2005
CA3140, CA3140A
N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
SEATING
B 0.014 0.022 0.356 0.558 -
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
22 FN957.10
July 11, 2005
CA3140, CA3140A
N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
INDEX
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B- SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L A1 0.0040 0.0098 0.10 0.25 -
-C-
E 0.1497 0.1574 3.80 4.00 4
µα e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6
N 8 8 7
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of α 0o 8o 0o 8o -
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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23 FN957.10
July 11, 2005