CHAPTER 1

INTRODUCTION

1.1 Introduction

In this chapter, we discuss the area of work of our project, our motivation to do this
project, our objectives and what targets we choose to achieve through this project.

This project involves working with Xilinx Spartan-6 FPGA. Spartan-6 devices are the
most cost-optimized FPGAs, offering industry leading connectivity features. Verilog is
primarily used as the hardware descriptive language in this project. Wireless
communication is among technology’s biggest contributions to mankind. Wireless
communication involves the transmission of information over a distance without help of
wires, cables or any other forms of electrical conductors. The transmitted distance can be
anywhere between a few meters (for example, a television’s remote control) and
thousands of kilometres (for example, radio communication).

1.2 Motivation

In today’s world, wireless communication plays an indispensible part in technology.

Every device, ranging from a small wireless mouse to a device as massive as a satellite,
uses wireless technology. FPGAs are hardware accelerated and hence provide a more
efficient and fast wireless communication module. At the end of the project, this module
is available as a library which can be easily included in a project for wireless
communication and this provides flexibility to use multiple algorithms and the users can
switch between them in real time without resetting the system based on their performance
and needs.

1.3 Objective of the work

Objective of this project is to develop a wireless communication module library that has
different algorithms for encryption/decryption, compression/expansion and
modulation/demodulation, from which the users can select the appropriate algorithms
depending on their performance and needs, in real time, without the need to reset the
entire system for the switch.

Secondary objective of this project is comparing the performance of the algorithms that
are implemented in this module.

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1.4 Timeline of work

Table 1.1 Project Timeline

2
 CHAPTER 2
BACKGROUND THEORY

2.1 Introduction

This chapter focuses on explaining the basic idea and theory behind all the concepts used
in this project.

2.2 Introduction to the project title

This wireless communication module takes in plaintext data to transmitted and then
prepares it for transmission. How this is done is that the data is first compressed, then
encrypted, then modulated and then finally given to a transmission circuit to be
broadcasted wirelessly. This module is a transceiver module which means it has both the
transmitter and receiver incorporated into it and hence can perform the reverse operation
after the data is received and convert it back to plaintext data.

2.3 Theoretical Discussions

Encryption is used to make sure that the data is secure from unauthorised access. Multiple
encryption algorithms have been implemented in this project. These will be explained in
detail in the next chapter.

Compression is used to compress the data into a smaller size so that it requires lesser
bandwidth and hence can be transmitted faster and more efficiently.

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 CHAPTER 3
METHODOLOGY

3.1 Introduction

In this chapter, a detailed methodology, that includes various algorithms, will be

explained along with the block diagram of the entire wireless communication system.
Detailed explanation of the components used and its functionality will also be explained
in addition to the software used for programming and deploying the HDL.

3.2 Methodology

The main electronic system used for this module is the FPGA. In specific, the Spartan-6
FPGA from Xilinx is used. The hardware descriptive language used is Verilog. This
Hardware descriptive language is used as it is simple and has a structure of C language.

The wireless communication module consists of the following subsystems:

3.2.1 Block Diagram

The block diagram of WiComm is as shown below.

Fig 3.1 Block Diagram for the WiComm module

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3.2.2 Encryption System

Various encryption algorithms have been implemented in this module such as SDES,
TEA and GOST. These algorithms are explained below.

3.2.2.1 SDES

Simple Data Encryption Standard is a block cipher. This is an algorithm that has
many features of the DES, but is much simpler then DES.

Fig 3.2 SDES Key Gen Block Fig 3.3 SDES Key Gen Block

In this algorithm two keys are generated using a key generator circuit and then
these keys are passed to the actual encryption block where the plaintext is passed
through a number of operations to generate a cipher text.

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3.2.2.2 TEA

Tiny Encryption Algorithm is also a block cipher notable for its simplicity of
description and implementation. This algorithm originally operates on two 32-bit
unsigned integers and uses a 128-bit encryption key. It has a Feistel structure with
a suggested 64 rounds but for the purpose of implementation in this project it has
been modified to operate on 8 bit data.

Fig. 3.4 TEA Feistel Structure

Only one block of two Feistel rounds has been used in the TEA encryption
module. It has an extremely simple key schedule, mixing all of the key material in
exactly the same way for each cycle. TEA has a few weaknesses. Most notably, it
suffers from equivalent keys—each key is equivalent to three others, which means
that the effective key size is only 126 bits. As a result, TEA is especially bad as a
cryptographic hash function.

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3.2.2.3 GOST

GOST has a 64-bit block size and a key length of 256 bits. GOST is a Feistel
network of 32 rounds. The S-boxes accept a four-bit input and produce a four-bit
output. The S-box substitution in the round function consists of eight 4 × 4 S-
boxes. The S-boxes are implementation-dependent – parties that want to secure
their communications using GOST must be using the same S-boxes. For extra
security, the S-boxes can be kept secret. Compared to DES, GOST has a very
simple round function.

However, the designers of GOST attempted to offset the simplicity of the round
function by specifying the algorithm with 32 rounds and secret S-boxes. Another
concern is that the avalanche effect is slower to occur in GOST than in DES. This
is because of GOST's lack of an expansion permutation in the round function, as
well as its use of a rotation instead of a permutation. Again, this is offset by
GOST's increased number of rounds.

This algorithm also for implementation purposes has been modified to work with
8 bit data. And the number of Feistel rounds has been reduced to allow reduction
in area required for synthesis.

Fig. 3.5 GOST Feistel Structure

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3.2.3 Compression System
The compression system includes the following algorithms explained below.

3.2.3.1 Simple String Compression

This algorithm was originally implemented for use in an SMS application. Using
this algorithm, it could send about 256 characters per message (typically 160
characters per message) through the same 7-bit GSM network. The idea is, this
program reduces the standard 7-bit encoding to some application specific 5-bit
encoding system and then pack into a byte array. This method will reduce the size
of a string considerably when the string is lengthy and the compression ratio is not
affected by the content of the string.

Encoding

Consider a string with 8 characters (example: - “abcdefgh”). If this is put on a byte

array, the data will be a byte array with the size of 8. The following diagram
shows how these ASCII characters can store in an array.

|97|98|99|100|101|102|103|104|

A single character will need 8 bits if the characters are represented with ASCII. A
set of 8 bits can represent 256 different characters. But if we consider the current
application, a simple SMS might be included only around 26 different characters.
Therefore it is enough to have 5-bit encoding which can give up to 32 different
characters to represent. For conversion to 5-bit, new values are assigned to the
above characters.

| a = 1 | b=2 | c=3 | d=4 | e=5 | f=6 | g=7 | h=8 |

Rewriting in binary the new byte array will look like the following (the values of
characters are in binary representation).

00000001|00000010|00000011|00000100|00000101|00000110|00000111|00001000|

In the next step, each byte from the position of 3rd bit from the left side are
chopped and 5 least significant bits are extracted. The result is as follows:

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|00001|00010|00011|00100|00101|00110|00111|01000|

These bits can be rearranged to form bytes as shown below.

|00001000|10000110|01000010|10011000|11101000|

Hence 8 bytes are reduced to 5 bytes.

Decoding

When an array of bytes is given, each byte should be represented in to binary.

Then all the 1’s and 0’s should be arranged as their index and then can be split to
the sets of five bits. After splitting, it will be as follows:

|00001 000|10 00011 0|0100 0010|1 00110 00|111 01000|

These sets can be converted to decimals and these values represent the characters
that we have encoded.

|00001 = 1(a)
000|10 = 2 (b)
00011 = 3(c)
0|0100 = 4 (d)
0010|1 = 5 (e)
00110 = 6 (f)
00|111 = 7 (g)
01000| = 8 (h)

Then the information can be decoded as “abcdefgh”.

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3.2.4 Data Acquisition System

Two methods of data acquisition are used to provide data that will be transmitted.

3.2.4.1 Alphabet Generator

This is a system which periodically generates alphabets. These alphabets can be

sent to the communication system to be compressed and encrypted. It generates
ASCII values of upper case alphabets.

3.2.4.2 ADC Analog to Digital Converter

The on-board ADC is used to generate data for transmission. A mux can be used
to switch between ADC data or alphabet generator. The on-board ADC has a
resolution of 8 bits and can measure voltages between 0 to 3.3 volts. The value of
the ADC can be changed by use of a potentiometer which is also provided on the
FPGA kit.

3.2.5 LCD Display Module

LCD is used to display various details about the system state such as the
encryption algorithm under use, data input, data output etc.

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3.2.6 UART Communication System

UART is a method of asynchronous communication. PuTTY is used on the laptop to

send information to the board. This enables the use of a serial command line interface
to send data and instructions to the FPGA in addition to the switches available on
board. It is configured to use a baud rate of 250 KHz.

The UART communication module is custom coded in Verilog and it reads data in a
SIPO (Serial In Parallel Out) manner along with one start bit which is a low bit and
one stop bit which again is a low bit, in the idle state the RX line is pulled to a high
logic level. No parity bits are used.

Fig. 3.6 UART Protocol Specification

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 CHAPTER 4
RESULT ANALYSIS

4.1 Result Analysis

Compression is done using simple string compression in 5 and 6 bit modes. The
simulation result for the 6 bit mode is given below.

Fig. 4.1 Simple String Compression in 6 bit mode simulation output

Given below is the overview of the Spartan 6 board showing the switches, LED’s and
the LCD Module displaying the various details about the state of the machine at the
current moment.

Fig 4.2 Overview of the FPGA kit

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Fig. 4.3 LCD Module Close-up

Fig. 4.4 LCD Module Close-up

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 CHAPTER 5
CONCLUSION AND FUTURE SCOPE OF WORK

5.1 Brief Summary

The problem statement defined for out project is to create a portable easy to use wireless
communication module library that can be implemented on FPGA.

5.2 Conclusions

The WiComm module provides a very efficient and flexible environment to those who
wish to employ wireless communication in their FPGA projects without the hassles of
coding it from scratch. Flexibility is provided in terms of choice of the various algorithms
implemented.

5.3 Future Scope of Work

• Compression algorithms
– Adaptive Huffman
– LZ77
– DEFLATE
• Advanced UART interface with bidirectional communication
• Enhanced LCD UI
• Modulation/Demodulation algorithms
• Transmission Circuit Development

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 REFERENCES

1. L. Fu and M. Pan, "A Simplified FPGA Implementation Based on an Improved DES

Algorithm," 2009 Third International Conference on Genetic and Evolutionary
Computing, Guilin, 2009, pp.227-230. doi: 10.1109/WGEC.2009.11
2. M. A. Hussain and R. Badar, "FPGA Based Implementation Scenarios of TEA Block
Cipher," 2015 13th International Conference on Frontiers of Information Technology
(FIT), Islamabad, 2015, pp. 283-286. doi: 10.1109/FIT.2015.56
3. Srinivas, N.S Sai, and MD Akramuddin. "FPGA Based Hardware Implementation of AES
Rijndael Algorithm for Encryption and Decryption.".
4. Ms. Neha Khatri and Prof. V. K. Kshirsagar ‘Blowfish Algorithm’, Volume 16, Issue 2,
Ver. X, Mar-April 2014

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 ANNEXURES

WiComm Top Module Code

`timescale 1ns / 1ps

module WiCommMaster(
input clk,
input alen_in,
input serial_override,
input data_sel, //1 = alpha 0 = adc
input text_mode_sel_in,
input [7:0]adc_pins,
input adc_intr,
input [1:0]enc_sel_in,
input enc_dec_sel_in,
input serial_in,
output rs,
output adc_wr,
output en,
output [7:0]lcd_data_out,
output [7:0]outsig
);

wire divided_clk;
wire [7:0]adc_val;
wire [7:0]alpha;
wire [7:0]data_to_use; //data_sel decides this
reg [1:0]enc_sel;
reg enc_dec_sel;
reg alen;

reg [7:0]serial_data;
wire [7:0]serial_data_wr;
wire ser_data_avail;

reg [1:0]enc_sel_ser;
reg enc_dec_sel_ser;
reg alen_ser;
reg [4:0]ser_cmd = 0;

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 integer enc_sel_ser_var=0;

reg [9:0]sdes_key;
reg [7:0]tea_key;
reg [3:0]gost_key;

wire [7:0]sdes_enc_data;
wire [7:0]sdes_dec_data;

wire [7:0]tea_enc_data;
wire [7:0]tea_dec_data;

wire [7:0]gost_enc_data;
wire [7:0]gost_dec_data;

wire [7:0]encrypted;
wire [7:0]decrypted;

wire [7:0]lcd_data;
reg [7:0]lcd_data_reg ;
wire [7:0]lcd_pos;
reg [7:0]lcd_pos_reg ;

reg [7:0] string [0:15] =

{8'h43,8'h55,8'h52,8'h52,8'h45,8'h4e,8'h54,8'h3a,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'
h20};
reg [7:0] string2 [0:15] =
{8'h45,8'h4e,8'h43,8'h52,8'h59,8'h50,8'h54,8'h45,8'h44,8'h3a,8'h20,8'h20,8'h20,8'h20,8'h20,8'
h20};
reg [7:0] string3 [0:15] =
{8'h44,8'h45,8'h43,8'h52,8'h59,8'h50,8'h54,8'h45,8'h44,8'h3a,8'h20,8'h20,8'h20,8'h20,8'h20,8'
h20};

parameter MEM_SIZE = 16;

integer textmode;
reg [7:0] text_mode_str [0:15] =
{8'h54,8'h45,8'h58,8'h54,8'h20,8'h4d,8'h4f,8'h44,8'h45,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'
h20};
reg [7:0] text_data [0:MEM_SIZE-1] =
{8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'
h20};

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reg [3:0] text_read_index;
integer k;

initial begin
sdes_key = 10'b0111010001;
tea_key = 8'h2c;
//gost_key = 4'he;

lcd_data_reg = 8'h41;
lcd_pos_reg = 8'h80;

//serial_data = "-";

enc_sel_ser = 2'd0;
enc_dec_sel_ser = 1'b0;

enc_sel = enc_sel_in;
enc_dec_sel = enc_dec_sel_in;
alen = alen_in;

textmode = 0;
text_read_index = 0;

for(k=0; k<MEM_SIZE; k = k+1) begin

text_data[k] = 8'h20;
end

end

always @ (*) begin

serial_data = serial_data_wr;
end

always @ (serial_override) begin

if(serial_override == 1'b0) begin
enc_sel = enc_sel_in;
enc_dec_sel = enc_dec_sel_in;
alen = alen_in;
end
if(serial_override == 1'b1) begin
enc_sel = enc_sel_ser;

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 enc_dec_sel = enc_dec_sel_ser;
alen = alen_ser;
end
end

always @ (serial_data) begin

string2[15] = serial_data;
string3[15] = serial_data;

enc_sel_ser = enc_sel_ser_var;

if(textmode == 0) begin
case (serial_data)

"1": begin ser_cmd = ser_cmd & 5'b10011; end

"2": begin
ser_cmd = ser_cmd & 5'b10111;
ser_cmd = ser_cmd | 5'b00100;
end
"3": begin
ser_cmd = ser_cmd | 5'b01000;
ser_cmd = ser_cmd & 5'b11011;

end
"4": begin ser_cmd = ser_cmd | 5'b01100; end

"e": begin ser_cmd = ser_cmd & 5'b11101; end

"d": begin ser_cmd = ser_cmd | 5'b00010; end

"q": begin ser_cmd = ser_cmd | 5'b10000; end

"w": begin ser_cmd = ser_cmd & 5'b01111; end

"t": begin
text_read_index = 0;
textmode = 1;

text_mode_str[5] = 8'h4d;
text_mode_str[6] = 8'h4f;
text_mode_str[7] = 8'h44;
text_mode_str[8] = 8'h45;

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 end

"y": begin textmode = 0; end

default: ser_cmd = ser_cmd & 5'b11111;

endcase

enc_sel_ser = {ser_cmd[3],ser_cmd[2]};
enc_dec_sel_ser = ser_cmd[1];
alen_ser = ser_cmd[4];
end

else begin
if(textmode == 1 && text_read_index <= 15 && serial_data != "`")
begin
text_data[text_read_index] = serial_data;
text_read_index = text_read_index + 1;
end

if(text_read_index > 15 || serial_data == "`") begin

textmode = 0;
text_mode_str[5] = 8'h52;
text_mode_str[6] = 8'h45;
text_mode_str[7] = 8'h41;
text_mode_str[8] = 8'h44;
end

end
end

always @ (data_to_use or data_sel) begin

if(data_sel == 1) begin
string[9] = data_to_use;

string[0] = "A";
string[1] = "L";
string[2] = "P";
string[3] = "H";
string[4] = "A";

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 string[5] = " ";
string[6] = " ";
string[10] = " ";
end
else begin
string[9] = data_to_use[7:4] + 8'h30;
string[10] = data_to_use[3:0] + 8'h30;

if(string[9] > 8'h39) begin string[9] = string[9] + 7; end

if(string[10] > 8'h39) begin string[10] = string[10] + 7; end

string[0] = "A";
string[1] = "D";
string[2] = "C";
string[3] = " ";
string[4] = " ";
string[5] = " ";
string[6] = " ";
end
end

always @ (outsig or enc_dec_sel) begin

if(enc_dec_sel == 0) begin
string2[11] = outsig;
//string2[15] = serial_data;
end
else begin
if(data_sel == 1) begin
string3[11] = outsig;
string3[12] = " ";

//string3[15] = serial_data;
end
else begin
string3[11] = outsig[7:4] + 8'h30;
string3[12] = outsig[3:0] + 8'h30;

//string3[15] = serial_data;

if(string3[11] > 8'h39) begin string3[11] = string3[11] + 7; end

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 if(string3[12] > 8'h39) begin string3[12] = string3[12] + 7; end
end

if(enc_sel == 3) begin
string3[11] = "-";
string3[12] = " ";

//string3[15] = serial_data;
end
end

case(enc_sel)
0: begin
string[11] = " ";
string[12] = "S";
string[13] = "D";
string[14] = "E";
string[15] = "S";

end
1: begin
string[11] = " ";
string[12] = " ";
string[13] = "T";
string[14] = "E";
string[15] = "A";
end
2: begin
string[11] = " ";
string[12] = "G";
string[13] = "O";
string[14] = "S";
string[15] = "T";
end

default: begin
string[11] = " ";
string[12] = "N";
string[13] = "U";
string[14] = "L";
string[15] = "L";

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 end
endcase
end

assign lcd_data = lcd_data_reg;

assign lcd_pos = lcd_pos_reg;

integer index = 0;
integer index2 = 0;
integer lcd_clk_divider = 0;

//LCD writer
always @ (posedge clk) begin

lcd_clk_divider = lcd_clk_divider + 1;

if(lcd_clk_divider > 40000) begin

if(textmode == 0) begin
if(index < 16 ) begin
lcd_pos_reg = 8'h80 + index;
lcd_data_reg = string[index];
end
else begin
lcd_pos_reg = 8'hc0 + index - 16;
lcd_data_reg = (enc_dec_sel) ? string3[index-
16]:string2[index-16];
end

index = index + 1;

if(index > 31) begin

index = 0;
end
end
else begin
if(index2 < 16 ) begin
lcd_pos_reg = 8'h80 + index2;
lcd_data_reg = text_mode_str[index2];
end
else begin

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 lcd_pos_reg = 8'hc0 + index2 - 16;
lcd_data_reg = /*(enc_dec_sel) ? string3[index2-
16]:*/text_data[index2-16];
end

index2 = index2 + 1;

if(index2 > 31) begin

index2 = 0;
end
end

lcd_clk_divider = 0;
end
end

ClockDivider(clk,divided_clk);
AphaGen(divided_clk,alen,alpha);

Encrypter_SDES(clk,data_to_use,sdes_key,sdes_enc_data);
Decrypter_SDES(clk,sdes_enc_data,sdes_key,sdes_dec_data);
Encrypter_TEA(clk,data_to_use,tea_key,tea_enc_data);
Decrypter_TEA(clk,tea_enc_data,tea_key,tea_dec_data);
Encrypter_GOST(clk,data_to_use,gost_key,gost_enc_data);
Decrypter_GOST(clk,gost_enc_data,gost_key,gost_dec_data);

Mux41(sdes_enc_data,tea_enc_data,gost_enc_data,"-",enc_sel,encrypted);
Mux41(sdes_dec_data,tea_dec_data,gost_dec_data,"-",enc_sel,decrypted);
Mux21(encrypted,decrypted,enc_dec_sel,outsig);
//assign outsig = {3'b000,ser_cmd};
Mux21(adc_val,alpha,data_sel,data_to_use);

LCDModule(clk,lcd_pos,lcd_data,rs,en,lcd_data_out);
ADCInputModule(clk,adc_pins,adc_intr,adc_wr,adc_val);

UART_Rx_Module(clk,serial_in,ser_data_avail,serial_data_wr);
endmodule

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 PROJECT DETAILS

Student Details
Student Name Shiv Narain Capoor
Register Number 130907490 Section / Roll No A/39
Email Address shivcapoor95@gmail.com Phone No (M) 7795164488
Student Name Muktha Padakandla
Register Number 130907028 Section / Roll No A/6
Email Address muktha95@gmail.com Phone No (M) 8495876186
Student Name Anushka Sinha
Register Number 130907472 Section / Roll No A/37
Email Address aditianu1995@gmail.com Phone No (M) 8904851736
Project Details
Project Title WiComm- Wireless Communication module for FPGA
Project Duration 6 months Date of reporting 10-01-2017
Organization Details
Organization Name Manipal Institute of Technology
Full postal address with Manipal Institute of Technology, Madhav Nagar, Manipal-576104
pin code Udupi, Karnataka
Website address www.manipal.edu

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