Microprocessor Systems (Lecture) Quiz 2

(SetA) 1st Quarter SY 2019-2020

Multiple Choice
Identify the choice that best completes the statements or answers the question.

_D_ 1. Which is not goal of RISC?

a. Pipelining everything c. Reduce accesses to main memory
b. Utilize the compiler extensively d. Make instructions to multi-task
_D_ 2. Which is/are improvement(s) of Pentium Pro over Pentium?
a. CPU3 b. L2 cache c. double-sized L1 cache d. both a and b
_A_ 3. MMX instructions can process

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a. integer data only b. floating point number c. both a and b

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_A_ 4. Pentium can run _____ instructions concurrently.

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a. 2 b. 3 c. 4 d. 5

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5. Which of the following is a special bus cycle?
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a. Code read, 256 bits burst Line Fill c. Interrupt Acknowledge (2 locked cycles)
b. I/O write, 32-bits or less, Non-cacheable d. Halt
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_B_ 6. Intel Pentium’s microarchitechture is known as

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a. 80586 b. P5 c. Netburst d. Willamette

_B_ 7. The following are new flags bits made available in Pentiums except for
a. ID b. VM c. AC d. VIP
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_A_ 8. An internal parity error is detected by the Pentium allowing the _____ to run
a. Shutdown b. Halt c. Pipelined d. Inquire
_C_ 9. It is a technique used to enable one instruction to complete with each clock cycle
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a. RISC b. Burst c. Pipelining d. Micro-op

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_D_ 10. Which of the following is NOT a Pentium's Special Cycle?

a. Shutdown b. Flush c. Halt d. 256 bit Burst Write Back
_B_ 11. Bus _____ input provides a second way for a different bus master to take control of the Pentium's
buses.
a. BOFF b. HOLD c. INTR d. FLUSH
_D_ 12. These are all component of NetBurst Architecture EXCEPT
a. Hyper Piped Line Technology c. Execution Trace Cache
b. Rapid Execution Engine d. Executive Engine Line

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 _A_ 13. Which of the following is an invalid Pentium Bus Address?
a. 0000 0005H b. 0000 0008H c. 0000 0010H d. 0000 0020H
_D_ 14. Indicates to the Pentium whether or not the system can support a cache line fill for the current cycle
a. CACHE# b. HIT# c. HITM# d. KEN#
_C_ 15. Which is not a feature of the Pentium II?
a. MMX b. Reservation station c. SSE d. 242-pin SECC
_C_ 16. Which processor is influenced by the EPIC philosophy?
a. Pentium 4 b. Xeon c. Itanium d. Celeron
_A_ 17. Which is examined first when processor need to read data from main memory?
a. Cache b. Memory c. Stack d. Register
_C_ 18. Processors capable of parallel execution of multiple instructions are called _____ machines.

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a. Dual-load b. Parallelized c. Superscalar d. Multi-core

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_D_ 19. This Pentium signal provides even parity for the memory address on all Pentium initiated memory

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and I/O transfers;

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a. BUSCHK
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_D_ 20. Which has no L2 cache?
a. Pentium b. Pentium MMX c. Celeron d. All of the choices
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_A_ 21. Branch prediction is assisted by the use of

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a. History bits b. Branch priority c. Prediction arrays d. speculative execution

_D_ 22. All of the following belongs to P6 microarchitecture family except
a. Pentium Pro b. Celeron c. Pentium 3 d. Pentium 4
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_B_ 23. Pentiums' superscalar architecture means

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a. it can make predictions on next instruction to be executed c. it has separate Code and Data Caches
b. it can execute more than one instruction at a time d. all of the above
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_A_ 24. This cycle is used to transfer up to 8 bytes of non-cacheable data between the processor and
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memory
a. Single-transfer b. Burst c. LOCK d. BOFF
_B_ 25. Choosing to make the instruction set smaller using fewer instructions and simpler addressing codes
was the decision of _____ designers
A. Computer B. RISC C. CISC D. System
_A_ 26. It controls the access to the system buses by generating memory address and control signals, and
passes and fetches data or instructions to either a level 1 data cache or a level 1 instruction cache
a. BIU b. IFU c. DU d. FPU
_B_ 27. Which microprocessor has integrated (on-die) L2 cache?
a. Pentium b. Pentium Pro c. Pentium 2 d. Celeron
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 _C_ 28. Which has 36-bit address bus and therefore can access 64GB of memory
a. 80486 b. Pentium c. Pentium Pro d. Both b and c
_A_ 29. The following microprocessors are all 3-way superscalar except
a. Pentium b. Pentium 2 c. Pentium 3 d. Celeron
_D_ 30. Which CPU supports RAMBUS memory technology
a. Pentium b. Pentium II c. Pentium III d. Pentium 4
_A_ 31. It provides a way for other processors in a multiprocessor system to instantly take over the
Pentium's buses.
a. BOFF b. Shutdown c. Bus Hold d. HALT
_A_ 32. Indicates that a new valid bus cycle is currently being driven by the Pentium processor
a. ADS# b. BRDY# c. EADS# d. PRDY#

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_B_ 33. All of the following Pentiums has 64-bit data bus except

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a. Pentium b. Pentium Overdrive c. Pentium Pro d. Pentium II

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_D_ 34. SSE2 is first introduced in

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a. Pentium Pro
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_B_ 35. The following features are first introduced in Intel Pentium processor except
a. Superscalar Capability b. Cache Memory c. Branch Predictions d. None of the Choices
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_C_ 36. Pentium Pro's IFDU contains how many separate instruction decoders for simultaneous decoding
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a. 5 b. 4 c. 3 d. 2
_D_ 37. When two instructions are to be paired for parallel execution, both instruction must _____
a. Must Lack Dependencies b. Must be simple c. Must Contain No Displacement d. All of the above
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_C_ 38. It allows a new 8-byte chunk to transfer every clock cycle.
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a. Bus operation b. Pipelining c. Burst Operation d. Branch Operation

_D_ 39. Which is not a component of Dynamic Execution
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a. Multiple Branch Prediction c. Speculative Execution

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b. Data Flow Analysis d. none of the choices

_B_ 40. This is an implementation technique where multiple instructions are overlapped in execution?
a. Super scaling b. Pipelining c. RISC d. CISC
_A_ 41. Which instruction is NOT new Pentium instructions?
a. CMPXCHG b. CPUID c. WRMSR d. RSM
_D_ 42. The state in which data requested for processing by a component or application is found in the
cache memory?
a. Cache fluff b. Cache miss c. Cache drop d. Cache hit

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 True/False
Write T if the statement is True and F if the statement is False

_F_ 43. A Burst Cycle transfers a maximum of 64 bits for a minimum of 2 clocks
_T_ 44. Cache is used to reduce access to main memory
_F_ 45. Pentium’s address lines are named A31:A0
_F_ 46. Pentium 4’s pipelines has 14 stages
_F_ 47. Pentium is Intel’s first 64-bit microprocessor having a data bus that is 64-bit wide
_T_ 48. At any time, an instruction pipeline may have multiple instructions in different stages of processing
_F_ 49. Pentium’s U-pipeline executes only simple instructions while V-pipeline can execute any processor
instruction

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_T_ 50. For the Pentium, all cache operations are burst cycles

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_T_ 51. After a cache miss, there could be no another miss for the same data read from main memory

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_F_ 52. The Pentium is a pure RISC machine

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53. Pentium is a 32-bit microprocessor
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_T_ 54. Instructions are executed out of order in speculative execution
_T_ 55. The I- and D-caches of Pentium are both two-way associative
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_F_ 56. There are only four types of bus cycles in the Pentium
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57. Pentium PRO is Intel’s first sixth generation processor

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_T_
_T_ 58. The reduced set of operations in RISC is easier to implement on silicon, resulting faster
performance
ed d

_F_ 59. Pentium’s standard Single Transfer Cycle can read or write up to 32 bytes at a time
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 Problem
60. Fill the table to show the activated BE# signals, Locations Accessed and Addresses placed on
Address Bus for the following memory accesses
1) 1 word starting at 0A3DF00D
2) 1 byte starting at 12301004
3) 1 word starting at FE025600
4) 1 double word starting at 80001002
5) 1 word starting at 0A32080E

7 6 5 4 3 2 1 0
F E D C B A 9 8

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Address on the Bus BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# Accessed Locations

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0A3DF008 1 0 0 1 1 1 1 1 0A3DF00D, 0A3DF00E

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12301000 1 1 1 0 1 1 1 1 12301004

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FE025600 1 1 1 1 1 1 0 0 FE025600, FE025601
80001000 1 1rs e0 0 0 0 1 1 80001002-80001005
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0A320808 0 0 1 1 1 1 1 1 0A32080E, 0A32080F
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ed d
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