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A 10-bit LNA
M IREF PCA PRO
U
300 ksps Serial
Timer 0
X ADC Interface PA
+ +
Timer 1
Timer 2 Port 1
VREF
TEMP – – Timer 3 Mixer
SENSOR VREG VOLTAGE CRC Port 2 PGA
COMPARATORS ADC
24.5 MHz PRECISION 20 MHz LOW POWER
INTERNAL OSCILLATOR INTERNAL OSCILLATOR
Digital
External Oscillator HARDWARE smaRTClock Modem PLL
2 Rev. 0.2
Si1000/1/2/3/4/5
Table of Contents
1. System Overview ..................................................................................................... 16
1.1. Typical Connection Diagram ............................................................................. 20
1.2. CIP-51™ Microcontroller Core .......................................................................... 21
1.3. Port Input/Output ............................................................................................... 22
1.4. Serial Ports ........................................................................................................ 23
1.5. Programmable Counter Array............................................................................ 23
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode............................................................................................... 24
1.7. Programmable Current Reference (IREF0)....................................................... 25
1.8. Comparators...................................................................................................... 25
2. Ordering Information ............................................................................................... 27
3. Pinout and Package Definitions ............................................................................. 28
4. Electrical Characteristics ........................................................................................ 38
4.1. Absolute Maximum Specifications..................................................................... 38
4.2. MCU Electrical Characteristics .......................................................................... 39
4.3. EZRadioPRO® Electrical Characteristics .......................................................... 64
4.4. Definition of Test Conditions for the EZRadioPRO Peripheral .......................... 71
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low
Power Burst Mode ....................................................................................................... 72
5.1. Output Code Formatting .................................................................................... 72
5.2. Modes of Operation ........................................................................................... 74
5.3. 8-Bit Mode ......................................................................................................... 78
5.4. Programmable Window Detector....................................................................... 85
5.5. ADC0 Analog Multiplexer .................................................................................. 88
5.6. Temperature Sensor.......................................................................................... 90
5.7. Voltage and Ground Reference Options ........................................................... 93
5.8. External Voltage References............................................................................. 93
5.9. Internal Voltage References .............................................................................. 94
5.10. Analog Ground Reference............................................................................... 94
5.11. Temperature Sensor Enable ........................................................................... 94
5.12. Voltage Reference Electrical Specifications .................................................... 95
6. Programmable Current Reference (IREF0)............................................................ 96
6.1. IREF0 Specifications ......................................................................................... 96
7. Comparators............................................................................................................. 97
7.1. Comparator Inputs............................................................................................. 97
7.2. Comparator Outputs .......................................................................................... 98
7.3. Comparator Response Time ............................................................................. 99
7.4. Comparator Hysteresis...................................................................................... 99
7.5. Comparator Register Descriptions .................................................................. 100
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 104
8. CIP-51 Microcontroller........................................................................................... 107
8.1. Performance .................................................................................................... 107
8.2. Programming and Debugging Support ............................................................ 108
Rev. 0.2 3
Si1000/1/2/3/4/5
4 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 5
Si1000/1/2/3/4/5
6 Rev. 0.2
Si1000/1/2/3/4/5
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control ................................................................ 79
SFR Definition 5.2. ADC0CF: ADC0 Configuration ...................................................... 80
SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration ................................. 81
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time ............................ 82
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time ....................................... 83
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte ............................................ 84
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte .............................................. 84
SFR Definition 5.8. ADC0GTH: ADC0 Greater-Than High Byte ................................... 85
SFR Definition 5.9. ADC0GTL: ADC0 Greater-Than Low Byte .................................... 85
SFR Definition 5.10. ADC0LTH: ADC0 Less-Than High Byte ...................................... 86
SFR Definition 5.11. ADC0LTL: ADC0 Less-Than Low Byte ........................................ 86
SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select ........................................ 89
SFR Definition 5.13. TOFFH: ADC0 Data Word High Byte .......................................... 92
SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte ............................................ 92
SFR Definition 5.15. REF0CN: Voltage Reference Control .......................................... 95
SFR Definition 6.1. IREF0CN: Current Reference Control ........................................... 96
SFR Definition 7.1. CPT0CN: Comparator 0 Control .................................................. 100
SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection .................................... 101
SFR Definition 7.3. CPT1CN: Comparator 1 Control .................................................. 102
SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection .................................... 103
SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select ............................. 105
SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select ............................. 106
SFR Definition 8.1. DPL: Data Pointer Low Byte ........................................................ 113
SFR Definition 8.2. DPH: Data Pointer High Byte ....................................................... 113
SFR Definition 8.3. SP: Stack Pointer ......................................................................... 114
SFR Definition 8.4. ACC: Accumulator ....................................................................... 114
SFR Definition 8.5. B: B Register ................................................................................ 114
SFR Definition 8.6. PSW: Program Status Word ........................................................ 115
SFR Definition 10.1. EMI0CN: External Memory Interface Control ............................ 120
SFR Definition 11.1. SFR Page: SFR Page ................................................................ 123
SFR Definition 12.1. IE: Interrupt Enable .................................................................... 131
SFR Definition 12.2. IP: Interrupt Priority .................................................................... 132
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 ............................................ 133
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 ............................................ 134
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2 ............................................ 135
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2 ............................................ 136
SFR Definition 12.7. IT01CF: INT0/INT1 Configuration .............................................. 138
SFR Definition 13.1. PSCTL: Program Store R/W Control ......................................... 145
SFR Definition 13.2. FLKEY: Flash Lock and Key ...................................................... 146
SFR Definition 13.3. FLSCL: Flash Scale ................................................................... 147
SFR Definition 13.4. FLWR: Flash Write Only ............................................................ 147
SFR Definition 14.1. PMU0CF: Power Management Unit Configuration1,2 ....................... 153
SFR Definition 14.2. PCON: Power Management Control Register ........................... 154
SFR Definition 15.1. CRC0CN: CRC0 Control ........................................................... 158
Rev. 0.2 7
Si1000/1/2/3/4/5
8 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 9
Si1000/1/2/3/4/5
List of Figures
Figure 1.1. Si1000 Block Diagram ........................................................................... 17
Figure 1.2. Si1001 Block Diagram ........................................................................... 17
Figure 1.3. Si1002 Block Diagram ........................................................................... 18
Figure 1.4. Si1003 Block Diagram ........................................................................... 18
Figure 1.5. Si1004 Block Diagram ........................................................................... 19
Figure 1.6. Si1005 Block Diagram ........................................................................... 19
Figure 1.7. Si1002/3 RX/TX Direct-tie Application Example .................................... 20
Figure 1.8. Si1000/1 Antenna Diversity Application Example ................................. 20
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 22
Figure 1.10. PCA Block Diagram ............................................................................. 23
Figure 1.11. ADC0 Functional Block Diagram ......................................................... 24
Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 25
Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 26
Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 26
Figure 3.1. Si1000/1/2/3 Pinout Diagram (Top View) .............................................. 32
Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 33
Figure 3.3. QFN-42 Package Drawing .................................................................... 34
Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 36
Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 43
Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 44
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V ... 45
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 46
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 47
Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 48
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 50
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 51
Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 52
Figure 4.11. Typical VOL Curves, 0.9–1.8 V ........................................................... 54
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 72
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 75
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 76
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 77
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 87
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 87
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 88
Figure 5.8. Temperature Sensor Transfer Function ................................................ 90
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 91
Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 93
Figure 7.1. Comparator 0 Functional Block Diagram .............................................. 97
Figure 7.2. Comparator 1 Functional Block Diagram .............................................. 98
Figure 7.3. Comparator Hysteresis Plot .................................................................. 99
Figure 7.4. CPn Multiplexer Block Diagram ........................................................... 104
Figure 8.1. CIP-51 Block Diagram ......................................................................... 107
10 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 11
Si1000/1/2/3/4/5
12 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 13
Si1000/1/2/3/4/5
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 27
Table 3.1. Pin Definitions for the Si1000/1/2/3/4/5 .................................................. 28
Table 3.2. QFN-42 Package Dimensions ................................................................ 35
Table 3.3. PCB Land Pattern ................................................................................... 37
Table 4.1. Absolute Maximum Ratings .................................................................... 38
Table 4.2. Global Electrical Characteristics ............................................................. 39
Table 4.3. Port I/O DC Electrical Characteristics ..................................................... 49
Table 4.4. Reset Electrical Characteristics .............................................................. 55
Table 4.5. Power Management Electrical Specifications ......................................... 56
Table 4.6. Flash Electrical Characteristics .............................................................. 56
Table 4.7. Internal Precision Oscillator Electrical Characteristics ........................... 57
Table 4.8. Internal Low-Power Oscillator Electrical Characteristics ........................ 57
Table 4.9. ADC0 Electrical Characteristics .............................................................. 58
Table 4.10. Temperature Sensor Electrical Characteristics .................................... 59
Table 4.11. Voltage Reference Electrical Characteristics ....................................... 59
Table 4.12. IREF0 Electrical Characteristics ........................................................... 60
Table 4.13. Comparator Electrical Characteristics .................................................. 61
Table 4.14. DC-DC Converter (DC0) Electrical Characteristics .............................. 63
Table 4.15. VREG0 Electrical Characteristics ......................................................... 63
Table 4.16. DC Characteristics1 .................................................................................................... 64
Table 4.17. Synthesizer AC Electrical Characteristics1 ........................................................ 65
Table 4.18. Receiver AC Electrical Characteristics1 ............................................... 66
Table 4.19. Transmitter AC Electrical Characteristics1 ........................................................ 67
Table 4.20. Auxiliary Block Specifications1 ............................................................................... 68
Table 4.21. Digital IO Specifications (nIRQ) ............................................................................. 69
Table 4.22. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ................................ 69
Table 4.23. Absolute Maximum Ratings .................................................................. 70
Table 8.1. CIP-51 Instruction Set Summary .......................................................... 109
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0) ............... 121
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF) ............... 122
Table 11.3. Special Function Registers ................................................................. 123
Table 12.1. Interrupt Summary .............................................................................. 129
Table 13.1. Flash Security Summary .................................................................... 141
Table 14.1. Power Modes ...................................................................................... 148
Table 15.1. Example 16-bit CRC Outputs ............................................................. 156
Table 16.1. IPeak Inductor Current Limit Settings ................................................. 163
Table 19.1. Recommended XFCN Settings for Crystal Mode ............................... 181
Table 19.2. Recommended XFCN Settings for RC and C modes ......................... 182
Table 20.1. SmaRTClock Internal Registers ......................................................... 188
Table 20.2. SmaRTClock Load Capacitance Settings .......................................... 194
Table 20.3. SmaRTClock Bias Settings ................................................................ 196
Table 21.1. Port I/O Assignment for Analog Functions ......................................... 206
Table 21.2. Port I/O Assignment for Digital Functions ........................................... 207
14 Rev. 0.2
Si1000/1/2/3/4/5
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions .... 207
Table 22.1. Serial Interface Timing Parameters .................................................... 227
Table 22.2. SPI Timing Parameters ...................................................................... 235
Table 23.1. EZRadioPRO Operating Modes ......................................................... 237
Table 23.2. EZRadioPRO Operating Modes Response Time ............................... 238
Table 23.3. Frequency Band Selection ................................................................. 243
Table 23.4. Packet Handler Registers ................................................................... 262
Table 23.5. Minimum Receiver Settling Time ........................................................ 264
Table 23.6. POR Parameters ................................................................................ 267
Table 23.7. Temperature Sensor Range ............................................................... 270
Table 23.8. Antenna Diversity Control ................................................................... 276
Table 1. EZRadioPRO Internal Register Descriptions ........................................... 281
Table 23.1. SMBus Clock Source Selection .......................................................... 287
Table 23.2. Minimum SDA Setup and Hold Times ................................................ 288
Table 23.3. Sources for Hardware Changes to SMB0CN ..................................... 292
Table 23.4. Hardware Address Recognition Examples (EHACK = 1) ................... 293
Table 23.5. SMBus Status Decoding With Hardware ACK Generation Disabled
(EHACK = 0) ....................................................................................... 302
Table 23.6. SMBus Status Decoding With Hardware ACK Generation Enabled
(EHACK = 1) ....................................................................................... 304
Table 24.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator .............................................. 312
Table 24.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator ......................................... 312
Table 25.1. SPI Slave Timing Parameters ............................................................ 325
Table 26.1. Timer 0 Running Modes ..................................................................... 328
Table 27.1. PCA Timebase Input Options ............................................................. 349
Table 27.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Mod-
ules ..................................................................................................... 351
Table 27.3. Watchdog Timer Timeout Intervals1 ................................................... 361
Rev. 0.2 15
Si1000/1/2/3/4/5
1. System Overview
Si1000/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted features
are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
16 Rev. 0.2
Si1000/1/2/3/4/5
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
Engine GND PGA
VDD VREG CP0, CP0A ADC
+
SYSCLK -
CP1, CP1A +
-
GND
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
Modulator
Low Power Transceiver Control Interface
20 MHz Digital
Logic
Oscillator
UART
P0.2/XTAL1 External
Oscillator Timers 0, OSC XIN
P0.3/XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 22 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
Engine GND PGA
VDD VREG CP0, CP0A ADC
+
SYSCLK -
CP1, CP1A +
-
GND
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
Modulator
Low Power Transceiver Control Interface
20 MHz Digital
Logic
Oscillator
UART
P0.2/XTAL1 External
Oscillator Timers 0, OSC XIN
P0.3/XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 22 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
Rev. 0.2 17
Si1000/1/2/3/4/5
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
Engine GND PGA
VDD VREG CP0, CP0A ADC
+
SYSCLK -
CP1, CP1A +
-
GND
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
Modulator
Low Power Transceiver Control Interface
20 MHz Digital
Logic
Oscillator
UART
P0.2/XTAL1 External
Oscillator Timers 0, OSC XIN
P0.3/XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 22 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
Engine GND PGA
VDD VREG CP0, CP0A ADC
+
SYSCLK -
CP1, CP1A +
-
GND
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
Modulator
Low Power Transceiver Control Interface
20 MHz Digital
Logic
Oscillator
UART
P0.2/XTAL1 External
Oscillator Timers 0, OSC XIN
P0.3/XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 22 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
18 Rev. 0.2
Si1000/1/2/3/4/5
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
GND/DC-
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
VBAT DC/DC Modulator
Converter Low Power Transceiver Control Interface
20 MHz Digital
Logic
GND Oscillator
UART
XTAL1 External
Oscillator Timers 0, OSC XIN
XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 19 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
External
TX
256 Byte SRAM Internal
C2CK/RST Debug /
VREF VREF VDD AGC
Programming RXp
4096 Byte XRAM VREF
Hardware A
10-bit Temp LNA RXn
M
300ksps Sensor
C2D U
ADC
CRC X Mixer
GND/DC-
Precision
SFR Comparators Digital
Modem
24.5 MHz Bus
Oscillator
Digital Peripherals Delta
Sigma
VBAT DC/DC Modulator
Converter Low Power Transceiver Control Interface
20 MHz Digital
Logic
GND Oscillator
UART
XTAL1 External
Oscillator Timers 0, OSC XIN
XTAL2 Circuit 1, 2, 3 XOUT
Priority
XTAL3 PCA/ Crossbar
SmaRTClock Decoder
Oscillator WDT
XTAL4
SMBus
System Clock 19 ANALOG &
Port I/O
SPI 0 Config DIGITAL I/O
Configuration
Rev. 0.2 19
Si1000/1/2/3/4/5
supply voltage
C6 C7 C8 X1
30MHz
100p 100n 1u
XOUT
nIRQ
SDN
XIN
L1
VDD_RF VDD_MCU
L2 TX VDD_DIG
L4 L3 C1 Px.x
RFp
Si100x
C3 C2 RXn
C4
0.1 uF 0.1 uF
GPIO0
GPIO1
GPIO2
VR_DIG
ANT1
L6 L5
C9
C5 1u
Supply Voltage
C6 C7 C8 X1
30MHz
100 p 100 n 1u
XOUT
nIRQ
SDN
XIN
L1
VDD_RF VDD_MCU
TR & ANT-DIV L3 L2 TX VDD_DIG
Switch
C3 C2 C1 Px.x
RXp
1 6 Si100x
RXn
2 5
3 4 C4
0.1 uF 0.1 uF
GPIO0
GPIO1
GPIO2
VR_DIG
L4
C9
C5 1u
20 Rev. 0.2
Si1000/1/2/3/4/5
Number of Instructions 26 50 5 14 7 3 1 2 1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS.
1.2.3. Additional Features
The Si1000/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides multiple interrupt sources into the CIP-51, allowing numerous
analog and digital peripherals to interrupt the controller. An interrupt driven system requires less interven-
tion by the MCU, giving it more effective throughput. The extra interrupt sources are very useful when
building multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip VDD monitor (forces reset
when power supply voltage drops below safe levels), a watchdog timer, a Missing Clock Detector, SmaRT-
Clock oscillator fail or alarm, a voltage level detection from Comparator0, a forced software reset, an exter-
nal reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset
Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently disabled
in software after a power-on reset during MCU initialization.
The internal oscillator factory is calibrated to 24.5 MHz and is accurate to ±2% over the full temperature
and supply range. The internal oscillator period can also be adjusted by user firmware. An additional
20 MHz low power oscillator is also available which facilitates low-power operation. An external oscillator
drive circuit is included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock
source to generate the system clock. If desired, the system clock source may be switched between both
internal and external oscillator circuits. An external oscillator can also be extremely useful in low power
applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to
the fast (up to 25 MHz) internal oscillator as needed.
Rev. 0.2 21
Si1000/1/2/3/4/5
External Interrupts
Priority EX0 and EX1
Decoder
PnMDOUT,
2 PnMDIN Registers
Highest UART
Priority
SPI0 4
SPI1
P0.0
(Internal Digital Signals)
2
SMBus Digital P0
Crossbar I/O
8 Cells
CP0 4
CP1 P0.7
Outputs
SYSCLK P1.5
8
P1
7 I/O P1.6
PCA
Cells
P1.7
Lowest 2
T0, T1
Priority
8 P2.0
8
P0 (P0.0-P0.7) P2
I/O P2.6
(Port Latches)
8 Cell
P2.7
P1 (P1.0-P1.7)
To Analog Peripherals
8 (ADC0, CP0, and CP1 inputs, No analog functionality
VREF, IREF0, AGND) available on P2.7
P2 (P2.0-P2.7)
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the
EZRadioPRO peripheral. P1.3 is not internally or externally connected.
P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3
22 Rev. 0.2
Si1000/1/2/3/4/5
SYSCLK /12
SYSCLK /4
Timer 0 Overflow PCA
16 -Bit Counter/Timer
CLOCK
ECI MUX
SYSCLK
External Clock /8
Capture/ Compare Capture/ Compare Capture/ Compare Capture/ Compare Capture/ Compare Capture/ Compare
Module 0 Module 1 Module 2 Module 3 Module 4 Module5 / WDT
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
Crossbar
Port I/O
Rev. 0.2 23
Si1000/1/2/3/4/5
1.6. 10-bit SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous
Low Power Burst Mode
Si1000/1/2/3/4/5 devices have a 300 ksps, 10-bit successive-approximation-register (SAR) ADC with inte-
grated track-and-hold and programmable window detector. ADC0 also has an autonomous low power
Burst Mode which can automatically enable ADC0, capture and accumulate samples, then place ADC0 in
a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that can automati-
cally average the ADC results, providing an effective 11, 12, or 13-bit ADC result without any additional
CPU intervention.
The ADC can sample the voltage at any of the GPIO pins (with the exception of P2.7) and has an on-chip
attenuator that allows it to measure voltages up to twice the voltage reference. Additional ADC inputs
include an on-chip temperature sensor, the VDD_MCU supply voltage, the VBAT supply voltage, and the
internal digital supply voltage.
ADC0CN
BURSTEN
AD0BUSY
AD0WINT
AD0CM2
AD0CM1
AD0CM0
AD0INT
AD0EN
10-bit
ADC0L
From
AMUX0
AIN+ SAR
ADC 16-Bit Accumulator
ADC0H
SYSCLK
REF
AD0WINT
Window
Compare
AMP0GN
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
32
AD08BE
Logic
AD0TM
ADC0LTH ADC0LTL
24 Rev. 0.2
Si1000/1/2/3/4/5
ADC0MX
AM0MX0
AD0MX4
AD0MX3
AD0MX2
AD0MX1
P0.0
Programmable
Attenuator
AIN+
P2.6* AMUX ADC0
Temp
Sensor
Gain = 0. 5 or 1
Digital Supply
VDD_MCU
The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches. See Application Note “AN338: Capacitive Touch Sense
Solution” for details on Capacitive Touch Switch sensing.
Rev. 0.2 25
Si1000/1/2/3/4/5
CP0EN
CP0OUT
CP0RIF VDD
CPT0CN
CP0FIF
CP0HYP1
CP0HYP0 CP0
Interrupt
CP0HYN1
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0MD0
CP0MD1
CP0RIE
CP0FIE
CP0 CP0
Px.x
Rising-edge Falling-edge
CP0 + Interrupt
Logic
Px.x
CP0
+
SET SET
D Q D Q
- CLR Q CLR Q
Px.x Crossbar
(SYNCHRONIZER)
CP0 - GND
(ASYNCHRONOUS)
CP0A
Reset
Px.x Decision
Tree
CP1EN
CP1OUT
CP1RIF VDD
CPT0CN
CP1FIF
CP1HYP1
CP1HYP0 CP1
Interrupt
CP1HYN1
CP1HYN0
CPT0MD
Analog Input Multiplexer
CP1MD0
CP1MD1
CP1RIE
CP1FIE
CP1 CP1
Px.x
Rising-edge Falling-edge
CP1 + Interrupt
Logic
Px.x
CP1
+
SET SET
D Q D Q
- CLR Q CLR Q
Px.x Crossbar
(SYNCHRONIZER)
CP1 - GND
(ASYNCHRONOUS)
CP1A
Reset
Px.x Decision
Tree
26 Rev. 0.2
Si1000/1/2/3/4/5
2. Ordering Information
Table 2.1. Product Selection Guide
Temperature Sensor
10-bit 300ksps ADC
Flash Memory (kB)
Timers (16-bit)
RAM (bytes)
MIPS (Peak)
SMBus/I2C
Package
UART
Rev. 0.2 27
Si1000/1/2/3/4/5
28 Rev. 0.2
Si1000/1/2/3/4/5
XTAL2 A Out External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
D In External Clock Input. This pin is the external clock input in
external CMOS clock mode.
A In External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See Oscillator section for complete details.
Rev. 0.2 29
Si1000/1/2/3/4/5
CNVSTR D In External Convert Start Input for ADC0. See ADC0 section
for a complete description.
P0.7 29 29 D I/O or Port 0.7. See Port I/O section for a complete description.
A In
IREF0 A Out IREF0 Output. See IREF section for complete description.
P1.5 10 10 D I/O or Port 1.5. See Port I/O section for a complete description.
A In
P1.6 9 9 D I/O or Port 1.6. See Port I/O section for a complete description.
A In
P1.7 8 8 D I/O or Port 1.7. See Port I/O section for a complete description.
A In
P2.0 7 7 D I/O or Port 2.0. See Port I/O section for a complete description.
A In
P2.1 6 6 D I/O or Port 2.1. See Port I/O section for a complete description.
A In
P2.2 5 5 D I/O or Port 2.2. See Port I/O section for a complete description.
A In
P2.3 4 4 D I/O or Port 2.3. See Port I/O section for a complete description.
A In
P2.4 3 — D I/O or Port 2.4. See Port I/O section for a complete description.
A In
P2.5 2 — D I/O or Port 2.5. See Port I/O section for a complete description.
A In
P2.6 41 — D I/O or Port 2.6. See Port I/O section for a complete description.
A In
30 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 31
Si1000/1/2/3/4/5
GND_MCU
P0.0/VREF
RST/C2CK
VDD_MCU
P2.7/C2D
XTAL4
P2.6
42
41
40
39
38
37
36
XTAL3 1 35 P0.1/AGND
P2.5 2 34 P0.2/XTAL1
P2.4 3 33 P0.3/XTAL2
P2.3 4 32 P0.4/TX
P2.2 5 31 P0.5/RX
P2.0 7 29 P0.7/IREF0
Si1000/1/2/3
P1.7 8 Top View 28 VDD_DIG
P1.6 9 27 VR_DIG
P1.5 10 26 GPIO_2
nIRQ 11 25 GPIO_1
XOUT 12 24 GPIO_0
N.C. 14 22 N.C.
15
16
17
18
19
20
21
SDN
TX
RXp
RXn
N.C.
ANT_A
VDD_RF
32 Rev. 0.2
Si1000/1/2/3/4/5
VDD_MCU/DC+
GND_MCU/DC-
GND/VBAT-
P0.0/VREF
RST/C2CK
DCEN
VBAT
42
41
40
39
38
37
36
P2.7/C2D 1 35 P0.1/AGND
XTAL4 2 34 P0.2/XTAL1
XTAL3 3 33 P0.3/XTAL2
P2.3 4 32 P0.4/TX
P2.2 5 31 P0.5/RX
P2.0 7 29 P0.7/IREF0
Si1004/5
P1.7 8 Top View 28 VDD_DIG
P1.6 9 27 VR_DIG
P1.5 10 26 GPIO_2
nIRQ 11 25 GPIO_1
XOUT 12 24 GPIO_0
N.C. 14 22 N.C.
15
16
17
18
19
20
21
N.C.
TX
VDD_RF
ANT_A
SDN
RXp
RXn
Rev. 0.2 33
Si1000/1/2/3/4/5
34 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 35
Si1000/1/2/3/4/5
36 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 37
Si1000/1/2/3/4/5
4. Electrical Characteristics
In sections 4.1 and 4.2, , “VDD” refers to the VDD_MCU supply voltage on Si1000/1/2/3 devices and to the
VDD_MCU/DC+ supply voltage on Si1004/5 devices. The ADC, Comparator, and Port I/O specifications in
these two sections do not apply to the EZRadioPRO peripheral.
In sections 4.3 and 4.4, “VDD” refers to the VDD_RF and VDD_DIG Supply Voltage. All specifications in
these sections pertain to the EZRadioPRO peripheral.
4.1. Absolute Maximum Specifications
Table 4.1. Absolute Maximum Ratings
Voltage on any Px.x I/O Pin or VDD > 2.2 V –0.3 — 5.8 V
RST with Respect to GND VDD < 2.2 V –0.3 — VDD + 3.6
38 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 39
Si1000/1/2/3/4/5
40 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 41
Si1000/1/2/3/4/5
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
8. The EZRadioPRO peripheral is placed in Shutdown mode.
42 Rev. 0.2
Si1000/1/2/3/4/5
4200
4100 F < 10 MHz F > 10 MHz
4000 Oneshot Enabled Oneshot Bypassed
3900
3800
3700
3600
3500
3400 < 170 µA/MHz
3300
3200
3100
3000
2900 200 µA/MHz
2800
2700
2600 215 µA/MHz
2500
2400
Supply Current (uA)
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400 240 µA/MHz
1300
1200
1100
1000
900
800 250 µA/MHz
700
600
500
400
300 300 µA/MHz
200
100
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
Rev. 0.2 43
Si1000/1/2/3/4/5
4200
4100
4000
3900
3800
3700
3600
3500
3400
3300
3200
3100
3000
2900
2800
2700
2600
2500
2400
Supply Current (uA)
2300
2200
2100
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Frequency (MHz)
44 Rev. 0.2
Si1000/1/2/3/4/5
6:6(/ 6:6(/
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\FKRRVLQJDQ
LQGXFWRUZLWKDORZHU(65
Rev. 0.2 45
Si1000/1/2/3/4/5
6:6(/ 6:6(/
9%$7 9
9%$7 9
9%$7 9
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
9'''& 90LQLPXP3XOVH:LGWK QV
3XOVH6NLSSLQJ'LVDEOHG
1RWH(IILFLHQF\DWKLJKFXUUHQWVPD\EHLPSURYHGE\
FKRRVLQJDQLQGXFWRUZLWKDORZHU(65
46 Rev. 0.2
Si1000/1/2/3/4/5
9%$7 9
9%$7 9
9%$7 9
Efficiency (%)
9%$7 9
9%$7 9
9%$7 9
9%$7 9
X+,QGXFWRUSDFNDJH(65 2KPV
6:6(/ 9'''& 90LQLPXP3XOVH:LGWK QV
Load current (mA)
Rev. 0.2 47
Si1000/1/2/3/4/5
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
0LQ3XOVH:LGWKQV
9%$7&XUUHQWX$
9%$79
48 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 49
Si1000/1/2/3/4/5
3.6
VDD = 3.6V
3.3
3 VDD = 3.0V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0 5 10 15 20 25 30 35 40 45 50
Load Current (mA)
3.6
3 VDD = 3.0V
2.4
VDD = 1.8V
2.1
1.8
1.5
1.2
0.9
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Load Current (mA)
50 Rev. 0.2
Si1000/1/2/3/4/5
1.8
1.7 VDD = 1.8V
1.6
VDD = 1.5V
1.5
1.4
VDD = 1.2V
1.3
Voltage
1.8
1.7 VDD = 1.8V
1.6
1.5 VDD = 1.5V
1.4
VDD = 1.2V
1.3
Voltage
Rev. 0.2 51
Si1000/1/2/3/4/5
1.8
VDD = 3.6V
1.5
VDD = 3.0V
1.2
VDD = 2.4V
Voltage
0.6
0.3
0
-80 -70 -60 -50 -40 -30 -20 -10 0
Load Current (mA)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
1.2
VDD = 2.4V
Voltage
0.6
0.3
0
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Load Current (mA)
52 Rev. 0.2
Si1000/1/2/3/4/5
1.8
VDD = 3.6V
1.5
VDD = 3.0V
1.2
VDD = 2.4V
Voltage
0.6
0.3
0
-80 -70 -60 -50 -40 -30 -20 -10 0
Load Current (mA)
1.8
VDD = 3.6V
1.5
VDD = 3.0V
1.2
VDD = 2.4V
Voltage
0.6
0.3
0
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Load Current (mA)
Rev. 0.2 53
Si1000/1/2/3/4/5
0.5
VDD = 1.8V
0.4
VDD = 1.5V
VDD = 1.2V
0.3
Voltage
VDD = 0.9V
0.2
0.1
0
-5 -4 -3 -2 -1 0
Load Current (mA)
0.5
0.4
0.3
Voltage
VDD = 1.8V
0.2
VDD = 1.5V
VDD = 1.2V
0.1
VDD = 0.9V
0
-3 -2 -1 0
Load Current (mA)
54 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 55
Si1000/1/2/3/4/5
56 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 57
Si1000/1/2/3/4/5
58 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 59
Si1000/1/2/3/4/5
60 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 61
Si1000/1/2/3/4/5
62 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 63
Si1000/1/2/3/4/5
64 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 65
Si1000/1/2/3/4/5
66 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 67
Si1000/1/2/3/4/5
68 Rev. 0.2
Si1000/1/2/3/4/5
Rev. 0.2 69
Si1000/1/2/3/4/5
70 Rev. 0.2
Si1000/1/2/3/4/5
TA = +25 °C
VDD = +3.3 VDC
Sensitivity measured at 919 MHz
TX output power measured at 915 MHz
External reference signal (XOUT) = 1.0 VPP at 30 MHz, centered around 0.8 VDC
Production test schematic (unless noted otherwise)
All RF input and output levels referred to the pins of the Si100x (not the RF module)
TA = –40 to +85 °C
VDD = +1.8 to +3.6 VDC
Using 4432, 4431, or 4430 DKDB1 reference design or production test schematic
All RF input and output levels referred to the pins of the Si100x (not the RF module)
Rev. 0.2 71
Si1000/1/2/3/4/5
ADC0CN
BURSTEN
AD0BUSY
AD0WINT
AD0CM2
AD0CM1
AD0CM0
AD0INT
AD0EN
10-bit
ADC0L
From
AMUX0
AIN+ SAR
ADC 16-Bit Accumulator
ADC0H
REF
SYSCLK
AD0WINT
W indow
Compare
AMP0GN
AD0SC4
AD0SC3
AD0SC2
AD0SC1
AD0SC0
AD08BE
32 Logic
AD0TM
ADC0LTH ADC0LTL
72 Rev. 0.2
Si1000/1/2/3/4/5
When the repeat count is greater than 1, the output conversion code represents the accumulated result of
the conversions performed and is updated after the last conversion in the series is finished. Sets of 4, 8,
16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0AC register. When a repeat count higher
than 1, the ADC output must be right-justified (AD0SJST = 0xx); unused bits in the ADC0H and ADC0L
registers are set to 0. The example below shows the right-justified result for various input voltages and
repeat counts. Notice that accumulating 2n samples is equivalent to left-shifting by n bit positions when all
samples returned from the ADC have the same value.
The AD0SJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Rev. 0.2 73
Si1000/1/2/3/4/5
74 Rev. 0.2
Si1000/1/2/3/4/5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SAR
Clocks
Track or
AD0TM=0 Convert Track
Convert
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0)
Rev. 0.2 75
Si1000/1/2/3/4/5
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or
64 using an internal Burst Mode clock (approximately 25 MHz), then re-enters a low power state. Since the
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or
suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e., the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an exam-
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 77 for more
details.
Notes:
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
S yste m C lo ck
C o n ve rt S ta rt
AD0PW R AD0TK
T = T ra ckin g se t b y A D 0 T K
T 3 = T ra ckin g se t b y A D 0 T M (3 S A R clo cks)
C = C o n ve rtin g
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
76 Rev. 0.2
Si1000/1/2/3/4/5
n
t = ln ------- R TOTAL C SAMPLE
2
SA
MUX Select
P0.x
R MUX
C SAMPLE
Note: The value of CSAMPLE depends on the PGA Gain. See Table 4.9 for details.
Rev. 0.2 77
Si1000/1/2/3/4/5
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2.
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF volt-
age, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are con-
trolled by the AMP0GN bit in register ADC0CF.
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
78 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Rev. 0.2 79
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 0 0 0
FCLK
AD0SC = -------------------- – 1 *
CLK SAR
*Round the result up.
or
FCLK
CLK SAR = ----------------------------
AD0SC + 1
80 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Rev. 0.2 81
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Type R R R R R/W
Reset 0 0 0 0 1 1 1 1
The ADC0 Burst Mode Power-Up time is programmed according to the follow-
ing equation:
Tstartup
AD0PWR = ---------------------- – 1
400ns
or
82 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name AD0TK[5:0]
Type R R R/W
Reset 0 0 0 1 0 1 1 0
The ADC0 Burst Mode Track time is programmed according to the following equa-
tion:
Notes:
1. If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
2. The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
Rev. 0.2 83
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name ADC0[15:8]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name ADC0[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
84 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name AD0GT[15:8]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name AD0GT[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Rev. 0.2 85
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name AD0LT[15:8]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name AD0LT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
86 Rev. 0.2
Si1000/1/2/3/4/5
ADC0H:ADC0L ADC0H:ADC0L
Input Voltage Input Voltage
(Px.x - GND) (Px.x - GND)
AD0WINT
AD0WINT=1
not affected
0x0081 0x0081
VREF x (128/1024) 0x0080 ADC0LTH:ADC0LTL VREF x (128/1024) 0x0080 ADC0GTH:ADC0GTL
0x007F 0x007F
AD0WINT
AD0WINT=1
not affected
0x0041 0x0041
VREF x (64/1024) 0x0040 ADC0GTH:ADC0GTL VREF x (64/1024) 0x0040 ADC0LTH:ADC0LTL
0x003F 0x003F
AD0WINT AD0WINT=1
not affected
0 0x0000 0 0x0000
ADC0H:ADC0L ADC0H:ADC0L
Input Voltage Input Voltage
(Px.x - GND) (Px.x - GND)
AD0WINT
AD0WINT=1
not affected
0x2040 0x2040
VREF x (128/1024) 0x2000 ADC0LTH:ADC0LTL VREF x (128/1024) 0x2000 ADC0GTH:ADC0GTL
0x1FC0 0x1FC0
AD0WINT
AD0WINT=1
not affected
0x1040 0x1040
VREF x (64/1024) 0x1000 ADC0GTH:ADC0GTL VREF x (64/1024) 0x1000 ADC0LTH:ADC0LTL
0x0FC0 0x0FC0
AD0WINT AD0WINT=1
not affected
0 0x0000 0 0x0000
Rev. 0.2 87
Si1000/1/2/3/4/5
ADC0MX
AM0MX0
AD0MX4
AD0MX3
AD0MX2
AD0MX1
P0.0
Programmable
Attenuator
AIN+
P2.6* AMUX ADC0
Temp
Sensor
Gain = 0. 5 or 1
Digital Supply
VDD_MCU
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT = 0 and
Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register PnSKIP.
See Section “21. Port Input/Output” on page 204 for more Port I/O configuration details.
88 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name AD0MX
Reset 0 0 0 1 1 1 1 1
Rev. 0.2 89
Si1000/1/2/3/4/5
Slope ( V / deg C)
Voltage
Offset ( V at 25 Celsius)
Temperature
Figure 5.8. Temperature Sensor Transfer Function
5.6.1. Calibration
The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea-
surements (see Table 4.10 for linearity specifications). For absolute temperature measurements, offset
and/or gain calibration is recommended. Typically a 1-point (offset) calibration includes the following steps:
90 Rev. 0.2
Si1000/1/2/3/4/5
Figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Parame-
ters that affect ADC measurement, in particular the voltage reference value, will also affect temper-
ature measurement.
A single-point offset measurement of the temperature sensor is performed on each device during produc-
tion test. The measurement is performed at 25 °C ±5 °C, using the ADC with the internal high speed refer-
ence buffer selected as the Voltage Reference. The direct ADC result of the measurement is stored in the
SFR registers TOFFH and TOFFL, shown in SFR Definition 5.13 and SFR Definition 5.14.
5.00 5.00
4.00 4.00
3.00 3.00
2.00 2.00
Error (degrees C)
1.00 1.00
0.00 0.00
-40.00 -20.00 0.00 40.00 60.00 80.00
20.00
-1.00 -1.00
-2.00 -2.00
-3.00 -3.00
-4.00 -4.00
-5.00 -5.00
Temperature (degrees C)
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V)
Rev. 0.2 91
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Name TOFF[9:2]
Type R R R R R R R R
Bit 7 6 5 4 3 2 1 0
Name TOFF[1:0]
Type R R
92 Rev. 0.2
Si1000/1/2/3/4/5
R E F 0C N
REFGND
REFSL1
REFSL0
TEMPE
REFOE
ADC
T em p S ensor Input
EN M ux
REFOE
EN
REFGND
Rev. 0.2 93
Si1000/1/2/3/4/5
94 Rev. 0.2
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 1 1 0 0 0
Rev. 0.2 95
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
96 Rev. 0.2
Si1000/1/2/3/4/5
7. Comparators
Si1000/1/2/3/4/5 devices include two on-chip programmable voltage comparators: Comparator 0 (CPT0) is
shown in Figure 7.1; Comparator 1 (CPT1) is shown in Figure 7.2. The two comparators operate identi-
cally, but may differ in their ability to be used as reset or wake-up sources. See the Reset Sources chapter
and the Power Management chapter for details on reset sources and low power mode wake-up sources,
respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
7.1. Comparator Inputs
Each Comparator performs an analog comparison of the voltage levels at its positive (CP0+ or CP1+) and
negative (CP0- or CP1-) input. Both comparators support multiple port pin inputs multiplexed to their posi-
tive and negative comparator inputs using analog input multiplexers. The analog input multiplexers are
completely under software control and configured using SFR registers. See Section “7.6. Comparator0 and
Comparator1 Analog Multiplexers” on page 104 for details on how to select and configure Comparator
inputs.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs and skipped by the Crossbar. See the Port I/O chapter for more details on how to
configure Port I/O pins as Analog Inputs. The Comparator may also be used to compare the logic level of
digital signals, however, Port I/O pins configured as digital inputs must be driven to a valid logic state
(HIGH or LOW) to avoid increased power consumption.
CP0EN
CP0OUT
CP0RIF VDD
CPT0CN
CP0FIF
CP0HYP1
CP0HYP0 CP0
Interrupt
CP0HYN1
CP0HYN0
CPT0MD
Analog Input Multiplexer
CP0MD0
CP0MD1
CP0RIE
CP0FIE
CP0 CP0
Px.x
Rising-edge Falling-edge
CP0 + Interrupt
Logic
Px.x
CP0
+
SET SET
D Q D Q
- CLR Q CLR Q
Px.x Crossbar
(SYNCHRONIZER)
CP0 - GND
(ASYNCHRONOUS)
CP0A
Reset
Px.x Decision
Tree
Rev. 0.2 97
Si1000/1/2/3/4/5
CP1EN
CP1OUT
CP1RIF VDD
CPT0CN
CP1FIF
CP1HYP1
CP1HYP0 CP1
Interrupt
CP1HYN1
CP1HYN0
CPT0MD
Analog Input Multiplexer
CP1MD0
CP1MD1
CP1RIE
CP1FIE
CP1 CP1
Px.x
Rising-edge Falling-edge
CP1 + Interrupt
Logic
Px.x
CP1
+
SET SET
D Q D Q
- CLR Q CLR Q
Px.x Crossbar
(SYNCHRONIZER)
CP1 - GND
(ASYNCHRONOUS)
CP1A
Reset
Px.x Decision
Tree
98 Rev. 0.2
Si1000/1/2/3/4/5
CPn+
VIN+ +
CPn OUT
CPn- _
VIN-
CIRCUIT CONFIGURATION
V OH
OUTPUT
V OL
Negative Hysteresis Maximum
Disabled Negative Hysteresis
Rev. 0.2 99
Si1000/1/2/3/4/5
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 1 0 0 0 0 0 1 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 1 0 0 0 0 0 1 0
CPTnMX
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
P0.1 P0.0
P0.3 P0.2
P0.5 P0.4
P0.7 P0.6
CPnOUT CPnOUT
VDD_MCU VDD_MCU
GND
R R
½ x VDD_MCU ½ x VDD_MCU
GND
Important Note About Comparator Input Configuration: Port pins selected as comparator inputs should
be configured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for
analog input, set to 0 the corresponding bit in register PnMDIN and disable the digital driver (PnMDOUT =
0 and Port Latch = 1). To force the Crossbar to skip a Port pin, set to 1 the corresponding bit in register
PnSKIP. See Section “21. Port Input/Output” on page 204 for more Port I/O configuration details.
Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 1
8. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 28), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set Reset Input
25 MIPS Peak Throughput with 25 MHz Clock Power Management Modes
0 to 25 MHz Clock Frequency On-chip Debug Logic
Extended Interrupt Handler Program and Data Memory Security
8.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
DATA BUS
D8
D8
D8
D8
D8
TMP1 TMP2
SRAM
PSW ADDRESS SRAM
ALU REGISTER
D8
D8
D8
D8
DATA BUS
SFR_ADDRESS
BUFFER D8
SFR_CONTROL
SFR
D8 BUS SFR_WRITE_DATA
DATA POINTER D8
INTERFACE
SFR_READ_DATA
PC INCREMENTER
DATA BUS
D8 MEM_ADDRESS
PROGRAM COUNTER (PC)
MEM_CONTROL
MEMORY
PRGM. ADDRESS REG. A16 INTERFACE MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE D8
RESET CONTROL
LOGIC
SYSTEM_IRQs
CLOCK
INTERRUPT
D8
INTERFACE EMULATION_IRQ
STOP
POWER CONTROL
D8
IDLE REGISTER
Number of Instructions 26 50 5 14 7 3 1 2 1
rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same
2 kB page of program memory as the first byte of the following instruction.
addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 8 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
Bit 7 6 5 4 3 2 1 0
Name DPL[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name DPH[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name SP[7:0]
Type R/W
Reset 0 0 0 0 0 1 1 1
Bit 7 6 5 4 3 2 1 0
Name ACC[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name B[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
Si1000/1/2/3/4/5 device family is shown in Figure 9.1
0x0000
EXTERNAL DATA ADDR ESS SPACE
Si1001/3
0x03FF 0xFFFF
Scrachpad M em ory
0x0000 (D ATA only)
Reserved
0x7FFF
0x1000
32KB FLASH 0x0FFF
0x0000 0x0000
Si1000/2 Si1001/3
(SFLE=0) (SFLE=0)
0xFFFF 0xFFFF
Reserved Area
0xFC00
Lock Byte 0xFBFF Unpopulated
1024-byte pages
0xF800
0xF7FF
0x8000
Lock Byte 0x7FFF
Si1000/2 0x7FFE
Si1001/3 Flash Memory Space Lock Byte Page
0x7C00
(SFLE=1) 0x7BFF
0x03FF
Flash Memory Space
Scratchpad
(Data Only)
0x0000 0x0000 0x0000
Bit 7 6 5 4 3 2 1 0
Name PGSEL[3:0]
Type R R R R R/W
Reset 0 0 0 0 0 0 0 0
For Example:
If EMI0CN = 0x01, addresses 0x0100 through 0x01FF will be accessed.
If EMI0CN = 0x0F, addresses 0x0F00 through 0x0FFF will be accessed.
Table 11.1. Special Function Register (SFR) Memory Map (Page 0x0)
F8 SPI0CN PCA0L PCA0H PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
F0 B P0MDIN P1MDIN P2MDIN SMB0ADR SMB0ADM EIP1 EIP2
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 RSTSRC
E0 ACC XBR0 XBR1 XBR2 IT01CF EIE1 EIE2
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0PWM
D0 PSW REF0CN PCA0CPL5 PCA0CPH5 P0SKIP P1SKIP P2SKIP P0MAT
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPM5 P1MAT
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
B8 IP IREF0CN ADC0AC ADC0MX ADC0CF ADC0L ADC0H P1MASK
B0 SPI1CN OSCXCN OSCICN OSCICL PMU0CF FLSCL FLKEY
A8 IE CLKSEL EMI0CN Reserved RTC0ADR RTC0DAT RTC0KEY Reserved
A0 P2 SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
98 SCON0 SBUF0 CPT1CN CPT0CN CPT1MD CPT0MD CPT1MX CPT0MX
90 P1 TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H DC0CF DC0CN
88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PSCTL
80 P0 SP DPL DPH SPI1CFG SPI1CKR SPI1DAT PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0 B EIP1 EIP2
E8
E0 ACC EIE1 EIE2
D8
D0 PSW
C8
C0
B8 ADC0PWR ADC0TK
B0
A8 IE CLKSEL
A0 P2 P0DRV P1DRV P2DRV SFRPAGE
98
90 P1 CRC0DAT CRC0CN CRC0IN CRC0FLIP CRC0AUTO CRC0CNT
88
80 P0 SP DPL DPH TOFFL TOFFH PCON
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
Bit 7 6 5 4 3 2 1 0
Name SFRPAGE[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit addressable?
Interrupt Source Pending Flag Enable Priority
Cleared by HW?
Interrupt Vector
Flag Control
Priority Order
Reset 0x0000 Top None N/A N/A Always Always
Enabled Highest
External Interrupt 0 (INT0) 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)
Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)
External Interrupt 1 (INT1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)
Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)
UART0 0x0023 4 RI0 (SCON0.0) Y N ES0 (IE.4) PS0 (IP.4)
TI0 (SCON0.1)
Timer 2 Overflow 0x002B 5 TF2H (TMR2CN.7) Y N ET2 (IE.5) PT2 (IP.5)
TF2L (TMR2CN.6)
SPI0 0x0033 6 SPIF (SPI0CN.7) Y N ESPI0 PSPI0
WCOL (SPI0CN.6) (IE.6) (IP.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
SMB0 0x003B 7 SI (SMB0CN.0) Y N ESMB0 PSMB0
(EIE1.0) (EIP1.0)
SmaRTClock Alarm 0x0043 8 ALRM (RTC0CN.2)* N N EARTC0 PARTC0
(EIE1.1) (EIP1.1)
ADC0 Window 0x004B 9 AD0WINT Y N EWADC0 PWADC0
Comparator (ADC0CN.3) (EIE1.2) (EIP1.2)
ADC0 End of Conversion 0x0053 10 AD0INT (ADC0STA.5) Y N EADC0 PADC0
(EIE1.3) (EIP1.3)
Programmable Counter 0x005B 11 CF (PCA0CN.7) Y N EPCA0 PPCA0
Array CCFn (PCA0CN.n) (EIE1.4) (EIP1.4)
Comparator0 0x0063 12 CP0FIF (CPT0CN.4) N N ECP0 PCP0
CP0RIF (CPT0CN.5) (EIE1.5) (EIP1.5)
Comparator1 0x006B 13 CP1FIF (CPT1CN.4) N N ECP1 PCP1
CP1RIF (CPT1CN.5) (EIE1.6) (EIP1.6)
Timer 3 Overflow 0x0073 14 TF3H (TMR3CN.7) N N ET3 PT3
TF3L (TMR3CN.6) (EIE1.7) (EIP1.7)
VDD_MCU Supply 0x007B 15 VDDOK EWARN PWARN
Monitor Early Warning (VDM0CN.5)1 (EIE2.0) (EIP2.0)
Port Match 0x0083 16 None EMAT PMAT
(EIE2.1) (EIP2.1)
Bit addressable?
Interrupt Source Pending Flag Enable Priority
Cleared by HW?
Interrupt Vector
Flag Control
Priority Order
SmaRTClock Oscillator 0x008B 17 OSCFAIL N N ERTC0F PFRTC0F
Fail (RTC0CN.5)2 (EIE2.2) (EIP2.2)
EZRadioPRO Serial 0x0093 18 SPIF (SPI1CN.7) N N ESPI1 PSPI1
Interface (SPI1) WCOL (SPI1CN.6) (EIE2.3) (EIP2.3)
MODF (SPI1CN.5)
RXOVRN (SPI1CN.4)
Notes:
1. Indicates a read-only interrupt pending flag. The interrupt enable may be used to prevent software from
vectoring to the associated interrupt service routine.
2. Indicates a register located in an indirect memory space.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 1 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 12.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 207 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 1
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 1024-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x03FF), where n is the 1s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is unlocked when no other Flash pages are locked
(all bits of the Lock Byte are 1) and locked when any other Flash pages are locked (any bit of the
Lock Byte is 0). See the Si1000 example below.
The level of Flash security depends on the Flash access method. The three Flash access methods that
can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on
unlocked pages, and user firmware executing on locked pages. Table 13.1 summarizes the Flash security
features of the Si1000/1/2/3/4/5 devices.
- All prohibited operations that are performed via the C2 interface are ignored (do not cause device reset).
- Locking any Flash page also locks the page containing the Lock Byte.
- Once written to, the Lock Byte cannot be modified except by performing a C2 Device Erase.
- If user code writes to the Lock Byte, the Lock does not take effect until the next device reset.
- The scratchpad is locked when all other Flash pages are locked.
- The scratchpad is erased when a Flash Device Erase command is performed.
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
2. Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot meet
this rise time specification, then add an external VDD brownout circuit to the RST pin of the device that
holds the device in reset until VDD reaches the minimum device operating voltage and re-asserts RST if
VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For C-based
systems, this will involve modifying the startup code added by the C compiler. See your compiler
documentation for more details. Make certain that there are no delays in software between enabling the
VDD Monitor and enabling the VDD Monitor as a reset source. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
Notes: On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source must be enabled to write
or erase Flash without generating a Flash Error Device Reset.
On Si1000/1/2/3/4/5 devices, both the VDD Monitor and the VDD Monitor reset source are enabled by hardware
after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a reset
source inside the functions that write and erase Flash memory. The VDD Monitor enable instructions
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
13.5.2. PSWE Maintenance
7. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
both PSWE and PSEE both to a 1 to erase Flash pages.
8. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
and loop maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing this can be
found in “AN201: Writing to Flash from Firmware," available from the Silicon Laboratories website.
9. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
reset to 0. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
10.Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
11. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
Additional Flash recommendations and example code can be found in “AN201: Writing to Flash from Firm-
ware," available from the Silicon Laboratories website.
13.6. Minimizing Flash Read Current
The Flash memory in the Si1000/1/2/3/4/5 devices is responsible for a substantial portion of the total digital
supply current when the device is executing code. Below are suggestions to minimize Flash read current.
1. Use Idle, Suspend, or Sleep Modes while waiting for an interrupt, rather than polling the interrupt flag.
Idle Mode is particularly well-suited for use in implementing short pauses, since the wake-up time is no
more than three system clock cycles. See the Power Management chapter for details on the various
low-power operating modes.
2. Si1000/1/2/3/4/5 devices have a one-shot timer that saves power when operating at system clock
frequencies of 10 MHz or less. The one-shot timer generates a minimum-duration enable signal for the
Flash sense amps on each clock cycle in which the Flash memory is accessed. This allows the Flash to
remain in a low power state for the remainder of the long clock cycle.
At clock frequencies above 10 MHz, the system clock cycle becomes short enough that the one-shot
timer no longer provides a power benefit. Disabling the one-shot timer at higher frequencies reduces
power consumption. The one-shot is enabled by default, and it can be disabled (bypassed) by setting
the BYPASS bit (FLSCL.6) to logic 1. To re-enable the one-shot, clear the BYPASS bit to logic 0. See
the note in SFR Definition 13.3. FLSCL: Flash Scale for more information on how to properly clear the
BYPASS bit.
3. Flash read current depends on the number of address lines that toggle between sequential Flash read
operations. In most cases, the difference in power is relatively small (on the order of 5%).
4. The Flash memory is organized in rows. Each row in the Si1000/1/2/3/4/5 Flash contains 128 bytes. A
substantial current increase can be detected when the read address jumps from one row in the Flash
memory to another. Consider a 3-cycle loop (e.g., SJMP $, or while(1);) which straddles a 128-byte
Flash row boundary. The Flash address jumps from one row to another on two of every three clock
cycles. This can result in a current increase of up 30% when compared to the same 3-cycle loop
contained entirely within a single row.
5. To minimize the power consumption of small loops, it is best to locate them within a single row, if
possible. To check if a loop is contained within a Flash row, divide the starting address of the first
instruction in the loop by 128. If the remainder (result of modulo operation) plus the length of the loop is
less than 127, then the loop fits inside a single Flash row. Otherwise, the loop will be straddling two
adjacent Flash rows. If a loop executes in 20 or more clock cycles, then the transitions from one row to
another will occur on relatively few clock cycles, and any resulting increase in operating current will be
negligible.
Note: Future 16 and 8 kB derivatives in this product family will use a Flash memory that is organized in rows of 64
bytes each. To maintain code compatibility across the entire family, it is best to locate small loops within a single
64-byte segment.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name FLKEY[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name BYPASS
Type R R/W R R R R R R
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name Function
7 Reserved Always Write to 0.
6 BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the Flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0 Reserved Always Write to 000000.
Note: When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the FLWR register. When programming in C, the dummy value written to FLWR should be a non-
zero value to prevent the compiler from generating a 2-byte MOV instruction.
Bit 7 6 5 4 3 2 1 0
Name FLWR[7:0]
Type W
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
In battery powered systems, the system should spend as much time as possible in Sleep mode in order to
preserve battery life. When a task with a fixed number of clock cycles needs to be performed, the device
should switch to Normal mode, finish the task as quickly as possible, and return to Sleep mode. Idle Mode
and Suspend modes provide a very fast wake-up time; however, the power savings in these modes will not
be as much as in Sleep Mode. Stop Mode is included for legacy reasons; the system will be more power
efficient and easier to wake up when Idle, Suspend, or Sleep Mode are used.
Although switching power modes is an integral part of power management, enabling/disabling individual
peripherals as needed will help lower power consumption in all power modes. Each analog peripheral can
be disabled when not in use or placed in a low power mode. Digital peripherals such as timers or serial
busses draw little power whenever they are not in use. Digital peripherals draw no power in Sleep Mode.
Active/Idle/
Sleep
Stop/Suspend 1.8 V Digital Peripherals
UART
PMU0 CIP-51
Flash
SPI
Core
The Comparator0 Rising Edge wakeup is only valid in two-cell mode. The comparator requires a supply
voltage of at least 1.8 V to operate properly.
In addition, any falling edge on RST (due to a pin reset or a noise glitch) will cause the device to exit sleep
mode. In order for the MCU to respond to the pin reset event, software must not place the device back into
sleep mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-up was
due to a falling edge on the RST pin. If the wake-up source is not due to a falling edge on RST, there is no
time restriction on how soon software may place the device back into sleep mode. A 4.7 k pullup resistor
to VDD_MCU/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.6. Configuring Wakeup Sources
Before placing the device in a low power mode, one or more wakeup sources should be enabled so that
the device does not remain in the low power mode indefinitely. For Idle Mode, this includes enabling any
interrupt. For Stop Mode, this includes enabling any reset source or relying on the RST pin to reset the
device.
Wake-up sources for Suspend and Sleep Modes are configured through the PMU0CF register. Wake-up
sources are enabled by writing 1 to the corresponding wake-up source enable bit. Wake-up sources must
be re-enabled each time the device is placed in Suspend or Sleep mode, in the same write that places the
device in the low power mode.
The reset pin is always enabled as a wake-up source. On the falling edge of RST, the device will be
awaken from Sleep Mode. The device must remain awake for more than 15 µs in order for the reset to take
place.
14.7. Determining the Event that Caused the Last Wakeup
When waking from Idle Mode, the CPU will vector to the interrupt which caused it to wake up. When wak-
ing from Stop mode, the RSTSRC register may be read to determine the cause of the last reset.
Upon exit from Suspend or Sleep mode, the wake-up flags in the PMU0CF register can be read to deter-
mine the event which caused the device to wake up. After waking up, the wake-up flags will continue to be
updated if any of the wake-up events occur. Wake-up flags are always updated, even if they are not
enabled as wake-up sources.
All wake-up flags enabled as wake-up sources in PMU0CF must be cleared before the device can enter
Suspend or Sleep mode. After clearing the wake-up flags, each of the enabled wake-up events should be
checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags
were being cleared.
Bit 7 6 5 4 3 2 1 0
Bit 7 6 5 4 3 2 1 0
Type R/W W W
Reset 0 0 0 0 0 0 0 0
CRC0SEL CRC0AUTO
CRC0INIT CRC Engine
CRC0VAL
CRC0CNT
CRC0PNT1 32
CRC0PNT0
RESULT
CRC0FLIP
Write 8 8 8 8
4 to 1 MUX
8
CRC0DAT
CRC0FLIP
Read
Repeat Steps 2a/2b for the number of input bits (8). The algorithm is also described in the following exam-
ple.
The 16-bit Si1000/1/2/3/4/5 CRC algorithm can be described by the following code:
unsigned short UpdateCRC (unsigned short CRC_acc, unsigned char CRC_input)
{
unsigned char i; // loop counter
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
//
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x8000) == 0x8000)
{
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc << 1;
CRC_acc ^= POLY;
}
else
{
// if not, just shift the CRC value
CRC_acc = CRC_acc << 1;
}
}
The following table lists several input values and the associated outputs using the 16-bit Si1000/1/2/3/4/5
CRC algorithm:
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name CRC0IN[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name CRC0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 1 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name CRC0CNT[5:0]
Reset 0 0 0 0 0 0 0 0
CRC0FLIP
Write
CRC0FLIP
Read
Bit 7 6 5 4 3 2 1 0
Name CRC0FLIP[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
DC/DC Converter
VBAT
0.68 uH VDD_MCU/DC+
DCEN
Diode
4.7 uF Bypass
Duty
Control Logic
Cycle
Control Voltage 1uF Iload Cload
DC0CN Reference
DC/DC
DC0CF Oscillator
Lparasitic Lparasitic
GND/VBAT- GND_MCU/DC-
• The maximum total output capacitance is given in Table 4.15 on page 63. This value includes the
required 1 µF ceramic output capacitor and any additional capacitance connected to the
VDD_MCU/DC+ pin.
Once initial power-on is complete, the peak inductor current limit can be increased by software as shown in
Table 16.1. Limiting the peak inductor current can allow the device to start up near the battery’s end of life.
.
Table 16.1. IPeak Inductor Current Limit Settings
The peak inductor current is dependent on several factors including the dc load current and can be esti-
mated using following equation:
0.68 uH
DC-DC Converter 1 uF
4.7 uF
Enabled
0.9 to 1.8 V
Supply Voltage VBAT GND/VBAT- DCEN GND_MCU/
VDD_MCU/ DC-
(one-cell mode)
DC+
When the dc-dc converter “Enabled” configuration (one-cell mode) is chosen, the following guidelines
apply:
In most cases, the GND/VBAT– pin should not be externally connected to GND.
The 0.68 µH inductor should be placed as close as possible to the DCEN pin for maximum efficiency.
The 4.7 µF capacitor should be placed as close as possible to the inductor.
The current loop including GND/VBAT-, the 4.7 µF capacitor, the 0.68 µH inductor and the DCEN pin
should be made as short as possible to minimize capacitance.
The PCB traces connecting VDD_MCU/DC+ to the output capacitor and the output capacitor to
GND_MCU/DC– should be as short and as thick as possible in order to minimize parasitic inductance.
16.5. Minimizing Power Supply Noise
To minimize noise on the power supply lines, the GND/VBAT- and GND_MCU/DC- pins should be kept
separate, as shown in Figure 16.2; GND_MCU/DC- should be connected to the pc board ground plane.
The large decoupling capacitors in the input and output circuits ensure that each supply is relatively quiet
with respect to its own ground. However, connecting a circuit element "diagonally" (e.g., connecting an
external chip between VDD_MCU/DC+ and GND/VBAT-, or between VBAT and GND_MCU/DC-) can
result in high supply noise across that circuit element.
To accommodate situations in which ADC0 is sampling a signal that is referenced to one of the external
grounds, we recommend using the Analog Ground Reference (P0.1/AGND) option described in Section
5.12. This option prevents any voltage differences between the internal chip ground and the external
grounds from modulating the ADC input signal. If this option is enabled, the P0.1 pin should be tied to the
from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be
small compared to the current from VDD_MCU/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL and
ILIMIT bits, the battery internal resistance, the load current, and the difference between the VBAT voltage
level and the programmed output voltage. The wake up time can be as short as 2 µs, though it is more
commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.
See Section “14. Power Management” on page 148 for more information about sleep mode.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 1 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
Name Reserved CLKDIV[1:0] AD0CKINV CLKINV ILIMIT VDDSLP CLKSEL
Type R R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
SFR Page = 0x0; SFR Address = 0x96
Bit Name Function
7 Reserved Read = 0b; Must write 0b.
6:5 CLKDIV[1:0] DC-DC Clock Divider.
Divides the dc-dc converter clock when the system clock is selected as the clock
source for dc-dc converter. These bits are ignored when the dc-dc converter is
clocked from its local oscillator.
00: The dc-dc converter clock is system clock divided by 1.
01: The dc-dc converter clock is system clock divided by 2.
10: The dc-dc converter clock is system clock divided by 4.
11: The dc-dc converter clock is system clock divided by 8.
4 AD0CKINV ADC0 Clock Inversion (Clock Invert During Sync).
Inverts the ADC0 SAR clock derived from the dc-dc converter clock when the SYNC
bit (DC0CN.3) is enabled. This bit is ignored when the SYNC bit is set to zero.
0: ADC0 SAR clock is inverted.
1: ADC0 SAR clock is not inverted.
3 CLKINV DC-DC Converter Clock Invert.
Inverts the system clock used as the input to the dc-dc clock divider.
0: The dc-dc converter clock is not inverted.
1: The dc-dc converter clock is inverted.
2 ILIMIT Peak Current Limit Threshold.
Sets the threshold for the maximum allowed peak inductor current. See Table 16.1
for peak inductor current levels.
0: Peak inductor current is set at a lower level.
1: Peak inductor current is set at a higher level.
1 VDDSLP VDD_MCU/DC+ Sleep Mode Connection.
Specifies the power source for VDD_MCU/DC+ in Sleep Mode when the dc-dc con-
verter is enabled.
0: VDD_MCU/DC+ connected to VBAT in Sleep Mode.
1: VDD_MCU/DC+ is floating in Sleep Mode.
0 CLKSEL DC-DC Converter Clock Source Select.
Specifies the dc-dc converter clock source.
0: The dc-dc converter is clocked from its local oscillator.
1: The dc-dc converter is clocked from the system clock.
The REG0CN register allows the Precision Oscillator Bias to be disabled, saving approximately 80 µA in
all non-Sleep power modes. This bias should only be disabled when the precision oscillator is not being
used.
The internal regulator (VREG0) is disabled when the device enters Sleep Mode and remains enabled
when the device enters Suspend Mode. See Section “14. Power Management” on page 148 for complete
details about low power modes.
Bit 7 6 5 4 3 2 1 0
Name Reserved Reserved OSCBIAS Reserved
Reset 0 0 0 1 0 0 0 0
VDD_MCU/DC+ VBAT
*On Si1000/1/2/3 devices,
VBAT is internally
connected to VDD_MCU.
Power On
Supply Reset
Monitor (wired-OR)
Comparator 0
Px.x +
+ -
0 RST
Enable
- C0RSEF
Px.x
SmaRTClock
RTC0RE
Missing Reset
Clock Funnel
Detector
(one-
shot) PCA
EN
WDT (Software Reset)
SWRSF
EN
Illegal Flash
Enable
Enable
Operation
MCD
WDT
System
Clock
CIP-51
Microcontroller System Reset System Reset
Power Management
Core Block (PMU0)
Power-On Reset
Reset
Extended Interrupt
Handler
VBAT
~0.8 VPOR
0.6
AT
VB
~0.5
See specification
table for min/max
voltages.
t
RST
Logic HIGH
TPORDelay TPORDelay
Logic LOW
Power-On Power-On
Reset Reset
VDD_MCU/DC+
V WARN
V RST
VBAT
V POR
t
VDDOK
SLEEP
RST
Important Notes:
The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section
“4. Electrical Characteristics” on page 38 for complete electrical characteristics of the VDD_MCU
monitor.
Software should take care not to inadvertently disable the VDD Monitor as a reset source when writing
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the VDD Monitor enabled as a reset source.
The VDD_MCU supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD_MCU supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD_MCU supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 38 for minimum VDD_MCU Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD_MCU supply monitor and selecting it as a reset source is shown below:
Bit 7 6 5 4 3 2 1 0
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
18.8. SmaRTClock (Real Time Clock) Reset
The SmaRTClock can generate a system reset on two events: SmaRTClock Oscillator Fail or SmaRT-
Clock Alarm. The SmaRTClock Oscillator Fail event occurs when the SmaRTClock Missing Clock Detector
is enabled and the SmaRTClock clock is below approximately 20 kHz. A SmaRTClock alarm event occurs
when the SmaRTClock Alarm is enabled and the SmaRTClock timer value matches the ALARMn regis-
ters. The SmaRTClock can be configured as a reset source by writing a 1 to the RTC0RE flag (RST-
SRC.7). The SmaRTClock reset remains functional even when the device is in the low power Suspend or
Sleep mode. The state of the RST pin is unaffected by this reset.
18.9. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Bit 7 6 5 4 3 2 1 0
CLKDIV2
CLKDIV1
CLKDIV0
CLKRDY
IOSCEN
CLKSL1
CLKSL0
VDD
IFRDY
XTAL2 XTAL2
EN
Clock Divider
smaRTClock Oscillator
Option 4
XTAL2
XOSCMD2
XOSCMD1
XOSCMD0
XTLVLD
OSCXCN
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
15 pF
XTAL1
25 MHz
10 M
XTAL2
15 pF
Important Note on External Crystals: Crystal oscillator circuits are quite sensitive to PCB layout. The
crystal should be placed as close as possible to the XTAL pins on the device. The traces should be as
short as possible and shielded with ground plane from any other traces which could introduce noise or
interference.
When using an external crystal, the external oscillator drive circuit must be configured by software for Crys-
tal Oscillator Mode or Crystal Oscillator Mode with divide by 2 stage. The divide by 2 stage ensures that the
clock derived from the external oscillator has a duty cycle of 50%. The External Oscillator Frequency Con-
trol value (XFCN) must also be specified based on the crystal frequency. The selection should be based on
Table 19.1. For example, a 25 MHz crystal requires an XFCN setting of 111b.
When the crystal oscillator is first enabled, the external oscillator valid detector allows software to deter-
mine when the external system clock has stabilized. Switching to the external oscillator before the crystal
oscillator has stabilized can result in unpredictable behavior. The recommended procedure for starting the
crystal is:
1. Configure XTAL1 and XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
3. Poll for XTLVLD => 1.
4. Switch the system clock to the external oscillator.
3
1.23 10
f = -------------------------
RC
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
To determine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register,
first select the RC network value to produce the desired frequency of oscillation. For example, if the fre-
quency desired is 100 kHz, let R = 246 k and C = 50 pF:
3 3
1.23 10 1.23 10
f = ------------------------- = ------------------------- = 100 kHz
RC 246 50
where
f = frequency of clock in MHz; R = pull-up resistor value in k
VDD = power supply voltage in Volts; C = capacitor value on the XTAL2 pin in pF
Referencing Table 19.2, the recommended XFCN setting is 010.
When the RC oscillator is first enabled, the external oscillator valid detector allows software to determine
when oscillation has stabilized. The recommended procedure for starting the RC oscillator is:
1. Configure XTAL2 for analog I/O and disable the digital output drivers.
2. Configure and enable the external oscillator.
KF
f = ---------------------
C V DD
where
f = frequency of clock in MHzR = pull-up resistor value in k
VDD = power supply voltage in VoltsC = capacitor value on the XTAL2 pin in pF
Below is an example of selecting the capacitor and finding the frequency of oscillation Assume VDD = 3.0 V
and f = 150 kHz:
KF
f = ---------------------
C V DD
KF
0.150 MHz = -----------------
C 3.0
Since a frequency of roughly 150 kHz is desired, select the K Factor from Table 19.2 as KF = 22:
22
0.150 MHz = -----------------------
C 3.0 V
22
C = -----------------------------------------------
0.150 MHz 3.0 V
C = 48.8 pF
Therefore, the XFCN value to use in this example is 011 and C is approximately 50 pF.
The recommended startup procedure for C mode is the same as RC mode.
19.3.4. External CMOS Clock Mode
If an external CMOS clock is used as the external oscillator, the clock should be directly routed into XTAL2.
The XTAL2 pin should be configured as a digital input. XTAL1 is not used in external CMOS clock mode.
The external oscillator valid detector will always return zero when the external oscillator is configured to
External CMOS Clock mode.
19.4. Special Function Registers for Selecting and Configuring the System Clock
The clocking sources on Si1000/1/2/3/4/5 devices are enabled and configured using the OSCICN,
OSCICL, OSCXCN and the SmaRTClock internal registers. See Section “20. SmaRTClock (Real Time
Clock)” on page 187 for SmaRTClock register descriptions. The system clock source for the MCU can be
selected using the CLKSEL register. To minimize active mode current, the oneshot timer which sets Flash
read time should by bypassed when the system clock is greater than 10 MHz. See the FLSCL register
description for details.
The clock selected as the system clock can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. When switching
between two clock divide values, the transition may take up to 128 cycles of the undivided clock source.
The CLKRDY flag can be polled to determine when the new clock divide value has been applied. The clock
divider must be set to "divide by 1" when entering Suspend or Sleep Mode.
The system clock source may also be switched on-the-fly. The switchover takes effect after one clock
period of the slower oscillator.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 1 1 0 1 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 1 1 1 1
Note: It is recommended to use read-modify-write operations such as ORL and ANL to set or clear the enable bit of
this register.
Bit 7 6 5 4 3 2 1 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
XTAL4 XTAL3
SmaRTClock
Power/
Programmable Load Capacitors Clock
Mgmt
SmaRTClock Oscillator
32-Bit
SmaRTClock
Timer
CIP-51 CPU
SmaRTClock State Machine
Wake-Up
Interrupt
Interface
Internal CAPTUREn Registers
Registers RTC0CN
RTC0KEY
RTC0XCN
RTC0XCF RTC0ADR
RTC0PIN
RTC0DAT
ALARMn
Note: The RTC0ADR and RTC0DAT registers will retain their state upon a device reset.
20.1.3. RTC0ADR Short Strobe Feature
Reads and writes to indirect SmaRTClock registers normally take 7 system clock cycles. To minimize the
indirect register access time, the Short Strobe feature decreases the read and write access time to 6 sys-
tem clocks. The Short Strobe feature is automatically enabled on reset and can be manually enabled/dis-
abled using the SHORT (RTC0ADR.4) control bit.
Recommended Instruction Timing for a single register read with short strobe enabled:
mov RTC0ADR, #095h
nop
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov RTC0ADR, #010h
mov RTC0DAT, #05h
nop
mov RTC0DAT, #06h
nop
mov RTC0DAT, #07h
nop
mov RTC0DAT, #08h
nop
Bit 7 6 5 4 3 2 1 0
Name RTC0ST[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRT-
Clock Interface.
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name RTC0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
20.2.4. Automatic Gain Control (Crystal Mode Only) and SmaRTClock Bias Doubling
Automatic Gain Control allows the SmaRTClock oscillator to trim the oscillation amplitude of a crystal in
order to achieve the lowest possible power consumption. Automatic Gain Control automatically detects
when the oscillation amplitude has reached a point where it safe to reduce the drive current, therefore, it
may be enabled during crystal startup. It is recommended to enable Automatic Gain Control in most sys-
tems which use the SmaRTClock oscillator in Crystal Mode. The following are recommended crystal spec-
ifications and operating conditions when Automatic Gain Control is enabled:
ESR < 50 k
Load Capacitance < 10 pF
Supply Voltage < 3.0 V
Temperature > –20 °C
When using Automatic Gain Control, it is recommended to perform an oscillation robustness test to ensure
that the chosen crystal will oscillate under the worst case condition to which the system will be exposed.
The worst case condition that should result in the least robust oscillation is at the following system condi-
tions: lowest temperature, highest supply voltage, highest ESR, highest load capacitance, and lowest bias
current (AGC enabled, Bias Double Disabled).
To perform the oscillation robustness test, the SmaRTClock oscillator should be enabled and selected as
the system clock source. Next, the SYSCLK signal should be routed to a port pin configured as a push-pull
digital output. The positive duty cycle of the output clock can be used as an indicator of oscillation robust-
ness. As shown in Figure 20.2, duty cycles less than 55% indicate a robust oscillation. As the duty cycle
approaches 60%, oscillation becomes less reliable and the risk of clock failure increases. Increasing the
bias current (by disabling AGC) will always improve oscillation robustness and will reduce the output
clock’s duty cycle. This test should be performed at the worst case system conditions, as results at very
low temperatures or high supply voltage will vary from results taken at room temperature or low supply
voltage.
Notes:
The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling
SmaRTClock Alarm Events (RTC0AEN = 0).
If AutoReset is disabled, disabling (RTC0AEN = 0) then Re-enabling Alarm Events (RTC0AEN = 1)
after a SmaRTClock Alarm without modifying ALARMn registers will automatically schedule the next
alarm after 2^32 SmaRTClock cycles (approximately 36 hours using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. See
Section “14. Power Management” on page 148 for information on how to capture a SmaRTClock Alarm
event using a flag which is not automatically cleared by hardware.
Bit 7 6 5 4 3 2 1 0
Name RTC0EN MCLKEN OSCFAIL RTC0TR RTC0AEN ALRM RTC0SET RTC0CAP
Type R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 Varies 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Bit 7 6 5 4 3 2 1 0
Name RTC0PIN
Type W
Reset 0 1 1 0 0 1 1 1
Bit 7 6 5 4 3 2 1 0
Name CAPTURE[31:0]
Reset 0 0 0 0 0 0 0 0
SmaRTClock Addresses: CAPTURE0 = 0x00; CAPTURE1 = 0x01; CAPTURE2 =0x02; CAPTURE3: 0x03.
Bit Name Function
7:0 CAPTURE[31:0] SmaRTClock Timer Capture.
These 4 registers (CAPTURE3–CAPTURE0) are used to read or set the 32-bit
SmaRTClock timer. Data is transferred to or from the SmaRTClock timer when
the RTC0SET or RTC0CAP bits are set.
Note: The least significant bit of the timer capture value is in CAPTURE0.0.
Bit 7 6 5 4 3 2 1 0
Name ALARM[31:0]
Reset 0 0 0 0 0 0 0 0
SmaRTClock Addresses: ALARM0 = 0x08; ALARM1 = 0x09; ALARM2 = 0x0A; ALARM3 = 0x0B
Bit Name Function
7:0 ALARM[31:0] SmaRTClock Alarm Programmed Value.
These 4 registers (ALARM3–ALARM0) are used to set an alarm event for the
SmaRTClock timer. The SmaRTClock alarm should be disabled (RTC0AEN=0)
when updating these registers.
Note: The least significant bit of the alarm programmed value is in ALARM0.0.
External Interrupts
Priority EX0 and EX1
Decoder
PnMDOUT,
2 PnMDIN Registers
Highest UART
Priority
SPI0 4
SPI1
P0.0
(Internal Digital Signals)
2
SMBus Digital P0
Crossbar I/O
8 Cells
CP0 4
CP1 P0.7
Outputs
SYSCLK P1.5
8
P1
7 I/O P1.6
PCA
Cells
P1.7
Lowest 2
T0, T1
Priority
8 P2.0
8
P0 (P0.0-P0.7) P2
I/O P2.6
(Port Latches)
8 Cell
P2.7
P1 (P1.0-P1.7)
To Analog Peripherals
8 (ADC0, CP0, and CP1 inputs, No analog functionality
VREF, IREF0, AGND) available on P2.7
P2 (P2.0-P2.7)
Note: P1.0, P1.1, P1.2, and P1.4 are internally connected to the
EZRadioPRO peripheral. P1.3 is not internally or externally connected.
P2.4, P2.5, and P2.6 are only available on Si1000/1/2/3
WEAKPUD
(Weak Pull-Up Disable)
PnMDOUT.x
(1 for push-pull) VDD/DC+ VDD/DC+
(0 for open-drain)
XBARE
(WEAK)
(Crossbar
Enable)
PORT
Pn.x – Output PAD
Logic Value
(Port Latch or
Crossbar)
PnMDIN.x GND
(1 for digital)
(0 for analog)
To/From Analog
Peripheral
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
UART0, SPI1, SPI0, SMBus, Any Port pin available for assignment by the XBR0, XBR1, XBR2
CP0 and CP1 Outputs, Sys- Crossbar. This includes P0.0–P2.6 pins which
tem Clock Output, PCA0, have their PnSKIP bit set to 0.
Timer0 and Timer1 External Note: The Crossbar will always assign UART0
Inputs. and SPI1 pins to fixed locations.
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
P0 P1 P2
CNVSTR
XTAL1
XTAL2
EZRadioPRO
AGND
IREF0
VREF
C2D
SF Signals Serial
Interface
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
RX0
No Connect
MOSI (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0) (*4-Wire SPI Only)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 X
P0SKIP[0:7] P1SKIP[0:7] P2SKIP[0:7]
P0 P1 P2
CNVSTR
XTAL1
XTAL2
EZRadioPRO
AGND
IREF0
VREF
C2D
SF Signals Serial
Interface
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
TX0
RX0
No Connect
MOSI (SPI1)
NSS* (SPI1)
SCK (SPI0)
MISO (SPI0)
MOSI (SPI0)
NSS* (SPI0) (*4-Wire SPI Only)
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 X
P0SKIP[0:7] P1SKIP[0:7] P2SKIP[0:7]
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P0MASK[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P0MAT[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P1MASK[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P1MAT[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
21.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic. The only exception to this is P2.7, which can only be
used for digital I/O.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
The drive strength of the output drivers are controlled by the Port Drive Strength (PnDRV) registers. The
default is low drive strength. See Section “4. Electrical Characteristics” on page 38 for the difference in out-
put drive strength between the two modes.
Bit 7 6 5 4 3 2 1 0
Name P0[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P0SKIP[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P0MDIN[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P0MDOUT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P0DRV[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P1[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P1SKIP[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P1MDIN[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P1MDOUT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P1DRV[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P2[7:0]
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P2SKIP[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Type R/W
Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
Name P2MDOUT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name P2DRV[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
SFR Bus
SPI1EN
WCOL1
MSTEN
RXBMT
MODFn
CKPHA
CKPOL
NSSIN
SRMT
SPIF1
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
Clock Divide
SYSCLK
Logic
Write Read
SPI0DAT SPI0DAT
SFR Bus
Figure 22.1. EZRadioPRO Serial Interface Block Diagram
Address Data
MSB
MSB LSB
SDI
MOSI RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
SCLK
NSS
nSEL
To read back data from the transceiver, the R/W bit must be set to 0 followed by the 7-bit address of the
register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored on the MOSI pin
when R/W = 0. The next eight negative edge transitions of the SCK signal will clock out the contents of the
selected register. The data read from the selected register will be available on the MISO output. The READ
function is shown in Figure 22.3. After the READ function is completed the MISO signal will remain at
either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When NSS goes high the
MISO output pin will be pulled high by internal pullup.
SCLK
SCL
NSS
nSEL
SCLK
SCL
nSEL
NSS
SCLK
SCL
First Bit
SDO
MISO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
nSEL
NSS
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 1 1
Bit 7 6 5 4 3 2 1 0
Reset 0 0 0 0 0 1 1 0
Bit 7 6 5 4 3 2 1 0
Name SCR1[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name SPI1DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
SCK*
T T
MCKH MCKL
T T
MIS MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
SHUTDOWN
SHUT DWN
IDLE*
TX RX
*Five Different Options for IDLE
The operational status of the EZRadioPRO peripheral can be read from "Register 02h. Device Status".
23.2. Interrupts
The EZRadioPRO peripheral is capable of generating an interrupt signal (nIRQ) when certain events
occur. The nIRQ pin is driven low to indicate a pending interrupt request. The EZRadioPRO interrupt
does not have an internal interrupt vector. To use the interrupt, the nIRQ pin must be looped back
to an external interrupt input. This interrupt signal will be generated when any one (or more) of the inter-
rupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low
until the Interrupt Status Register(s) (Registers 03h–04h) containing the active Interrupt Status bit is read.
The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be
enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h–06h). All
enabled interrupt bits will be cleared when the corresponding interrupt status register is read. If the inter-
rupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at
anytime in the Interrupt Status registers.
03 R Interrupt Status 1 ifferr itxffafull itxffaem irxffafull iext ipksent ipkvalid icrcerror —
04 R Interrupt Status 2 iswdet ipreaval ipreainval irssi iwut ilbd ichiprdy ipor —
enrxffa- encrcer-
05 R/W Interrupt Enable 1 enfferr entxffafull entxffaem enext enpksent enpkvalid 00h
full ror
enpreain-
06 R/W Interrupt Enable 2 enswdet enpreava enrssi enwut enlbd enchiprdy enpor 01h
val
See “AN440: EZRadioPRO Detailed Register Descriptions” for a complete list of interrupts.
23.3. System Timing
The system timing for TX and RX modes is shown in Figures 23.2 and 23.3. The figures demonstrate tran-
sitioning from STANDBY mode to TX or RX mode through the built-in sequencer of required steps. The
user only needs to program the desired mode, and the internal sequencer will properly transition the part
from its current mode.
The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow
for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting
of 100 µs. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 µs. Under certain
applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact appli-
cations support if faster turnaround time is desired.
PA RAMP DOWN
PRE PA RAMP
PA RAMP UP
PLL CAL
PLL T0
PLLTS
XTAL Settling
TX Packet
Time
600us
Configurable 5-20us, Recommend 5us
50us, May be skipped
6us, Fixed
Configurable 0-70us, Default = 50us
PLL CAL
PLL T0
PLLTS
XTAL Settling
RX Packet
Time
600us
f OUT 10MHz ( N F )
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Off-
set (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the
synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming
data; this is discussed further in “Frequency Deviation” on page 245. Also, a fixed offset can be added to
fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the
fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency
is shown below:
The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connect-
ing a ÷2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Regis-
ter 75h. Frequency Band Select". This effectively partitions the entire 240–960 MHz frequency range into
two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of
fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer
part has a fixed offset of 24 added to it as shown in the formula above. Table 23.3 demonstrates the selec-
tion of fb[4:0] for the corresponding frequency band.
After selection of the fb (N) the fractional component may be solved with the following equation:
fTX
fc[15 : 0] fb[4 : 0] 24 * 64000
10 MHz * (hbsel 1)
fb and fc are the actual numbers stored in the corresponding registers.
hbsel=0 hbsel=1
0 24 240–249.9 MHz 480–499.9 MHz
1 25 250–259.9 MHz 500–519.9 MHz
2 26 260–269.9 MHz 520–539.9 MHz
3 27 270–279.9 MHz 540–559.9 MHz
4 28 280–289.9 MHz 560–579.9 MHz
5 29 290–299.9 MHz 580–599.9 MHz
6 30 300–309.9 MHz 600–619.9 MHz
7 31 310–319.9 MHz 620–639.9 MHz
8 32 320–329.9 MHz 640–659.9 MHz
The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz (30 MHz ÷ 32) to
achieve the correct Intermediate Frequency (IF) when RX mode is entered. Low-side injection is used in
the RX Mixing architecture; therefore, no frequency reprogramming is required when using the same TX
frequency and switching between RX/TX modes.
23.3.3. Easy Frequency Programming for FHSS
While Registers 73h–77h may be used to program the carrier frequency of the transceiver, it is often easier
to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also,
there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is
desirable to change frequency by programming a single register. Once the channel step size is set, the fre-
quency may be changed by a single register corresponding to the channel number. A nominal frequency is
first set using Registers 73h–77h, as described above. Registers 79h and 7Ah are then used to set a chan-
nel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size
(fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency
Hopping Channel Select Register then selects channels based on multiples of the step size.
For example: if the nominal frequency is set to 900 MHz using Registers 73h–77h and the channel step
size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size". For example, if the "Register
79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz.
Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to
program the fhch[7:0] register in order to change the frequency.
f fd [8 : 0] 625Hz
f
fd [8 : 0] f = peak deviation
625Hz
f
Frequency
fcarrier
Time
The previous equation should be used to calculate the desired frequency deviation. If desired, frequency
modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center fre-
quency; see “Modulation Type” on page 248 for further details.
DesiredOffset
fo[9 : 0]
156.25Hz (hbsel 1)
The adjustment range in high band is ±160 kHz and in low band it is ±80 kHz. For example to compute an
offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of –50 kHz in high band
mode the fo[9:0] register should be set to 360h.
73 R/W Frequency Offset fo[7] fo[6] fo[5] fo[4] fo[3] fo[2] fo[1] fo[0] 00h
74 R/W Frequency Offset fo[9] fo[8] 00h
When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one
byte of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened
from 40 bits to 32 bits. Note that with the AFC disabled, the preamble length must still be long enough to
settle the receiver and to detect the preamble (see “Preamble Length” on page 263). The AFC corrects the
detected frequency offset by changing the frequency of the Fractional-N PLL. When the preamble is
detected, the AFC will freeze for the remainder of the packet. In multi-packet mode the AFC is reset at the
end of every packet and will re-acquire the frequency offset for the next packet. The AFC loop includes a
bandwidth limiting mechanism improving the rejection of out of band signals. When the AFC loop is
enabled, its pull-in-range is determined by the bandwidth limiter value (AFCLimiter) which is located in reg-
ister 2Ah.
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
The AFC Limiter register is an unsigned register and its value can be obtained from the EZRadioPRO Reg-
ister Calculator spreadsheet.
The amount of error correction feedback to the Fractional-N PLL before the preamble is detected is con-
trolled from afcgearh[2:0]. The default value 000 relates to a feedback of 100% from the measured fre-
quency error and is advised for most applications. Every bit added will half the feedback but will require a
longer preamble to settle.
The AFC operates as follows. The frequency error of the incoming signal is measured over a period of two
bit times, after which it corrects the local oscillator via the Fractional-N PLL. After this correction, some time
is allowed to settle the Fractional-N PLL to the new frequency before the next frequency error is measured.
The duration of the AFC cycle before the preamble is detected can be programmed with shwait[2:0]. It is
advised to use the default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for
settling). If shwait[2:0] is programmed to 3'b000, there is no AFC correction output. It is advised to use the
default value 001, which sets the AFC cycle to 4 bit times (2 for measurement and 2 for settling).
The AFC correction value may be read from register 2Bh. The value read can be converted to kHz with the
following formula:
AFC Correction = 156.25Hz x (hbsel +1) x afc_corr[7: 0]
Frequency Correction
RX TX
AFC disabled Freq Offset Register Freq Offset Register
AFC enabled AFC Freq Offset Register
16 + 5 txdtrtscale
DR_TX(kbps) 2
txdr[15:0] = ------------------------------------------------------------------------------------
1 MHz
For data rates higher than 100 kbps, Register 58h should be changed from its default of 80h to C0h. Non-
optimal modulation and increased eye closure will result if this setting is not made for data rates higher
than 100 kbps. The txdr register is only applicable to TX mode and does not need to be programmed for
RX mode. The RX bandwidth which is partly determined from the data rate is programmed separately.
TX Modulation Time Domain Waveforms -- FSK vs. GFSK TX Modulation Spectrum -- FSK vs GFSK (Continuous PRBS)
1.5 -20
1.0
ModSpectrum_FSK
SigData_FSK[0,::]
-40
0.5
0.0 -60
-0.5
-80
-1.0
-1.5 -100
1.0 -20
ModSpectrum_GFSK
SigData_GFSK[0,::]
0.5 -40
0.0 -60
-0.5 -80
-1.0 -100
0 50 100 150 200 250 300 350 400 450 500 -250 -200 -150 -100 -50 0 50 100 150 200 250
time, usec freq, KHz
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing
purposes.
In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time) output to GPIO
pins. The microcontroller may then process the RX data without using the FIFO or packet handler functions
of the RFIC. In RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the pre-
amble detection threshold (SPI Register 35h) must still be programmed. Once the preamble is detected,
certain bit timing functions within the RX Modem change their operation for optimized performance over
the remainder of the packet. It is not required that a Sync word be present in the packet in RX Direct mode;
however, if the Sync word is absent then the skipsyn bit in SPI Register 33h must be set, or else the bit tim-
ing and tracking function within the RX Modem will not be configured for optimum performance.
23.4.2.3. Direct Synchronous Mode
In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In
direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external
device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal
to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock sig-
nal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge
of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is con-
trolled by the programmed data rate of the RFIC; no TX Data bits are made available at the input of the
RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external
source are transmitted directly in real-time (i.e., not stored internally for later transmission).
All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in
the next section, there are limits on modulation types in TX direct asynchronous mode.
23.4.2.4. Direct Asynchronous Mode
In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream.
Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data
applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need
for a TX Clock output signal from the RFIC, as there is no synchronous "handshaking" between the RFIC
and the external data source. The TX Data bits supplied by the external source are transmitted directly in
real-time (i.e., not stored internally for later transmission).
It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode.
The chip still internally samples the incoming TX Data stream to determine when edge transitions occur;
however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples
the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accu-
rately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course,
it is still necessary to program the desired peak frequency deviation.)
Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not
available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data
rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming
data.
nIRQ
SDN
XOUT
XIN
Px.x
VDD_RF VDD_DIG
TX Px.x
Direct synchronous modulation. Full
control over the serial interface & using
Matching RXp Px.x interrupt. Bitrate clock and modulation
RXn via GPIO’s.
NC
GPIO_1
GPIO_0
VR_DIG
GPIO_2
ANT1
GPIO configuration
GP1 : TX DATA clock output
GP2 : TX DATA input
DataCLK
MOD(Data)
XOUT
XIN
RXn
NC GPIO configuration
GP2 : TX DATA input
GPIO_1
GPIO_0
VR_DIG
GPIO_2
ANT1
MOD(Data)
mode it will be the data to be modulated and transmitted. In RX mode it will be the received demodulated
data. Figure 23.9 demonstrates using MOSI and MISO as the TX/RX data and clock:
TX on TX off RX on RX off
TX mode RX mode
command command command command
NSS
MOSI SPI input don’t care SPI input MOD input SPI input don’t care SPI input Data output SPI input
If the MISO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by
programming Reg 0Eh bit 3.
23.4.3. PN9 Mode
In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The
primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having
to provide data.
23.5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
23.5.1. RX LNA
Depending on the part, the input frequency range for the LNA is between 240–960 MHz. The LNA provides
gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of
gain control which is controlled by the analog gain control (AGC) algorithm. The AGC algorithm adjusts the
gain of the LNA and PGA so the receiver can handle signal levels from sensitivity to +5 dBm with optimal
performance.
In the Si1002/3, the TX and RX may be tied directly. See the TX/RX direct-tie reference design available
on www.silabs.com. When the direct tie is used the lna_sw bit in Register 6Dh, TX Power must be set.
23.5.2. RX I-Q Mixer
The output of the LNA is fed internally to the input of the receive mixer. The receive mixer is implemented
as an I-Q mixer that provides both I and Q channel outputs to the programmable gain amplifier. The mixer
consists of two double-balanced mixers whose RF inputs are driven in parallel, local oscillator (LO) inputs
are driven in quadrature, and separate I and Q Intermediate Frequency (IF) outputs drive the programma-
ble gain amplifier. The receive LO signal is supplied by an integrated VCO and PLL synthesizer operating
between 240–960 MHz. The necessary quadrature LO signals are derived from the divider at the VCO out-
put.
23.5.3. Programmable Gain Amplifier
The programmable gain amplifier (PGA) provides the necessary gain to boost the signal level into the
dynamic range of the ADC. The PGA must also have enough gain switching to allow for large input signals
to ensure a linear RSSI range up to –20 dBm. The PGA has steps of 3 dB which are controlled by the AGC
algorithm in the digital modem.
bandwidth-time product (BT) is 0.5 for all programmed data rates, but it may not be adjusted to other val-
ues.
23.5.6. Synthesizer
An integrated Sigma Delta (ΣΔ) Fractional-N PLL synthesizer capable of operating from 240–960 MHz is
provided on-chip. Using a ΣΔ synthesizer has many advantages; it provides flexibility in choosing data
rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the
loop in the digital domain through the fractional divider which results in very precise accuracy and control
over the transmit deviation.
Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency
and channel spacing in the range from 240–960 MHz with a frequency resolution of 156.25 Hz (Low band)
or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123–256 kbps, and the
frequency deviation can be programmed between ±1–320 kHz. These parameters may be adjusted via
registers as shown in “Frequency Control” on page 242.
TX
Fref = 10 M Selectable
PFD CP LPF Divider RX
VCO
TX Delta-
Modulation Sigma
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-
chip inductors. The output of the VCO is followed by a configurable divider which will divide down the sig-
nal to the desired output frequency band. The modulus of the variable divide-by-N divider stage is con-
trolled dynamically by the output from the - modulator. The tuning resolution is sufficient to tune to the
commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240–
960 MHz.
23.5.6.1. VCO
The output of the VCO is automatically divided down to the correct output frequency depending on the
hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select". In receive mode, the LO frequency is
automatically shifted downwards by the IF frequency of 937.5 kHz, allowing transmit and receive operation
on the same frequency. The VCO integrates the resonator inductor and tuning varactor, so no external
VCO components are required.
The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will
automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this
might not be desirable so the VCO calibration may be skipped by setting the appropriate register.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load
capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load
capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load
Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps
(97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing
the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by
the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If
the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning.
Additional information on calculating Cext and crystal selection guidelines is provided in “AN417: Si4x3x
Family Crystal Oscillator.”
If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency
Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as dis-
cussed in “Frequency Control” on page 242.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for
the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration
are discussed further in “Output Clock” on page 267.
The transceiver may also be driven with an external 30 MHz clock signal through the XOUT pin. When
driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
23.5.9. Regulators
There are a total of six regulators integrated onto the transceiver. With the exception of the digital regulator,
all regulators are designed to operate with only internal decoupling. The digital regulator requires an exter-
nal 1 µF decoupling capacitor. All regulators are designed to operate with an input supply voltage from
+1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected
directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital reg-
ulator output.
TX FIFO RX FIFO
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO
reaches these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this
register corresponds to the desired threshold value in number of bytes. When the data being filled into the
TX FIFO crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter
TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO almost empty
threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO drops below the almost empty
threshold an interrupt will be generated. The microcontroller will need to switch out of TX mode or fill more
data into the TX FIFO. The transceiver can be configured so that when the TX FIFO is empty it will auto-
matically exit the TX state and return to one of the low power states. When TX is initiated, it will transmit
the number of bytes programmed into the packet length field (Reg 3Eh). When the packet ends, the chip
will return to the state specified in register 07h. For example, if 08h is written to address 07h then the chip
will return to the STANDBY state. If 09h is written then the chip will return to the READY state.
08 R/W Operating & antdiv[2] antdiv[1] antdiv[0] rxmpk autotx enldm ffclrrx ffclrtx 00h
Function
Control 2
7C R/W TX FIFO Reserved Reserved txafthr[5] txafthr[4] txafthr[3] txafthr[2] txafthr[1] txafthr[0] 37h
Control 1
7D R/W TX FIFO Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0] 04h
Control 2
The RX FIFO has one programmable threshold called the FIFO Almost Full Threshold, rxafthr[5:0]. When
the incoming RX data crosses the Almost Full Threshold an interrupt will be generated to the microcon-
troller via the nIRQ pin. The microcontroller will then need to read the data from the RX FIFO.
7E R/W RX FIFO Reserved Reserved rxafthr[5] rxafthr[4] rxafthr[3] rxafthr[2] rxafthr[1] rxafthr[0] 37h
Control
Both the TX and RX FIFOs may be cleared or reset with the ffclrtx and ffclrrx bits. All interrupts may be
enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and “Register 06h. Inter-
rupt Enable 2.” If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin
but the bits will still be read correctly in the Interrupt Status registers.
23.6.2. Packet Configuration
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. "Reg-
ister 30h. Data Access Control" through “Register 4Bh. Received Packet Length” control the configuration,
status, and decoded RX packet data for Packet Handling. The usual fields for network communication
(such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be auto-
matically added to the data payload. The fields needed for packet generation normally change infrequently
and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the transceiver.
The general packet structure is shown in Figure 23.12. The length of each field is shown below the field.
The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields
have programmable lengths to accommodate different applications. The most common CRC polynominals
are available for selection.
Packet Length
Sync Word
TX Header
0 or 1 Byte
Bytes
D ata 1
D ata
D ata
2
3
} This w ill be sent in the first transm ission
D ata 4
D ata
D ata
5
6
} This w ill be sent in the second transm ission
D ata 7
D ata
D ata
8
9
} This w ill be sent in the third transm ission
Register
Data Header(s) txhdlen = 0 txhdlen > 0
fixpklen fixpklen
Register
Data
Length 0 1 0 1
Data
H
H
FIFO
L L
Initial state PK 1 OK PK 2 OK PK 3 PK 4 OK
ERROR
RX FIFO Addr. RX FIFO Addr. RX FIFO Addr. RX FIFO Addr. RX FIFO Addr.
0 Write 0 0 0 0
Pointer H H H H
L L L L
63 63 63 63 63
Manchester
Whitening
CRC
CRC
(Over data only)
Header/ PK
Preamble Sync
Address Length
Data CRC
1 1 1 1 1 1 1 1 0 0 0 1 0
Preamble = 0xFF First 4bits of the synch. word = 0x2
0 0 0 0 0 0 0 0 0 0 0 1 0
Preamble = 0x00 First 4bits of the synch. word = 0x2
Note: The recommended preamble length and preamble detection threshold listed above are to achieve 0% PER.
They may be shortened when occasional packet errors are tolerable.
23.6.8. Invalid Preamble Detector
When scanning channels in a frequency hopping system it is desirable to determine if a channel is valid in
the minimum amount of time. The preamble detector can output an invalid preamble detect signal. which
can be used to identify the channel as invalid. After a configurable time set in Register 60h[7:4], an invalid
preamble detect signal is asserted indicating an invalid channel. The period for evaluating the signal for
invalid preamble is defined as (inv_pre_th[3:0] x 4) x Bit Rate Period. The preamble detect and invalid pre-
amble detect signals are available in "Register 03h. Interrupt/Status 1" and “Register 04h. Interrupt/Status
2.”
23.6.9. Synchronization Word Configuration
The synchronization word length for both TX and RX can be configured in Reg 33h, synclen[1:0]. The
expected or transmitted sync word can be configured from 1 to 4 bytes as defined below:
synclen[1:0] = 00—Expected/Transmitted Synchronization Word (sync word) 3.
synclen[1:0] = 01—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2.
synclen[1:0] = 10—Expected/Transmitted Synchronization Word 3 first, followed by sync word 2,
followed by sync word 1.
synclen[1:0] = 1—Send/Expect Synchronization Word 3 first, followed by sync word 2, followed by sync
word 1, followed by sync word 0.
The sync is transmitted or expected in the following sequence: sync 3sync 2sync 1sync 0. The sync
word values can be programmed in Registers 36h–39h. After preamble detection the part will search for
sync for a fixed period of time. If a sync is not recognized in this period then a timeout will occur and the
search for preamble will be re-initiated. The timeout period after preamble detections is defined as the
value programmed into the sync word length plus four additional bits.
hden[31:24] =
BIT
WISE
chhd[31:24]
bcen[3] header3_ok
Equivalence
comparison
FFh
=
rxhd[31:24] hdch[3]
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
Reset
TP
t
t=0, reset:
VDD starts to rise Vglitch>=0.4+t*0.2V/ms
Figure 23.20. POR Glitch Parameters
The reset will initialize all registers to their default values. The reset signal is also available for output and
use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by
default on GPIO_1.
23.8.2. Output Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output on GPIO2. This fea-
ture is useful to lower BOM cost by using only one crystal in the system. The output clock on GPIO2 may
be routed to the XTAL2 input to provide a syncronized clock source between the MCU and the EZRadio-
PRO peripheral. The output clock frequency is selectable from one of 8 options, as shown below. Except
for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The
32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default
setting for GPIO2 is to output the clock signal with a frequency of 1 MHz.
Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz
clock can be automatically switched to become the output clock. This feature is called enable low fre-
quency clock and is enabled by the enlfc bit in “Register 0Ah. Microcontroller Output Clock." When enlfc =
1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided regardless of the setting of
mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin in all IDLE,
If an interrupt is triggered, the output clock will remain enabled regardless of the selected mode. As soon
as the interrupt is read the state machine will then move to the selected mode. The minimum current con-
sumption will not be achieved until the interrupt is read. For instance, if the EZRadioPRO peripheral is
commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the
interrupt has been cleared.
23.8.3. General Purpose ADC
An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature
sensor reading. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be
used to configure the ADC operation. Details of these registers are in “AN440: EZRadioPRO Detailed Reg-
ister Descriptions.”
Every time an ADC conversion is desired, bit 7 "adcstart/adcbusy" in Register 1Fh “Clock Recovery Gear-
shift Override” must be set to 1. This is a self clearing bit that will be reset to 0 at the end of the conversion
cycle of the ADC. The conversion time for the ADC is 350 µs. After this time or when the "adcstart/adc-
busy" bit is cleared, then the ADC value may be read out of “Register 11h. ADC Value."
The architecture of the ADC is shown in Figure 23.21. The signal and reference inputs of the ADC are
selected by adcsel[2:0] and adcref[1:0] in register 0Fh “ADC Configuration”, respectively. The default set-
ting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG
reference the input range of the ADC is from 0–1.02 V with an LSB resolution of 4 mV (1.02/255). Chang-
ing the ADC reference will change the LSB resolution accordingly.
A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the
amplifier is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage
(VDD) dependent gain and offset. The reference voltage of the ADC can be changed to either VDD/2 or
VDD/3. A programmable VDD dependent offset voltage can be added using soffs[3:0] in register 10h.
See “AN448: General Purpose ADC Configuration” for more details on the usage of the general purpose
ADC.
Diff. MUX
Diff. Amp.
…
…
Input MUX
aoffs [4:0] soffs [3:0]
adcsel [2:0] adcgain [1:0]
GPIO0
GPIO1
…
GPIO2
8-bit ADC
Temperature Sensor
Vin
adc [7:0]
adcsel [2:0]
Vref
0 -1020mV / 0-255
Ref MUX
VDD / 3
VDD / 2
…
VBG (1.2V)
adcref [1:0]
11 R ADC Value adc[7] adc[6] adc[5] adc[4] adc[3] adc[2] adc[1] adc[0] —
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 °C
calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in “Register
12h. Temperature Sensor Control” and setting the offset with the tvoffs[7:0] bits in “Register 13h. Tempera-
ture Value Offset.” This method adds a positive offset digitally to the ADC value that is read in “Register
11h. ADC Value.” The other method of calibration is to use the tstrim which compensates the analog cir-
cuit. This is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in “Register
12h. Temperature Sensor Control.” With this method of calibration, a negative offset may be achieved.
With both methods of calibration better than ±3 °C absolute accuracy may be achieved.
The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 23.22. The value of
the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature
in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 – 64.
300
250
200
Sensor Range 0
ADC Value
Sensor Range 1
150
Sensor Range 2
Sensor Range 3
100
50
0
-40 -20 0 20 40 60 80 100
Temperature [Celsius]
The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled (enlbd = 1 in "Register 07h.
Operating Mode and Function Control 1") the battery voltage may be read at anytime by reading "Register
1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in “Register 1Ah. Low Bat-
tery Detector Threshold". When the battery voltage level drops below the battery voltage threshold an
interrupt will be generated on nIRQ pin to the microcontroller if the LBD interrupt is enabled in “Register
32 M 2 R
WUT ms
32 .768
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by
using the R value.
14 R/W Wake-Up Timer Period 1 wtr[4] wtr[3] wtr[2] wtr[1] wtr[0] 03h
15 R/W Wake-Up Timer Period 2 wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] 00h
16 R/W Wake-Up Timer Period 3 wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtm[2] wtm[1] wtm[0] 00h
17 R Wake-Up Timer Value 1 wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[10] wtv[9] wtv[8] —
18 R Wake-Up Timer Value 2 wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] wtv[2] wtv[1] wtv[0] —
There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is
enabled in “Register 06h. Interrupt Enable 2.” If the WUT interrupt is enabled then nIRQ pin will go low
when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the
microcontroller clock output is available for the microcontroller to use to process the interrupt. The other
method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation
the chip will not change state until commanded by the microcontroller. The different modes of operating the
WUT and the current consumption impacts are demonstrated in Figure 23.23.
A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in Register 07h
"Operating & Function Control 1", GPIO0 is automatically reconfigured so that an external 32 kHz XTAL
may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so
only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as pos-
sible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode
will use the 32 kHz XTAL and not the 32 kHz RC oscillator.
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
WUT Period
GPIOX =00001
nIRQ
SPI Interrupt
Read
Chip State
Sleep
Current
Consumption
1 uA
between the WUT and the TLDC. The ldc[7:0] bits are located in “Register 19h. Low Duty Cycle Mode
Duration.” The time of the TLDC is determined by the formula below:
42R
TLDC ldc [ 7 : 0 ] ms
32 . 768
0B R/W GPIO0 gpio0drv[1] gpio0drv[0] pup0 gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] 00h
Configuration
0C R/W GPIO1 gpio1drv[1] gpio1drv[0] pup1 gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] 00h
Configuration
0D R/W GPIO2 gpio2drv[1] gpio2drv[0] pup2 gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] 00h
Configuration
0E R/W I/O Port extitst[2] extitst[1] extitst[0] itsdo dio2 dio1 dio0 00h
Configuration
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000
default setting. The default settings for each GPIO are listed below:
For a complete list of the available GPIO's see “AN440: EZRadioPRO Detailed Register Descriptions”.
The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase
the drive strength and current capability of the GPIO by changing the driver size. Special care should be
ing options is recommended: majority polling, reading the RSSI value within 1 Tb of the RSSI interrupt, or
using the RSSI threshold described in the next paragraph for Clear Channel Assessment (CCA).
27 R/W RSSI Threshold for Clear Channel Indicator rssith[7] rssith[6] rssith[5] rssith[4] rssith[3] rssith[2] rssith[1] rssith[0] 00h
For CCA, threshold is programmed into rssith[7:0] in "Register 27h. RSSI Threshold for Clear Channel
Indicator." After the RSSI is evaluated in the preamble, a decision is made if the signal strength on this
channel is above or below the threshold. If the signal strength is above the programmed threshold then the
RSSI status bit, irssi, in "Register 04h. Interrupt/Status 2" will be set to 1. The RSSI status can also be
routed to a GPIO line by configuring the GPIO configuration register to GPIOx[3:0] = 1110.
250
200
150
RSSI
100
50
0
-120 -100 -80 -60 -40 -20 0 20
In Pow [dBm]
278
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band LR CR1 CR2 LC C0 LH CH RH L0 CM LM CC1, CC2 CM2 LM2 CM3 ) &
[MHz] [nH] [pF] [pF] [nH] [pF] [nH] [pF] [Ohm] [nH] [pF] [nH] [pF] [pF] [nH] [pF]
279
Si1000/1/2/3/4/5
Note: Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions.
23. SMBus
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus interface autonomously controlling
the serial transfer of the data. Data can be transferred at up to 1/20th of the system clock as a master or
slave (this can be faster than allowed by the SMBus specification, depending on the system clock used). A
method of extending the clock-low duration is available to accommodate devices with different speed
capabilities on the same bus.
The SMBus interface may operate as a master and/or slave, and may function on a bus with multiple mas-
ters. The SMBus provides control of SDA (serial data), SCL (serial clock) generation and synchronization,
arbitration logic, and START/STOP control and generation. The SMBus peripheral can be fully driven by
software (i.e., software accepts/rejects slave addresses, and generates ACKs), or hardware slave address
recognition and automatic ACK generation can be enabled to minimize software overhead. A block dia-
gram of the SMBus peripheral and the associated SFRs is shown in Figure 23.1.
SMB0CN SMB0CF
M T S S A A A S E I B E S S S S
A X T T CR C I N N U XMMMM
SMAOK B K S H S T B B B B
T O R L M Y H T F CC
E D QO B OO T S S
R E S L E E 1 0
T D
00 T0 Overflow
01 T1 Overflow
10 TMR2H Overflow
11 TMR2L Overflow
SCL
SMBUS CONTROL LOGIC FILTER
Interrupt Arbitration
Request SCL Synchronization
SCL Generation (Master Mode) SCL C
N
SDA Control Control R
Hardware Slave Address Recognition O
Hardware ACK Generation S
IRQ Generation Data Path SDA S Port I/O
Control Control B
A
R
SMB0DAT
SDA
7 6 5 4 3 2 1 0 FILTER
S S S S S S SG S S S S S S S E
L L L L L L L C L L L L L L L H
V V V V V V V V V V V V V V A
6 5 4 3 2 1 0 MMMMMMM C
6 5 4 3 2 1 0 K
SMB0ADR SMB0ADM
N
SDA
SCL
All transactions are initiated by a master, with one or more addressed slave devices as the target. The
master generates the START condition and then transmits the slave address and direction bit. If the trans-
action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time
waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the
data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master
generates a STOP condition to terminate the transaction and free the bus. Figure 23.3 illustrates a typical
SMBus transaction.
SCL
SDA
SLA6 SLA5-0 R/W D7 D6-0
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 23.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “26. Timers” on page 326.
1
T HighMin = T LowMin = ----------------------------------------------
f ClockSourceOverflow
Equation 23.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 23.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 23.2.
f ClockSourceOverflow
BitRate = ----------------------------------------------
3
Equation 23.2. Typical SMBus Bit Rate
Figure 23.4 shows the typical SCL generation described by Equation 23.2. Notice that THIGH is typically
twice as large as TLOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 23.1.
Timer Source
Overflows
SCL
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 23.2 shows the min-
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “23.3.4. SCL Low Timeout” on page 285). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 23.4).
Bit 7 6 5 4 3 2 1 0
Name ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS[1:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name MASTER TXMODE STA STO ACKRQ ARBLOST ACK SI
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name SLV[6:0] GC
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Reset 1 1 1 1 1 1 1 0
C:\SiLabs\MCU\Examples\C8051F93x_92x\SMBus\F93x_SMBus_Slave_Multibyte_HWACK.c
The SMBus examples folder, along with examples for many additional peripherals, is created when the Sil-
icon Laboratories IDE is installed. The latest version of the IDE may be downloaded from the software
downloads page www.silabs.com/MCUDownloads on the Silicon Laboratories website.
The following issue is present when operating as a master in a multi-master SMBus configuration:
If the SMBus master loses arbitration in a multi-master system, it may cause interference on the SMBus by
driving SDA low during the ACK cycle of transfers which it is not participating. This will occur regardless of
the state of the ACK bit (SMB0CN.1).
Impact:
The SMBus master and slave participating in the transfer are prevented from generating a NACK by the
MCU because it is holding SDA low during the ACK cycle. There is a potential for the SMBus to lock up.
Workaround:
Disable Hardware Acknowledge (EHACK = 0) when the MCU is operating as a master in a multi-master
SMBus configuration.
Bit 7 6 5 4 3 2 1 0
Name SMB0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be
set up by the software prior to receiving the byte when hardware ACK generation is enabled.
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if
SMB0DAT is written while an active Master Receiver. Figure 23.6 shows a typical master read sequence.
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data
byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK
generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and
after the ACK when hardware ACK generation is enabled.
Table 23.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Vector Expected
Write
Next Status
ARBLOST
ACKRQ
Vector
Status
Mode
ACK
ACK
STO
STA
1110 0 0 X A master START was gener- Load slave address + R/W into 0 0 X 1100
ated. SMB0DAT.
1100 0 0 0 A master data or address byte Set STA to restart transfer. 1 0 X 1110
was transmitted; NACK Abort transfer. 0 1 X -
received.
0 0 1 A master data or address byte Load next data byte into 0 0 X 1100
was transmitted; ACK SMB0DAT.
received. End transfer with STOP. 0 1 X -
Master Transmitter
Table 23.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
(Continued)
Values Read Current SMbus State Typical Response Options Values to
Vector Expected
Write
Next Status
ARBLOST
ACKRQ
Vector
Status
Mode
ACK
ACK
STO
STA
0100 0 0 0 A slave byte was transmitted; No action required (expecting 0 0 X 0001
NACK received. STOP condition).
0 0 1 A slave byte was transmitted; Load SMB0DAT with next data 0 0 X 0100
ACK received. byte to transmit.
Slave Transmitter
Table 23.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
Vector Expected
Write
Next Status
ARBLOST
ACKRQ
Vector
Status
Mode
ACK
ACK
STO
STA
1110 0 0 X A master START was gener- Load slave address + R/W into 0 0 X 1100
ated. SMB0DAT.
1100 0 0 0 A master data or address byte Set STA to restart transfer. 1 0 X 1110
was transmitted; NACK Abort transfer. 0 1 X -
received.
0 0 1 A master data or address byte Load next data byte into 0 0 X 1100
was transmitted; ACK SMB0DAT.
received. End transfer with STOP. 0 1 X -
End transfer with STOP and start 1 1 X -
Master Transmitter
another transfer.
Send repeated START. 1 0 X 1110
Switch to Master Receiver Mode 0 0 1 1000
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
1000 0 0 1 A master data byte was Set ACK for next data byte; 0 0 1 1000
received; ACK sent. Read SMB0DAT.
Set NACK to indicate next data 0 0 0 1000
byte as the last data byte;
Read SMB0DAT.
Initiate repeated START. 1 0 0 1110
Switch to Master Transmitter 0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
0 0 0 A master data byte was Read SMB0DAT; send STOP. 0 1 0 -
received; NACK sent (last Read SMB0DAT; Send STOP 1 1 0 1110
Master Receiver
Table 23.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)
(Continued)
Values Read Current SMbus State Typical Response Options Values to
Vector Expected
Write
Next Status
ARBLOST
ACKRQ
Vector
Status
Mode
ACK
ACK
STO
STA
0100 0 0 0 A slave byte was transmitted; No action required (expecting 0 0 X 0001
NACK received. STOP condition).
0 0 1 A slave byte was transmitted; Load SMB0DAT with next data 0 0 X 0100
ACK received. byte to transmit.
Slave Transmitter
0000 0 0 X A slave byte was received. Set ACK for next data byte; 0 0 1 0000
Read SMB0DAT.
Set NACK for next data byte; 0 0 0 0000
Read SMB0DAT.
0010 0 1 X Lost arbitration while attempt- Abort failed transfer. 0 0 X -
ing a repeated START. Reschedule failed transfer. 1 0 X 1110
0001 0 1 X Lost arbitration due to a Abort failed transfer. 0 0 X -
detected STOP. Reschedule failed transfer. 1 0 X 1110
0000 0 1 X Lost arbitration while transmit- Abort failed transfer. 0 0 X -
ting a data byte as master. Reschedule failed transfer. 1 0 X 1110
24. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “24.1. Enhanced Baud Rate Generation” on page 307). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SET
SBUF
D Q (TX Shift)
TX
CLR
Crossbar
Zero Detector
SCON
TI
UART Baud Serial
SMODE
RB8
TB8
Interrupt
RI
TI
RI
Rx IRQ
Rx Clock
Rx Control
Load
Start
Shift 0x1FF RB8 SBUF
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus RX
Crossbar
Timer 1 UART
Overflow
TL1 2 TX Clock
TH1
Start
Detected
Overflow
RX Timer 2 RX Clock
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see Section “26.1.3. Mode 2: 8-bit Coun-
ter/Timer with Auto-Reload” on page 329). The Timer 1 reload value should be set so that overflows will
occur at two times the desired UART baud rate frequency. Note that Timer 1 may be clocked by one of six
sources: SYSCLK, SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, the external oscillator clock / 8, or an exter-
nal input T1. For any given Timer 1 clock source, the UART0 baud rate is determined by Equation 24.1-A
and Equation 24.1-B.
1
A) UartBaudRate = --- T1_Overflow_Rate
2
T1 CLK
B) T1_Overflow_Rate = --------------------------
256 – TH1
Equation 24.1. UART0 Baud Rate
Where T1CLK is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
value). Timer 1 clock frequency is selected as described in Section “26.1. Timer 0 and Timer 1” on
page 328. A quick reference for typical baud rates and system clock frequencies is given in Table 24.1
through Table 24.2. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1.
24.2. Operational Modes
UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is
selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below.
TX
RS-232 RS-232
LEVEL RX C8051Fxxx
XLTR
OR
TX TX
MCU C8051Fxxx
RX RX
MARK START
BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP
SPACE BIT
BIT TIMES
BIT SAMPLING
(1) RI0 must be logic 0, and (2) if MCE0 is logic 1, the 9th bit must be logic 1 (when MCE0 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF0, the ninth bit is stored in RB80, and the RI0 flag is set to 1. If the above conditions are not met,
SBUF0 and RB80 will not be loaded and the RI0 flag will not be set to 1. A UART0 interrupt will occur if
enabled when either TI0 or RI0 is set to 1.
MARK START
BIT D0 D1 D2 D3 D4 D5 D6 D7 D8 STOP
SPACE BIT
BIT TIMES
BIT SAMPLING
Bit 7 6 5 4 3 2 1 0
Name S0MODE MCE0 REN0 TB80 RB80 TI0 RI0
Reset 0 1 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name SBUF0[7:0]
Reset 0 0 0 0 0 0 0 0
SFR Bus
RXOVRN
NSSMD1
NSSMD0
SLVSEL
SPIBSY
MSTEN
RXBMT
CKPHA
CKPOL
TXBMT
NSSIN
SPIEN
WCOL
MODF
SRMT
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPIF
Clock Divide
SYSCLK
Logic
Tx Data MOSI
C
SPI0DAT R
SCK
Transmit Data Buffer O
Pin
S
Control Port I/O
Shift Register Logic S
Rx Data MISO
7 6 5 4 3 2 1 0 B
A
R
Receive Data Buffer NSS
Write Read
SPI0DAT SPI0DAT
SFR Bus
Figure 25.1. SPI Block Diagram
operation. Therefore, the SPIF flag serves as both a transmit-complete and receive-data-ready flag. The
data byte received from the slave is transferred MSB-first into the master's shift register. When a byte is
fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by
reading SPI0DAT.
When configured as a master, SPI0 can operate in one of three different modes: multi-master mode, 3-wire
single-master mode, and 4-wire single-master mode. The default, multi-master mode is active when
NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In this mode, NSS is an input to the device, and
is used to disable the master SPI0 when another master is accessing the bus. When NSS is pulled low in
this mode, MSTEN (SPI0CN.6) and SPIEN (SPI0CN.0) are set to 0 to disable the SPI master device, and
a Mode Fault is generated (MODF, SPI0CN.5 = 1). Mode Fault will generate an interrupt if enabled. SPI0
must be manually re-enabled in software under these circumstances. In multi-master systems, devices will
typically default to being slave devices while they are not acting as the system master device. In multi-
master mode, slave devices can be addressed individually (if needed) using general-purpose I/O pins.
Figure 25.2 shows a connection diagram between two master devices in multiple-master mode.
3-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. In this
mode, NSS is not used, and is not mapped to an external port pin through the crossbar. Any slave devices
that must be addressed in this mode should be selected using general-purpose I/O pins. Figure 25.3
shows a connection diagram between a master device in 3-wire master mode and a slave device.
4-wire single-master mode is active when NSSMD1 (SPI0CN.3) = 1. In this mode, NSS is configured as an
output pin, and can be used as a slave-select signal for a single SPI device. In this mode, the output value
of NSS is controlled (in software) with the bit NSSMD0 (SPI0CN.2). Additional slave devices can be
addressed using general-purpose I/O pins. Figure 25.4 shows a connection diagram for a master device in
4-wire master mode and two slave devices.
NSS GPIO
MISO MISO
Master MOSI MOSI
Master
Device 1 SCK SCK
Device 2
GPIO NSS
Master Slave
Device MISO MISO Device
MOSI MOSI
SCK SCK
Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
MISO Slave
MOSI Device
SCK
NSS
Figure 25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
Bit 7 6 5 4 3 2 1 0
Name SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT
Reset 0 0 0 0 0 1 1 1
Bit 7 6 5 4 3 2 1 0
Name SPIF WCOL MODF RXOVRN NSSMD[1:0] TXBMT SPIEN
Reset 0 0 0 0 0 1 1 0
Bit 7 6 5 4 3 2 1 0
Name SCR[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name SPI0DAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
SCK*
T T
MCKH MCKL
T T
MIS MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
SCK*
T T
MCKH MCKL
T T
MIS MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
NSS
T T T
SE CKL SD
SCK*
T
CKH
T T
SIS SIH
MOSI
T T T
SEZ SOH SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
NSS
T T T
SE CKL SD
SCK*
T
CKH
T T
SIS SIH
MOSI
T T T T
SEZ SOH SLH SDZ
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
26. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. Additionally, Timer 2 and
Timer 3 have a Capture Mode that can be used to measure the SmaRTClock or a Comparator period with
respect to another oscillator. This is particularly useful when using Capacitive Touch Switches. See Appli-
cation Note AN338 for details on Capacitive Touch Switch sensing.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M–
T0M) and the Clock Scale bits (SCA1–SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 26.1 for pre-scaled clock selection).
Timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. Timer 2 and
Timer 3 may be clocked by the system clock, the system clock divided by 12. Timer 2 may additionally be
clocked by the SmaRTClock divided by 8 or the Comparator0 output. Timer 3 may additionally be clocked
by the external oscillator clock source divided by 8 or the Comparator1 output.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
Bit 7 6 5 4 3 2 1 0
Name T3MH T3ML T2MH T2ML T1M T0M SCA[1:0]
Reset 0 0 0 0 0 0 0 0
0 X X Disabled
1 0 X Enabled
1 1 0 Disabled
1 1 1 Enabled
Note: X = Don't Care
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal INT1 is used with Timer 1; the INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 12.7).
CKCON TM OD IT 0 1 C F
T T T T T T S S G C T T G C T T I I I I I I I I
3 3 2 2 1 0 C C A / 1 1 A / 0 0 N N N N N N N N
M M M MMM A A T T M M T T M M 1 1 1 1 0 0 0 0
E 1 1 0 E 0 1 0 P S S S P S S S
H L H L 1 0
1 0 L L L L L L L L
2 1 0 2 1 0
P re -s ca le d C lo c k 0
SYSCLK 1
1
TF1
T0 TR1
TCLK TL0 TH0 TF0 Inte rru pt
TR0 TR0
(5 b its ) (8 b its) IE 1
TCON
G ATE0 IT 1
C ro ss b a r IE 0
IT 0
IN 0 P L XOR
IN T 0
Pre-scaled Clock 0
SYSCLK 1
T0 TF1
TCLK TL0 TR1
TF0 Interrupt
(8 bits) TR0
IE1
TCON
TR0 IT1
Crossbar IE0
GATE0 IT0
TH0 Reload
(8 bits)
IN0PL XOR
INT0
CKCON TMOD
T T T T T T S S G C T T G C T T
3 3 2 2 1 0 C C A / 1 1 A / 0 0
MMMMMMA A T T M M T T M M
E 1 1 0 E 0 1 0
H L H L 1 0
1 0
Pre-scaled Clock 0
TR1 TH0
TF1 Interrupt
(8 bits) TR1
TF0 Interrupt
SYSCLK 1 TR0
0
TCON
IE1
IT1
IE0
IT0
T0
TL0
(8 bits)
TR0
Crossbar GATE0
IN0PL XOR
INT0
Bit 7 6 5 4 3 2 1 0
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name GATE1 C/T1 T1M[1:0] GATE0 C/T0 T0M[1:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TL0[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TL1[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TH0[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TH1[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
26.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode. Timer 2 can also be used in Capture Mode to measure the SmaRTClock or
the Comparator 0 period with respect to another oscillator. The ability to measure the Comparator 0 period
with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 2 may be clocked by the system clock, the system clock divided by 12, SmaRTClock divided by 8, or
Comparator 0 output. Note that the SmaRTClock divided by 8 and Comparator 0 output is synchronized
with the system clock.
26.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8, or Comparator 0 output. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 26.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
CKCON
T2XCLK[1:0] TTTTTTSS
3 3 2 2 1 0 CC
MMMMMM A A
HLHL 10
SYSCLK / 12 00 To ADC,
To SMBus
TL2 SMBus
Overflow
SmaRTClock / 8 01 0
TR2 TCLK
TMR2L TMR2H TF2H Interrupt
TF2L
TMR2CN
Comparator 0 11 TF2LEN
1 TF2CEN
T2SPLIT
TR2
SYSCLK
T2XCLK
TMR2RLL TMR2RLH
Reload
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-
ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the
TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags
are not cleared by hardware and must be manually cleared by software.
CKCON
TTTTTTSS
T2XCLK[1:0]
3 3 2 2 1 0 CC
MMMMMM A A Reload
HLHL 1 0 TMR2RLH To SMBus
SYSCLK / 12 00
0
SmaRTClock / 8 01 TCLK
TR2 TMR2H TF2H Interrupt
TF2L
1 TF2LEN
Comparator 0 11
TMR2CN
TF2CEN
T2SPLIT
Reload TR2
TMR2RLL
SYSCLK T2XCLK
1
TCLK To ADC,
TMR2L
SMBus
T2XCLK[1:0]
CKCON
TTTTTTSS
3 3 2 2 1 0CC
SYSCLK/12 X0 MMMMMM A A
HLHL 1 0
Comparator 0 01
SmaRTClock/8 11 0
TR2 TCLK
TMR2L TMR2H
SYSCLK 1 Capture
T2XCLK1 TF2CEN
TMR2RLL TMR2RLH TF2H Interrupt
TF2L
TMR2CN
TF2LEN
TF2CEN
SmaRTClock/8 0 T2SPLIT
TR2
T2XCLK1
T2XCLK0
Comparator 0 1
Bit 7 6 5 4 3 2 1 0
Name TF2H TF2L TF2LEN TF2CEN T2SPLIT TR2 T2XCLK[1:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR2RLL[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR2RLH[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR2L[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR2H[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
26.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR2CN.3) defines
the Timer 3 operation mode. Timer 3 can also be used in Capture Mode to measure the external oscillator
source or the Comparator 1 period with respect to another oscillator. The ability to measure the
Comparator 1 period with respect to the system clock is makes using Touch Sense Switches very easy.
Timer 3 may be clocked by the system clock, the system clock divided by 12, external oscillator source
divided by 8, or Comparator 1 output. The external oscillator source divided by 8 and Comparator 1 output
is synchronized with the system clock.
26.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, external oscillator clock source divided by 8, or Comparator 1
output. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in
the Timer 3 reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in
Figure 26.7, and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled
(if EIE1.7 is set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts
are enabled and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8
bits (TMR3L) overflow from 0xFF to 0x00.
CKCON
TTTTTTSS
T3XCLK[1:0]
3 3 2 2 1 0 CC
MMMMMM A A
HLHL 1 0
SYSCLK / 12 00
To ADC
External Clock / 8 01 0
TR3 TCLK
TMR3L TMR3H TF3H Interrupt
TF3L
TMR3CN
Comparator 1 11 TF3LEN
1 TF3CEN
T3SPLIT
TR3
SYSCLK T3XCLK1
T3XCLK0
TMR3RLL TMR3RLH
Reload
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, the external oscillator clock
source divided by 8, or Comparator 1. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select
either SYSCLK or the clock defined by the Timer 3 External Clock Select bits (T3XCLK[1:0] in TMR3CN),
as follows:
The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows
from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-
flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each
time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and
TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not
cleared by hardware and must be manually cleared by software.
CKCON
T TTTT TSS
T3XCLK[1:0]
3 3 2 2 1 0CC
MMMMMM A A Reload
HLHL 1 0 TMR3RLH
SYSCLK / 12 00
0
Comparator 1 01 TCLK
TR3 TMR3H TF3H Interrupt
TF3L
1 TF3LEN
External Clock / 8 11
TMR3CN
TF3CEN
T3SPLIT
Reload TR3
TMR3RLL T3XCLK1
SYSCLK T3XCLK0
1
TCLK TMR3L To ADC
T 3X C LK [1:0]
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
S Y S C LK / 1 2 X0 M M M MMMA A
H L H L 1 0
E xternal C lock / 8 01
C om parato r 1 11 0
TR3 T C LK
TM R3L T M R 3H
S Y S C LK 1 C apture
T 3X C LK 1 TF3CEN
T M R 3R L L T M R 3 R LH T F 3H Inte rrupt
T F 3L
TMR3CN
TF3LEN
T F 3C E N
C om p arator 1 0 T 3S P LIT
TR3
T3XCLK1
T3XCLK0
E xtern al C lock / 8 1
Bit 7 6 5 4 3 2 1 0
Name TF3H TF3L TF3LEN TF3CEN T3SPLIT TR3 T3XCLK[1:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR3RLL[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR3RLH[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR3L[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TMR3H[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
SYSCLK/12
SYSCLK/4
Timer 0 Overflow PCA
16-Bit Counter/Timer
ECI CLOCK
MUX
SYSCLK
External Clock/8
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
Crossbar
Port I/O
IDLE
PCA0MD PCA0CN
C WW C C CE CCC C C C C C
I D D P P PC FRC C C C C C
D T L S S S F F F F F F F
L E C 2 1 0 5 4 3 2 1 0 To SFR Bus
K PCA0L
read
Snapshot
Register
SYSCLK/12
000
SYSCLK/4
001
Timer 0 Overflow 0
010 Overflow
PCA0H PCA0L To PCA Interrupt System
1
ECI
011
CF
SYSCLK
100
External Clock/8 To PCA Modules
101
(for n = 0 to 5)
PCA0CPMn PCA0CN PCA0MD PCA0PWM
P ECCMT P E CCCCCCCC C WW CCCE A CE C C
WC A A AOWC FRCCCCCC I DD PPPC ROC L L
MOPP TGMC FFFFFF DT L SSSF S VO S S
1 MP N n n n F 5 4 3 2 1 0 LEC 2 1 0 EFV E E
6 n n n n K L L L
n 1 0
PCA Counter/Timer 8, 9,
Set 8, 9, 10, or 11 bit Operation
10 or 11-bit Overflow
PCA Counter/Timer 16- 0
0
bit Overflow 1
1 EPCA0 EA
ECCF0
0 0 0 Interrupt
PCA Module 0
Priority
(CCF0) 1 1 1
Decoder
ECCF1
PCA Module 1 0
(CCF1) 1
ECCF2
PCA Module 2 0
(CCF2) 1
ECCF3
PCA Module 3 0
(CCF3) 1
ECCF4
PCA Module 4 0
(CCF4) 1
ECCF5
PCA Module 5 0
(CCF5) 1
Table 27.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode PCA0CPMn PCA0PWM
Bit Number 7 6 5 4 3 2 1 0 7 6 5 4-2 1–0
Capture triggered by positive edge on CEXn X X 1 0 0 0 0 A 0 X B XXX XX
Capture triggered by negative edge on CEXn X X 0 1 0 0 0 A 0 X B XXX XX
Capture triggered by any transition on CEXn X X 1 1 0 0 0 A 0 X B XXX XX
Software Timer X C 0 0 1 0 0 A 0 X B XXX XX
Table 27.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Modules
Operational Mode PCA0CPMn PCA0PWM
High Speed Output X C 0 0 1 1 0 A 0 X B XXX XX
Frequency Output X C 0 0 0 1 1 A 0 X B XXX XX
8-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A 0 X B XXX 00
9-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 01
10-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 10
11-Bit Pulse Width Modulator (Note 7) 0 C 0 0 E 0 1 A D X B XXX 11
16-Bit Pulse Width Modulator 1 C 0 0 E 0 1 A 0 X B XXX XX
Notes:
1. X = Don’t Care (no functional difference for individual module if 1 or 0).
2. A = Enable interrupts for this module (PCA interrupt triggered on CCFn set to 1).
3. B = Enable 8th, 9th, 10th or 11th bit overflow interrupt (Depends on setting of CLSEL[1:0]).
4. C = When set to 0, the digital comparator is off. For high speed and frequency output modes, the
associated pin will not toggle. In any of the PWM modes, this generates a 0% duty cycle (output = 0).
5. D = Selects whether the Capture/Compare register (0) or the Auto-Reload register (1) for the associated
channel is accessed via addresses PCA0CPHn and PCA0CPLn.
6. E = When set, a match event will cause the CCFn flag for the associated channel to be set.
7. All modules set to 8, 9, 10 or 11-bit PWM mode use the same cycle length setting.
PCA Interrupt
PCA0CPMn
P ECCMT P E PCA0CN
WC A A AOWC CC CCC
MOPP TGMC FR CCC
1 MP N n n n F FFF
6 n n n n 2 1 0
n
x x 0 0 0 x
(to CCFn)
PCA0CPLn PCA0CPHn
0
1
CEXn Capture
Port I/O Crossbar
0
1
PCA
Timebase
PCA0L PCA0H
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
27.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare
register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn regis-
ter enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Write to
PCA0CPLn 0
ENB
Reset
Write to
PCA0CPHn ENB PCA Interrupt
1
PCA0CPMn
P ECCMT P E PCA0CN
WC A A AOWC CC CCC
MOPP TGMC PCA0CPLn PCA0CPHn FR CCC
1 MP N n n n F FFF
6 n n n n 2 1 0
n
x 0 0 0 0 x
0
Enable Match
16-bit Comparator
1
PCA
Timebase
PCA0L PCA0H
Write to
PCA0CPLn 0
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn ENB P ECCMT P E
1 WC A A AOWC
MOPP TGMC
1 MPN n n n F
6 n n n n
n
x 0 0 0 x
PCA Interrupt
PCA0CN
CC CCC
PCA0CPLn PCA0CPHn FR CCC
FFF
2 1 0
0
Enable Match
16-bit Comparator
1
TOGn
Toggle
0 CEXn
Crossbar Port I/O
1
PCA
Timebase
PCA0L PCA0H
F PCA
F CEXn = -----------------------------------------
2 PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Write to
PCA0CPLn 0
ENB
Reset
PCA0CPMn
Write to P ECCMT P E
PCA0CPHn ENB WC A A AOWC
PCA0CPLn 8-bit Adder PCA0CPHn
1 MOPP TGMC
1 MP N n n n F
Adder
6 n n n n Enable
n TOGn
x 0 0 0 x Toggle
0 CEXn
Enable 8-bit match Crossbar Port I/O
Comparator 1
PCA Timebase
PCA0L
27.3.5. 8-Bit, 9-Bit, 10-Bit and 11-Bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer, and
the setting of the PWM cycle length (8, 9, 10 or 11-bits). For backwards-compatibility with the 8-bit PWM
mode available on other devices, the 8-bit PWM mode operates slightly different than 9, 10 and 11-bit
PWM modes. It is important to note that all channels configured for 8/9/10/11-bit PWM mode will use
the same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11-
bit mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Out-
put, Software Timer, Frequency Output, or 16-bit PWM mode independently.
27.3.5.1. 8-Bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn cap-
ture/compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 27.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare
high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register, and setting the CLSEL bits in register PCA0PWM to 00b enables 8-Bit Pulse Width
Modulator mode. If the MATn bit is set to 1, the CCFn flag for the module will be set each time an 8-bit
comparator match (rising edge) occurs. The COVF flag in PCA0PWM can be used to detect the overflow
(falling edge), which will occur every 256 PCA clock cycles. The duty cycle for 8-Bit PWM Mode is given in
Equation 27.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 – PCA0CPHn
Duty Cycle = ---------------------------------------------------
256
Equation 27.2. 8-Bit PWM Duty Cycle
Using Equation 27.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn 0
ENB
Reset
PCA0CPHn
Write to
PCA0CPHn ENB
1 COVF
PCA0PWM PCA0CPMn
A EC C C P ECCMT P E
R CO L L WC A A AOWC
PCA0CPLn
S OV S S MOPP TGMC
E VF E E 1 MP N n n n F
L L L 6 n n n n
1 0 n
0 x 0 0 0 0 0 x 0 x
R CLR Q
PCA Timebase
PCA0L
Overflow
2 N – PCA0CPn -
Duty Cycle = -------------------------------------------
2N
Equation 27.3. 9, 10, and 11-Bit PWM Duty Cycle
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn 0 R/W when
ENB (Auto-Reload)
Reset ARSEL = 1 PCA0PWM
PCA0CPH:Ln
A EC C C
(right-justified)
Write to R CO L L
PCA0CPHn ENB
S OV S S
1 E VF E E
L L L
PCA0CPMn 1 0
P ECCMT P E R/W when x
(Capture/Compare)
WC A A AOWC ARSEL = 0 Set “N” bits:
MOPP TGMC PCA0CPH:Ln 01 = 9 bits
(right-justified) 10 = 10 bits
1 MP N n n n F
6 n n n n 11 = 11 bits
n
0 0 0 x 0 x
R CLR Q
PCA Timebase
PCA0H:L
Overflow of Nth Bit
65536 – PCA0CPn
Duty Cycle = -----------------------------------------------------
65536
Equation 27.4. 16-Bit PWM Duty Cycle
Using Equation 27.4, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn 0
ENB
Reset
Write to
PCA0CPHn ENB
1
PCA0CPMn
P EC C MT P E
WCA A AOW C
PCA0CPHn PCA0CPLn
MOP P TGM C
1 MP N n n n F
6 n n n n
n
1 0 0 x 0 x
R CLR
Q
PCA Timebase
PCA0H PCA0L
Overflow
PC A0M D
C W W C C C E
I D D P P P C PC A0C PH 5
D T L S S S F
L E C 2 1 0
K
8-bit M atch
R eset
Enable C om parator
PCA0L O verflow
PCA0CPL5 8-bit Adder PC A 0H
Adder
W rite to Enable
PCA 0C PH 2
Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 27.5, where PCA0L is the value of the PCA0L register
at the time of the update.
Bit 7 6 5 4 3 2 1 0
Name CF CR CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name CIDL WDTE WDLCK CPS2 CPS1 CPS0 ECF
Reset 0 1 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name ARSEL ECOV COVF CLSEL[1:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Reset 0 0 0 0 0 0 0 0
SFR Address, Page: PCA0CPM0 = 0xDA, 0x0; PCA0CPM1 = 0xDB, 0x0; PCA0CPM2 = 0xDC, 0x0
PCA0CPM3 = 0xDD, 0x0; PCA0CPM4 = 0xDE, 0x0; PCA0CPM5 = 0xCE, 0x0
Bit Name Function
7 PWM16n 16-bit Pulse Width Modulation Enable.
This bit enables 16-bit mode when Pulse Width Modulation mode is enabled.
0: 8 to 11-bit PWM selected.
1: 16-bit PWM selected.
6 ECOMn Comparator Function Enable.
This bit enables the comparator function for PCA module n when set to 1.
5 CAPPn Capture Positive Function Enable.
This bit enables the positive edge capture for PCA module n when set to 1.
4 CAPNn Capture Negative Function Enable.
This bit enables the negative edge capture for PCA module n when set to 1.
3 MATn Match Function Enable.
This bit enables the match function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the CCFn
bit in PCA0MD register to be set to logic 1.
2 TOGn Toggle Function Enable.
This bit enables the toggle function for PCA module n when set to 1. When enabled,
matches of the PCA counter with a module's capture/compare register cause the logic
level on the CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module oper-
ates in Frequency Output Mode.
1 PWMn Pulse Width Modulation Mode Enable.
This bit enables the PWM function for PCA module n when set to 1. When enabled, a
pulse width modulated signal is output on the CEXn pin. 8 to 11-bit PWM is used if
PWM16n is cleared; 16-bit mode is used if PWM16n is set to logic 1. If the TOGn bit is
also set, the module operates in Frequency Output Mode.
0 ECCFn Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
Note: When the WDTE bit is set to 1, the PCA0CPM5 register cannot be modified, and module 5 acts as the
watchdog timer. To change the contents of the PCA0CPM5 register or the function of module 5, the Watchdog
Timer must be disabled.
Bit 7 6 5 4 3 2 1 0
Name PCA0[7:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name PCA0[15:8]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name PCA0CPn[7:0]
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name PCA0CPn[15:8]
Reset 0 0 0 0 0 0 0 0
28. C2 Interface
Si1000/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash pro-
gramming and in-system debugging with the production part installed in the end application. The C2 inter-
face uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between
the device and a host system. See the C2 Interface Specification for details on the C2 protocol.
28.1. C2 Interface Registers
The following describes the C2 registers necessary to perform Flash programming through the C2 inter-
face. All C2 registers are accessed through the C2 interface as described in the C2 Interface Specification.
Bit 7 6 5 4 3 2 1 0
Name C2ADD[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name DEVICEID[7:0]
Type R/W
Reset 0 0 0 1 0 1 0 0
C2 Address: 0x00
Bit Name Function
7:0 DEVICEID[7:0] Device ID.
This read-only register returns the 8-bit device ID: 0x16 (Si1000/1/2/3/4/5).
Bit 7 6 5 4 3 2 1 0
Name REVID[7:0]
Type R/W
C2 Address: 0x01
Bit Name Function
7:0 REVID[7:0] Revision ID.
This read-only register returns the 8-bit revision ID. For example: 0x00 = Revision A.
Bit 7 6 5 4 3 2 1 0
Name FPCTL[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
C2 Address: 0x02
Bit Name Function
7:0 FPCTL[7:0] Flash Programming Control Register.
This register is used to enable Flash programming via the C2 interface. To enable C2
Flash programming, the following codes must be written in order: 0x02, 0x01. Note
that once C2 Flash programming is enabled, a system reset must be issued to
resume normal operation.
Bit 7 6 5 4 3 2 1 0
Name FPDAT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
C2 Address: 0xB4
Bit Name Function
7:0 FPDAT[7:0] C2 Flash Programming Data Register.
This register is used to pass Flash commands, addresses, and data during C2 Flash
accesses. Valid commands are listed below.
Code Command
0x06 Flash Block Read
0x07 Flash Block Write
0x08 Flash Page Erase
0x03 Device Erase
C8051Fxxx
Output (c)
C2 Interface Master
CONTACT INFORMATION
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