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• Gate lengths
Gate approaching one
micron
• Consists of many
n n n n small enhancement-
p p mode parallel-
connected MOSFET
cells, covering the
n- surface of the silicon
wafer
n • Vertical current flow
• n-channel device is
shown
Drain
source –
• p-n- junction is
reverse-biased
• off-state voltage
n n n n appears across n-
p p region
depletion region
n-
drain +
00V
0V
• On state: VGS >> Vth
=1
=2
10A
V
DS
=2
DS
V
• MOSFET can
V
V DS
ID conduct peak
currents well in
on state
excess of average
5A
1V
current rating
V DS = —characteristics are
unchanged
off V DS = 0.5V
state • on-resistance has
positive temperature
0A coefficient, hence
0V 5V 10V 15V
easy to parallel
VGS
D
• Cgs : large, essentially constant
• Cgd : small, highly nonlinear
Cgd
• Cds : intermediate in value, highly
G nonlinear
Cds
• switching times determined by rate
Cgs at which gate driver
charges/discharges Cgs and Cgd
C0 V0 C '0
Cds(vds) = Cds(vds) ≈ C0 vds = vds
v
1 + ds
V0
Vg + Cj
–
+
–
V0 C '0
Cds(vds) ≈ C0 vds = vds
4
— same energy loss as linear capacitor having value 3 Cds(VDS)