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    NM-A841 (CG521) Rev 1.0 PDF

    Uploaded by

    Starbyte Printer Saul Cipriano

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 50

    A B C D E

    1 1

    LCFC Confidential
    NANO G ACL CG521 M/B Schematics Document

    a
    hu
    2 2

    AMD FP4 Carrizo L SOC with DDRIIIL

    g.
    AMD R16M-M1-30

    an
    2016-02-24

    Hu
    3
    REV:1.0 3
    r
    Fo

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Cover Page
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Tuesday, March 08, 2016 Sheet 1 of 50
    A B C D E
    A B C D E

    LCFC confidential
    File Name : CG521
    AMD R16M-M1-30
    S3 Package: 23mmX23mm PCI-Express
    Page 18~24 4x Gen2 Memory BUS (DDR3L)
    Single Channel B DDR3L-SO-DIMM X1
    Page 12
    VRAM 256*16 PEG 0~3
    1
    1.35V DDR3L 1600 MT/s 1

    DDR3L*4 2GB 1333MT/s UP TO 8G


    Page 14~22

    USB Left
    HDMI Conn. HDMI x4 Lane Port1 USB 3.0 1x
    Page 25 AMD FP4 APU USB 2.0 Port0

    USB 2.0 2x
    eDP x2 Lane
    Carrizo L 15W JUSB1
    USB 2.0 Port7
    Int. Camera Page 32
    USB 3.0 Port3
    USB2.0 Port5
    USB2.0 1x JUSB2

    eDP Conn (Integrated FCH)

    a
    Page 23

    hu
    2 2

    g.
    SATA HDD SATA Gen3 USB2.0 1x
    Page 33 SATA Port0 Cardreader Realtek SD/MMC Conn.
    BGA-968 RTS5170 USB2.0 Port2

    an
    37mm*29mm USB Board
    SATA ODD SATA Gen1
    Page 33 SATA Port1

    USB 2.0 1x NGFF Card

    Hu
    WLAN&BT
    LAN Realtek PCIe 1x Key E
    RJ45 Conn. PCIe 1x PCIe Port1
    Page 29
    RTL8106E Page 31 USB2.0 Port4

    3 3
    Page 28 PCIe Port2
    SPI BUS SPI ROM
    HD Audio
    Page 4~11 8MB Page 08
    r
    TPM
    Fo
    Codec SPK Conn. reserve Page 30
    Realtek ALC3248 Page 34
    Page 34

    EC Thermistor
    ITE IT8586E-LQFP Page 30
    Page 35

    Int. MIC HP&Mic Combo Conn.


    Page 34 Page 34 Sub-board ( for 15")

    Touch Pad Int.KBD Thermal Sensor ODD Board


    4 Page 36 Page 36 NCT7718W 4
    Page 30 reserve

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Block Diagram
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Tuesday, March 08, 2016 Sheet 2 of 50
    A B C D E
    A B C D E

    Voltage Rails ( O --> Means ON , X --> Means OFF )


    SIGNAL BOARD
    +5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock Config. BOARD_ID0 BOARD_ID1 BOARD_ID2 Function
    +3VS 0: 14'' 0: Dis
    S0 (Full ON) HIGH HIGH ON ON ON ON
    +1.8VS 1: 15'' 1: UMA
    power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
    plane B+ +5VALW
    (+20VSB) +1.35V +0.95VS
    1 (+VSYSMEM_APU) S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF 1
    +3VALW +0.675VS
    +3VL (+3VALW_APU)
    +APU_CORE S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF
    +5VLP +APU_CORE_NB
    +1.8VALW S5 (Soft OFF) LOW LOW ON OFF OFF OFF
    +APU_GFX
    +0.95VALW +VGA_CORE
    State
    +3VGS USB Port Table for CarrizoL
    +0.775VALW
    +1.8VGS
    +1.35VGS
    USB 2.0 USB 3.0 Port Port device
    +0.95VGS 0 RIGHT USB (2.0) BOM Structure Table
    1 N/A BOM Structure BTO Item
    EHCI0
    2 Card Reader @ Not stuff
    S0 O O O O 3 Touch screen ME@ Connector
    Blue Tooth

    a
    4 14@ For 14" part
    EHCI1
    S3
    O O O X 5 Camera 15@ For 15" part
    0 6 LEFT USB (3.0) EMC@ EMC Part

    hu
    xHCI
    S5 S4/AC
    1 7 LEFT USB (3.0) EMC_NS@ EMC reserve Part
    2 O O X X EMC_PX@ EMC GPU part 2

    USB Port Table for Carrizo EMC_CZ@ EMC Carrizo APU part
    S5 S4/ Battery only EMC_15@ EMC 15 part
    O X X X

    g.
    USB 2.0 USB 3.0 Port Port device RF reserve Part
    RF_NS@
    S5 S4/AC & Battery
    0 RIGHT USB (2.0) RF_PXNS@ RF GPU reserve part
    don't exist X X X X 1 N/A UMA@ UMA SKU ID part
    EHCI0
    2 Card Reader PX@ Discrete GPU SKU part

    an
    3 Touch screen EXO@ EXO GPU Part

    SMBUS Control Table 4 Blue Tooth TOPAZ@ TOPAZ GPU Part


    5 Camera TPM@ TPM part

    SOURCE GPU BATT IT8586E SODIMM WLAN Thermal APU Charger HDMI
    xHCI 2 6 LEFT USB (3.0) AOAC@ AOAC support part
    3 7 LEFT USB (3.0) HDT@ HDT Debug part

    Hu
    Sensor Convert
    reserve TS@ Touch screen part
    EC_SMB_CK1 CZ@ Carrizo Part
    IT8586E
    EC_SMB_DA1 X V X X X X V X CZL@ CarrizoL part
    +3VALW
    CZPX@ Carrizo Discrete Part
    3
    EC_SMB_CK2 V CZLPX@ CarrizoL Discrete Part 3

    IT8586E V X X X V APU_SIC
    APU_SID X V
    EC_SMB_DA2
    +3VS +3VS_VGA 1.8VS for CZ PCIE PORT LIST S4GX4@ X76 SAMSUNG 2G
    r
    3VS for CZL
    M4GX4@ X76 MICRON 2G
    APU_SCLK0 APU H4GX4@ X76 HYNIX 2G
    Port Device
    APU_SDATA0 X X X V V X X X
    Fo
    +3VS S2GX4@ X76 SAMSUNG 1G
    0 N/A
    M2GX4@ X76 MICRON 1G
    GPP
    1 WLAN
    H2GX4@ X76 HYNIX 1G
    2 LAN
    S2G@ SAMSUNG 2G
    3 N/A MICRON 2G
    M2G@
    EC SM Bus1 address EC SM Bus2 address 0 H2G@ HYNIX 2G
    1 VRAM
    GFX CZL S1G@ SAMSUNG 1G
    Device Address Device Address 2 GPU M1G@ MICRON 1G
    Battery 0X16 Thermal Sensor 1001_100xb(reserve) 3 CZ
    H1G@ HYNIX 1G
    Charger 0001 0010 b GPU 0x41(default)
    4 GPU
    CZLUMA@ CarrizoL UMA Part
    releate to F3x1E4[SbiAddr] or Address Select Pins setting
    APU SB-TSI 5
    N/A CZUMA@ Carrizo UMA Part
    HDMI Convert RSVD 6
    4
    APU SM Bus address 7
    SIVCD@ SIV COST down material
    4

    HDMI@ HDMI Logo


    Device Address
    DDR DIMMA 0xA0h
    DDR DIMMB 0xA2h
    Security Classification LC Future Center Secret Data Title
    WLAN RSVD
    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 3 of 50
    A B C D E
    5 4 3 2 1

    D D

    UC2B
    PCIE

    U10 R1
    U9 P_GPP_RXP0 P_GPP_TXP0 R2
    P_GPP_RXN0 P_GPP_TXN0
    PCIE_PRX_DTX_P1 T6 R4 PCIE_PTX_DRX_P1 CC1 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
    {31} PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 {31}
    T5 R3 CC2 1 2 0.1U_0201_6.3V6-K
    WLAN {31} PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 {31} WLAN

    a
    PCIE_PRX_DTX_P2 T9 N1 PCIE_PTX_DRX_P2 CC3 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P2
    {28} PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_PTX_DRX_N2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 {28}
    T8 N2 CC4 1 2 0.1U_0201_6.3V6-K
    LAN {28} PCIE_PRX_DTX_N2 P_GPP_RXN2 P_GPP_TXN2 PCIE_PTX_C_DRX_N2 {28} LAN
    P7 N4
    P_GPP_RXP3 P_GPP_TXP3

    hu
    +0.95VS P6 N3 +0.95VS
    P_GPP_RXN3 P_GPP_TXN3
    C RC1 1 CZL@ 2 1.69K_0402_1% P_TX_ZVDD U7 U6 P_RX_ZVDD 1K_0402_1% 1 2 CZL@ RC2 C
    P_ZVDDP P_ZVSS/P_RX_ZVDDP
    with BOM strcture control, RC1 change to 196_0402_1% for Stoney and Carrizo 196_0402_1% 1 2 STN@ RC3

    PCIE_CRX_GTX_P0 P10 M2 PCIE_CTX_GRX_P0 CC5 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P0


    {15} PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 {15}
    P9 M1 CC6 CZLPX@1 2 0.1U_0201_6.3V6-K
    {15} PCIE_CRX_GTX_N0 PCIE_CTX_C_GRX_N0 {15}

    g.
    P_GFX_RXN0 P_GFX_TXN0
    PCIE_CRX_GTX_P1 N6 L1 PCIE_CTX_GRX_P1 CC7 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
    {15} PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 {15}
    N5 L2 CC8 CZLPX@1 2 0.1U_0201_6.3V6-K
    GPU {15} PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1 PCIE_CTX_C_GRX_N1 {15} GPU
    PCIE_CRX_GTX_P2 N9 L4 PCIE_CTX_GRX_P2 CC9 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
    {15} PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 {15}
    N8 L3 CC10 CZLPX@1 2 0.1U_0201_6.3V6-K
    {15} PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 {15}
    PCIE_CRX_GTX_P3 L7 J1 PCIE_CTX_GRX_P3 CC11 CZLPX@1 2 0.1U_0201_6.3V6-K PCIE_CTX_C_GRX_P3

    an
    {15} PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 P_GFX_RXP3 P_GFX_TXP3 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 {15}
    L6 J2 CC12 CZLPX@1 2 0.1U_0201_6.3V6-K
    {15} PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 {15}
    L10 J4
    L9 P_GFX_RXP4 P_GFX_TXP4 J3
    P_GFX_RXN4 P_GFX_TXN4
    with BOM strcture control, CC5--CC12 change to 0.22uf for STN
    K6 H2
    K5 P_GFX_RXP5 P_GFX_TXP5 H1
    P_GFX_RXN5 P_GFX_TXN5

    Hu
    K9 G1
    CarrizoL not support GFX4-GFX7 K8 P_GFX_RXP6 P_GFX_TXP6 G2
    P_GFX_RXN6 P_GFX_TXN6
    J7 G4
    J6 P_GFX_RXP7 P_GFX_TXP7 G3
    P_GFX_RXN7 P_GFX_TXN7

    B B
    FP4 REV 0.93
    @ AMD-CARRIZO_FP4-BGA968
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (PCIE I/F)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 4 of 50
    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQS[0..7]
    {12} DDRB_DQS[0..7]
    DDRB_DQS#[0..7]
    CarrizoL not support ChannelA {12} DDRB_DQS#[0..7]

    UC2A UC2I
    MEMORY A MEMORY B
    {12} DDRB_MA[15..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] {12}
    AE28 H17 AG31 A25
    Y27 MA_ADD0 MA_DATA0 J17 DDRB_MA1 AC30 MB_ADD0 MB_DATA0 C25 DDRB_DQ1
    Y29 MA_ADD1 MA_DATA1 F20 DDRB_MA2 AC31 MB_ADD1 MB_DATA1 C27 DDRB_DQ2
    Y26 MA_ADD2 MA_DATA2 H20 DDRB_MA3 AB32 MB_ADD2 MB_DATA2 D27 DDRB_DQ3
    W28 MA_ADD3 MA_DATA3 E17 DDRB_MA4 AA32 MB_ADD3 MB_DATA3 B24 DDRB_DQ4
    D D
    W29 MA_ADD4 MA_DATA4 F17 DDRB_MA5 AA33 MB_ADD4 MB_DATA4 B25 DDRB_DQ5
    W26 MA_ADD5 MA_DATA5 K18 DDRB_MA6 AA31 MB_ADD5 MB_DATA5 B27 DDRB_DQ6
    U29 MA_ADD6 MA_DATA6 E20 DDRB_MA7 Y33 MB_ADD6 MB_DATA6 A27 DDRB_DQ7
    W25 MA_ADD7 MA_DATA7 DDRB_MA8 AA30 MB_ADD7 MB_DATA7
    U26 MA_ADD8 A21 DDRB_MA9 W32 MB_ADD8 A29 DDRB_DQ8
    AG29 MA_ADD9 MA_DATA8 C21 DDRB_MA10 AG32 MB_ADD9 MB_DATA8 C29 DDRB_DQ9
    U27 MA_ADD10 MA_DATA9 C23 DDRB_MA11 Y32 MB_ADD10 MB_DATA9 B32 DDRB_DQ10
    T28 MA_ADD11 MA_DATA10 D23 DDRB_MA12 W33 MB_ADD11 MB_DATA10 D32 DDRB_DQ11
    AK26 MA_ADD12 MA_DATA11 B20 DDRB_MA13 AL31 MB_ADD12 MB_DATA11 B28 DDRB_DQ12
    T26 MA_ADD13 MA_DATA12 B21 DDRB_MA14 W30 MB_ADD13 MB_DATA12 B29 DDRB_DQ13
    T25 MA_ADD14/MA_BG1 MA_DATA13 B23 DDRB_MA15 V32 MB_ADD14/MB_BG1 MB_DATA13 A31 DDRB_DQ14
    MA_ADD15/MA_ACT_L MA_DATA14 A23 MB_ADD15/MB_ACT_L MB_DATA14 C31 DDRB_DQ15
    MA_DATA15 MB_DATA15
    G22 E30 DDRB_DQ16
    AG26 MA_DATA16 H22 DDRB_BS0# AH32 MB_DATA16 E31 DDRB_DQ17
    MA_BANK0 MA_DATA17 {12} DDRB_BS0# DDRB_BS1# MB_BANK0 MB_DATA17 DDRB_DQ22
    AG27 E25 AG33 G33
    MA_BANK1 MA_DATA18 {12} DDRB_BS1# DDRB_BS2# MB_BANK1 MB_DATA18 DDRB_DQ23
    T29 G25 W31 G32
    MA_BANK2/MA_BG0 MA_DATA19 J20
    {12} DDRB_BS2# MB_BANK2/MB_BG0 MB_DATA19 C33 DDRB_DQ20 DATA16--DATA23 Byte internal swap
    MA_DATA20 {12} DDRB_DM[7..0] DDRB_DM0 MB_DATA20 DDRB_DQ21
    E19 E22 D25 D33
    D21 MA_DM0 MA_DATA21 H23 DDRB_DM1 D29 MB_DM0 MB_DATA21 G30 DDRB_DQ19
    K21 MA_DM1 MA_DATA22 J23 DDRB_DM2 E33 MB_DM1 MB_DATA22 G31 DDRB_DQ18
    F29 MA_DM2 MA_DATA23 DDRB_DM3 J33 MB_DM2 MB_DATA23
    AP28 MA_DM3 F26 DDRB_DM4 AR30 MB_DM3 J30 DDRB_DQ24
    AV26 MA_DM4 MA_DATA24 E27 DDRB_DM5 AW30 MB_DM4 MB_DATA24 J31 DDRB_DQ25
    AR22 MA_DM5 MA_DATA25 J26 DDRB_DM6 BC30 MB_DM5 MB_DATA25 L33 DDRB_DQ26
    MA_DM6 MA_DATA26 MB_DM6 MB_DATA26

    a
    BC22 J27 DDRB_DM7 BC26 L32 DDRB_DQ27
    K29 MA_DM7 MA_DATA27 H25 @ TC20 1 DDRB_DM8 N33 MB_DM7 MB_DATA27 H32 DDRB_DQ29
    MA_DM8 MA_DATA28 E26 MB_DM8 MB_DATA28 H33 DDRB_DQ28 DATA24--DATA31 Byte internal swap
    H19 MA_DATA29 G28 DDRB_DQS0 B26 MB_DATA29 L30 DDRB_DQ30
    G19 MA_DQS_H0 MA_DATA30 G29 DDRB_DQS#0 A26 MB_DQS_H0 MB_DATA30 L31 DDRB_DQ31

    hu
    B22 MA_DQS_L0 MA_DATA31 DDRB_DQS1 B30 MB_DQS_L0 MB_DATA31
    A22 MA_DQS_H1 AN26 DDRB_DQS#1 A30 MB_DQS_H1 AN31 DDRB_DQ36
    F23 MA_DQS_L1 MA_DATA32 AP29 DDRB_DQS2 F32 MB_DQS_L1 MB_DATA32 AP32 DDRB_DQ32
    E23 MA_DQS_H2 MA_DATA33 AR26 DDRB_DQS#2 E32 MB_DQS_H2 MB_DATA33 AT32 DDRB_DQ39
    C
    G27 MA_DQS_L2 MA_DATA34 AP24 DDRB_DQS3 K32 MB_DQS_L2 MB_DATA34 AU32 DDRB_DQ35 C
    F27 MA_DQS_H3 MA_DATA35 AN29 DDRB_DQS#3 J32 MB_DQS_H3 MB_DATA35 AN33 DDRB_DQ33 DATA32--DATA39 Byte internal swap
    AP25 MA_DQS_L3 MA_DATA36 AN27 DDRB_DQS4 AR32 MB_DQS_L3 MB_DATA36 AN32 DDRB_DQ37
    AP26 MA_DQS_H4 MA_DATA37 AR29 DDRB_DQS#4 AR33 MB_DQS_H4 MB_DATA37 AR31 DDRB_DQ34
    AW27 MA_DQS_L4 MA_DATA38 AR27 DDRB_DQS5 AW32 MB_DQS_L4 MB_DATA38 AT33 DDRB_DQ38
    MA_DQS_H5 MA_DATA39 MB_DQS_H5 MB_DATA39

    g.
    AV27 DDRB_DQS#5 AW33
    AV22 MA_DQS_L5 AU26 DDRB_DQS6 BA29 MB_DQS_L5 AU30 DDRB_DQ41
    AU22 MA_DQS_H6 MA_DATA40 AV29 DDRB_DQS#6 AY29 MB_DQS_H6 MB_DATA40 AV32 DDRB_DQ44
    BA21 MA_DQS_L6 MA_DATA41 AU25 DDRB_DQS7 BA25 MB_DQS_L6 MB_DATA41 BA33 DDRB_DQ43
    AY21 MA_DQS_H7 MA_DATA42 AW25 DDRB_DQS#7 AY25 MB_DQS_H7 MB_DATA42 AY32 DDRB_DQ47
    L27 MA_DQS_L7 MA_DATA43 AU29 @ TC8 1 DDRB_DQS8 P32 MB_DQS_L7 MB_DATA43 AU33 DDRB_DQ45 DATA40--DATA47 Byte internal swap
    L26 MA_DQS_H8 MA_DATA44 AU28 @ TC9 1 DDRB_DQS#8 N32 MB_DQS_H8 MB_DATA44 AU31 DDRB_DQ40
    MA_DQS_L8 MA_DATA45 AW26 MB_DQS_L8 MB_DATA45 AW31 DDRB_DQ46
    AE25 MA_DATA46 AT25 DDRB_CLK0 AE33 MB_DATA46 AY33 DDRB_DQ42
    MA_CLK_H0 MA_DATA47 {12} DDRB_CLK0 MB_CLK_H0 MB_DATA47

    an
    AE26 DDRB_CLK0# AE32
    MA_CLK_L0 {12} DDRB_CLK0# DDRB_CLK1 MB_CLK_L0 DDRB_DQ54
    AD26 AV23 AE30 BC31
    MA_CLK_H1 MA_DATA48 {12} DDRB_CLK1 DDRB_CLK1# MB_CLK_H1 MB_DATA48 DDRB_DQ53
    AD27 AW23 AE31 BB30
    MA_CLK_L1 MA_DATA49 {12} DDRB_CLK1# MB_CLK_L1 MB_DATA49 DDRB_DQ50
    AB28 AV20 AD32 BB28
    AB29 MA_CLK_H2 MA_DATA50 AW20 AD33 MB_CLK_H2 MB_DATA50 AY27 DDRB_DQ52
    AB25 MA_CLK_L2 MA_DATA51 AR23 AC33 MB_CLK_L2 MB_DATA51 BB32 DDRB_DQ49 DATA48--DATA55 Byte internal swap
    AB26 MA_CLK_H3 MA_DATA52 AT23 AC32 MB_CLK_H3 MB_DATA52 BA31 DDRB_DQ48
    MA_CLK_L3 MA_DATA53 AR20 MB_CLK_L3 MB_DATA53 BC29 DDRB_DQ51
    N29 MA_DATA54 AT20 RC240 1 2 10_0402_5% MEM_MB_RST#_R T33 MB_DATA54 BB29 DDRB_DQ55
    MA_RESET_L MA_DATA55 {12} MEM_MB_RST# MEM_MB_EVENT#AG30 MB_RESET_L MB_DATA55
    AE29

    Hu
    MA_EVENT_L {12} MEM_MB_EVENT# MB_EVENT_L DDRB_DQ60
    BB23 BB27
    P27 MA_DATA56 BB22 DDRB_CKE0 U32 MB_DATA56 BB26 DDRB_DQ57
    MA_CKE0 MA_DATA57 {12} DDRB_CKE0 DDRB_CKE1 MB_CKE0 MB_DATA57 DDRB_DQ58
    P29 BB20 U33 BB24
    MA_CKE1 MA_DATA58 AY19
    {12} DDRB_CKE1 MB_CKE1 MB_DATA58 AY23 DDRB_DQ59 DATA56--DATA63 Byte internal swap
    MA_DATA59 BA23 MB_DATA59 BA27 DDRB_DQ61
    MA_DATA60 BC23 MB_DATA60 BC27 DDRB_DQ56
    AK27 MA_DATA61 BC21 DDRB_ODT0 AL30 MB_DATA61 BC25 DDRB_DQ63
    MA0_ODT0 MA_DATA62 {12} DDRB_ODT0 DDRB_ODT1 MB0_ODT0 MB_DATA62 DDRB_DQ62
    AL26 BB21 AM32 BB25
    MA0_ODT1 MA_DATA63 {12} DDRB_ODT1 MB0_ODT1 MB_DATA63
    AH25 AJ32
    AL25 MA1_ODT0 K26 AM33 MB1_ODT0 N30
    MA1_ODT1 MA_CHECK0 K28 MB1_ODT1 MB_CHECK0 N31
    B B
    AH26 MA_CHECK1 N26 DDRB_CS0# AJ33 MB_CHECK1 R33
    MA0_CS_L0 MA_CHECK2 {12} DDRB_CS0# DDRB_CS1# MB0_CS_L0 MB_CHECK2
    AL29 N28 AL32 R32
    MA0_CS_L1 MA_CHECK3 {12} DDRB_CS1# MB0_CS_L1 MB_CHECK3
    r
    AH29 J29 AJ30 M32
    AL28 MA1_CS_L0 MA_CHECK4 K25 AL33 MB1_CS_L0 MB_CHECK4 M33
    MA1_CS_L1 MA_CHECK5 L29 MB1_CS_L1 MB_CHECK5 R30
    MA_CHECK6 N25 MB_CHECK6 R31
    AG24 MA_CHECK7 DDRB_RAS# AH33 MB_CHECK7
    {12} DDRB_RAS#
    Fo
    AK29 MA_RAS_L/MA_RAS_L_ADD16 DDRB_CAS# AK32 MB_RAS_L/MB_RAS_L_ADD16 +1.35V
    MA_CAS_L/MA_CAS_L_ADD15 {12} DDRB_CAS# DDRB_WE# MB_CAS_L/MB_CAS_L_ADD15
    AH28 AJ31
    MA_WE_L/MA_WE_L_ADD14 {12} DDRB_WE# MB_WE_L/MB_WE_L_ADD14

    B19 AD29 APU_M_VREFDQ A19 AF32 MB_ZVDDIO RC10 1 2 39.2_0402_1%


    +MEM_VREF MA_VREFDQ MA_ZVDDIO_MEM_S {12} APU_M_VREFDQ MB_VREFDQ MB_ZVDDIO_MEM_S
    T32
    M_VREF
    FP4 REV 0.93 FP4 REV 0.93

    @ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968

    +1.35V

    +1.35V
    1

    RC4
    1K_0402_1% RC9 1 2 1K_0402_5% MEM_MB_EVENT#
    2

    +MEM_VREF

    @
    .47U_0402_6.3V6K
    1

    CC14 0.1U_0201_6.3V6-K

    1 1 1
    RC5 CC15
    A A
    1K_0402_1% 1000P_0201_50V7-K
    2 2 2
    2

    CC13

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (MEM)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 5 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VS_APU
    UC2C For Carrizo RPC18
    APU_DDC_CLK 1 4
    DisplayPort Auxiliary Channel pins are dual-mode pins and are 3.3V tolerant. APU_DDC_DATA 2 3
    DISPLAY/SVI2/JTAG/TEST In I2C mode AUXP pins change to SCL, and AUXN pins change to SDA.
    During this operation the pin type is B-IO33-OD. FDS 2.2K_0404_4P2R_5%
    B6 A9 DP_2K_ZVSS RC55 1 2 2K_0402_1%
    A6 DP2_TXP0 DP_ZVSS B9 DP_150_ZVSS RC12 1 2 150_0402_1%
    +1.8VS DP2_TXN0 DP_AUX_ZVSS G5 DP_ENBKL APU_EDP_HPD RC35 1 2 100K_0402_5%
    D7 DP_BLON G6 DP_ENVDD
    DP2_TXP1 DP_DIGON For STN,
    C7 F11 DP_EDP_PWM
    DP2_TXN1 DP_VARY_BL Hot Plug Detect pins is I-IO18-S,but 3.3V tolerant.
    1

    RC18
    CarrizoL not support DP2 A7 +1.8VS
    DP2_TXP2 RPC11
    300_0402_5% B7 H9 STN@
    D DP2_TXN2 DP2_AUXP D
    G9 APU_PROCHOT#_R 3 2
    D9 DP2_AUXN E9 ALERT# 4 1
    2

    APU_RST# C9 DP2_TXP3 DP2_HPD


    DP2_TXN3 F7 APU_DDC_CLK 1K_0404_4P2R_5%
    PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf APU_HDMI_TX2+ A2 DP1_AUXP E7 APU_DDC_DATA APU_DDC_CLK {25} HDMI Convert Carrizo
    {25} APU_HDMI_TX2+ APU_HDMI_TX2- DP1_TXP0 DP1_AUXN APU_HDMI_HPD APU_DDC_DATA {25}
    1 A3 F5
    {25} APU_HDMI_TX2- DP1_TXN0 DP1_HPD APU_HDMI_HPD {25}
    CC16
    150P_0402_50V8-J APU_HDMI_TX1+ B4 F8 APU_EDP_AUX +3VS_APU
    {25} APU_HDMI_TX1+ APU_HDMI_TX1- DP1_TXP1 DP0_AUXP APU_EDP_AUX# APU_EDP_AUX {23} RPC12
    @ A4 E8 CZL@
    2 {25} APU_HDMI_TX1- DP1_TXN1 DP0_AUXN G8 APU_EDP_HPD APU_EDP_AUX# {23} eDP APU_PROCHOT#_R 3 2
    CarrizoL:HDMI APU_HDMI_TX0+ D5 DP0_HPD APU_EDP_HPD {23} +3VALW_APU ALERT# 4 1
    {25} APU_HDMI_TX0+ APU_HDMI_TX0- DP1_TXP2 Core_type
    C5 K24 RC239 1 @ 2 100K_0402_5%
    {25} APU_HDMI_TX0- DP1_TXN2 RSVD_1 E15 1K_0404_4P2R_5%
    APU_HDMI_CLK+ A5 TEMPIN0 E14
    +1.8VS {25} APU_HDMI_CLK+ APU_HDMI_CLK- DP1_TXP3 TEMPIN1
    B5 E12
    {25} APU_HDMI_CLK- DP1_TXN3 TEMPIN2 F14
    TEMPINRETURN
    {23} APU_EDP_TX0+
    APU_EDP_TX0+ E2
    DP0_TXP0 TEST410
    AK24 TEST410 1 @ TC16 To EDP panel
    1

    APU_EDP_TX0- E1 AL24 TEST411 1 @ TC17


    {23} APU_EDP_TX0- DP0_TXN0 TEST411
    RC19 P24 TEST4 1 @ TC13
    300_0402_5% APU_EDP_TX1+ E3 TEST4 N24 TEST5 1 @ TC14 +3VS_APU
    eDP {23} APU_EDP_TX1+ APU_EDP_TX1- E4 DP0_TXP1 TEST5 AN24
    {23} APU_EDP_TX1- DP0_TXN1 TEST6 AB8
    2

    TEST9

    1
    D1 Y9
    APU_PWROK D2 DP0_TXP2 TEST10 B10 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5% +3VALW_APU RC70
    DP0_TXN2 TEST14 D11 APU_TEST15_BP1 1 @ TC18 4.7K_0402_5%
    C1 TEST15 A10 APU_TEST16_BP2 RC23 1 @ 2 1K_0402_5%
    PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf DP0_TXP3 TEST16

    2
    1 B1 C11 APU_TEST17_BP3 RC24 1 @ 2 1K_0402_5%

    2
    CC17 DP0_TXN3 TEST17 B11 APU_TEST11_BP4 RC1891 @ 2 1K_0402_5% RC71
    150P_0402_50V8-J APU_SVT_R TEST11 APU_TEST18_PLLTEST1 STN@
    RC249 1 2 0_0402_5% C15 A14 4 1 10K_0402_5%
    {49} APU_SVT APU_SVC_R SVT0 TEST18 APU_TEST19_PLLTEST0 PCH_EDP_PWM {23}
    @ RC213 1 2 0_0402_5% D17 B14 3 2
    2 {49} APU_SVC APU_SVD_R SVC0 TEST19
    RC215 1 2 0_0402_5% D19 1K_0404_4P2R_5%
    {49} APU_SVD

    1
    SVD0 RPC14 +3VS_APU +1.8VS
    STN@

    3
    APU_SVT_R B15 A13 APU_TEST28_H_PLLCHARZ 1 @ TC21 D
    C B16 SVT1 TEST28_H B13 APU_TEST28_L_PLLCHARZ 1 @ TC23 RC34 1 CZL@ 2 1K_0402_5% 5 QC8B C
    SVC1 TEST28_L
    1

    a
    CC210 A18 P26 APU_TEST31_MEM_TEST 1 @ TC25 RC28 1 STN@2 1K_0402_5% G DMN5L06DWK-7 2N SOT363-6
    1000P_0402_25V7-K SVD1 TEST31 E11 APU_TEST36_STEREOSYNC RC27 1 @ 2 1K_0402_5%
    @ APU_SIC B18 DP_STEREOSYNC/TEST36 A17 APU_TEST37 RC29 1 @ 2 1K_0402_5% S
    2

    4
    SIC TEST37

    6
    APU_SID C17 RC30 1 @ 2 1K_0402_5% D
    SID DP_EDP_PWM STN@
    2 QC8A
    +1.8VS +1.8VS APU_RST# D15 G

    hu
    RESET_L DMN5L06DWK-7 2N SOT363-6
    APU_PWROK C19
    {49} APU_PWROK PWROK

    1
    S

    1
    RC31 1 @ 2 0_0402_5% APU_PROCHOT#_R A15 RC11
    {35} H_PROCHOT# PROCHOT_L STN@
    ALERT# B17 100K_0402_5%
    ALERT_L
    4
    3

    H11
    RPC10 APU_TDI H15 VDDCR_GFX_SENSE J12 APU_VDDNB_SEN_H
    APU_VDDNB_SEN_H {49}

    2
    TDI VDDCR_NB_SENSE
    5

    APU_TDO H14 G12 APU_VDDCORE_SEN_H RC2051 CZL@ 2 0_0402_5%


    G

    1K_0404_4P2R_5% TDO VDDCR_CPU_SENSE APU_VDDCORE_SEN_H {49} STN@


    STN@ APU_TCK D13 AY18 VDD_095_FB_H 1
    APU_TMS G15 TCK VDDP_SENSE TC26 @
    1
    2

    APU_TRST# J14 TMS H12 APU_VSS_SEN_L RC2361 @ 2 0_0402_5%


    APU_SIC EC_SMB_CK2 APU_DBRDY TRST_L VSS_SENSE APU_VDD_SEN_L {49}
    4 3 C13

    g.
    S

    DBRDY
    D

    APU_DBREQ# A11
    STN@ DBREQ_L
    QC6B
    2

    DP_ENVDD RC2061 @ 2 0_0402_5%


    G

    DMN5L06DWK-7 2N SOT363-6 PCH_ENVDD {23}


    FP4 REV 0.93
    @ AMD-CARRIZO_FP4-BGA968
    APU_SID 1 6 EC_SMB_DA2
    S

    STN@ +3VS_APU
    QC6A
    DMN5L06DWK-7 2N SOT363-6 APU_VDDNB_SEN_H

    an
    1 @ TC27

    1
    APU_VDDCORE_SEN_H 1 @ TC28 +3VALW_APU RC245
    RPC7 CZL@ 4.7K_0402_5%
    APU_SIC 1 4 EC_SMB_CK2 APU_VDD_SEN_L 1 @ TC29
    EC_SMB_CK2 {16,30,35}

    2
    B APU_SID 2 3 EC_SMB_DA2 B
    EC_SMB_DA2 {16,30,35}

    2
    RC244
    STN@
    0_0404_4P2R_5% 10K_0402_5%
    PCH_ENBKL {23}

    1
    STN@

    3
    Hu
    D
    5 QC9B
    With HDT+ Header LCD Power IC can change for PCH_ENVDD for CZ cost down G DMN5L06DWK-7 2N SOT363-6
    +1.8VS +1.8VS
    S

    4
    6
    +1.8VS JHDT1 @ RPC5 D
    APU_TCK +1.8VS +1.8VS DP_ENBKL STN@
    1 2 8 1 2 QC9A
    1 2 7 2 G DMN5L06DWK-7 2N SOT363-6
    3 4 APU_TMS 6 3
    3 4
    2

    1
    5 4 1 S

    1
    1

    1
    RC7 5 6 APU_TDI RC246
    5 6 STN@
    1K_0402_5% 1K_0804_8P4R_5% CC25 RC32 RC36 100K_0402_5%
    7 8 APU_TDO 0.1U_0201_6.3V6-K 300_0402_5% 300_0402_5%
    7 8 2
    HDT@
    1

    2
    APU_TRST# RC76 1 HDT@ 2 33_0402_5% APU_TRST#_R 9 10 APU_PWROK_BUF RC2071 CZL@ 2 0_0402_5%
    STN@

    2
    9 10 UC6
    11 12 APU_RST#_BUF APU_PWROK 3 4 APU_PWROK_BUF
    r
    2 11 12 2A 2Y
    CC84 13 14 APU_DBRDY 2 5
    13 14 GND VCC
    0.01U_0201_6.3V7-K
    1 15 16 APU_DBREQ# APU_RST# 1 6 APU_RST#_BUF
    15 16 1A 1Y
    Fo
    8
    7
    6
    5

    17 18 APU_TEST19_PLLTEST0 HDT@ SN74LVC2G07YZPR_WCSP6


    RPC17 17 18
    10K_0804_8P4R_5% 19 20 APU_TEST18_PLLTEST1
    19 20
    HDT@
    1
    2
    3
    4

    A A
    SAMTE_ASP-136446-07-B

    PCH_ENBKL can to con EC ADC pin for CZ cost down because 1.8V level

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (DISPLAY/CLK/MISC)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 6 of 50
    5 4 3 2 1
    5 4 3 2 1

    RC46 1 2 33_0402_5% LPC_RST#_R +3VALW_APU


    {30,35} APU_LPC_RST#
    1
    CC20
    150P_0402_50V8-J

    2
    2 RC39 RC40 RC41
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    15@ UMA@ @

    1
    RC38 1 2 33_0402_5% PCIE_RST#_R BOARD_ID0
    {15,28,31} PLT_RST# BOARD_ID1
    BOARD_ID2

    1
    1
    RC43 CC19

    2
    D @ 100K_0402_5% 150P_0402_50V8-J D
    RC47 RC48 RC49
    2
    2 2K_0402_5% 2K_0402_5% 2K_0402_5%
    17@ PX@ @

    1
    +1.8VALW

    1
    Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.
    RC2472 1 RC53
    0_0402_5% 10K_0402_5%
    (CRB PWR Dealy: 22K/0.1uF) UC2D
    ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
    DC1 LPC_RST#_R BB12 BB2 @1 TC61

    2
    1 2 @ RSMRST#_R PCIE_RST#_R AN7 LPC_RST_L SD0_WP/EGPIO101 BB5 SD_PWR_CNTL @1
    {35} EC_RSMRST# PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 TC44
    BC2 ODD_DETECT# @1 TC75
    SD0_CD/AGPIO25
    LRB751V-40T1G_SOD323-2 1 Type1 2 3 all 1.8V RSMRST#_R AE4
    RSMRST_L SD0_CLK/EGPIO95
    BB4 @1
    TC45
    1

    AY5 @1
    PBTN_OUT# RC191 PWRBTN#_R SD0_CMD/EGPIO96 TC59
    RC66 CC21 1 2 0_0402_5% AE1
    {35} PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0
    @ 100K_0402_5% 0.1U_0201_6.3V6-K @ BC9
    2 SYS_RESET# AF2 PWR_GOOD
    {11} SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 SD_DATA0_R
    AG2 BC3 @1 TC62
    2

    WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BA3 SD_DATA1_R @1 TC63


    PM_SLP_S3# RC193 1 2 0_0402_5% PM_SLP_S3#_R AK7 SD0_DATA1/EGPIO98 BC5 SD_DATA2_R @1 TC64
    {35} PM_SLP_S3# PM_SLP_S5# RC194 PM_SLP_S5#_R SLP_S3_L SD0_DATA2/EGPIO99 SD_DATA3_R
    1 @ 2 0_0402_5% AH5 BA5 @1 TC65
    {35} PM_SLP_S5# SLP_S5_L SD0_DATA3/EGPIO100 SD_LED
    @ BB6
    SD0_LED/EGPIO93

    a
    AGPIO10 AE8
    APU_S5_MUX_CTRL AH8 S0A3_GPIO/AGPIO10 BA15 APU_SMB_CLK
    {9} APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_CLK {12,31}
    TEST0 AH6 SDA0/I2C2_SDA/EGPIO114
    AY17 APU_SMB_DATA
    RPC2
    APU_SMB_DATA {12,31} DIMM1, DIMM2, Mini CARD,HDMI Convert
    TEST0
    with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2 TEST1 AK8
    TEST1/TMS SCL1/I2C3_SCL/AGPIO19
    AG5 SCL1 1 4

    hu
    TEST2 AE3 AG4 SDA1 2 3
    +1.8VS TEST2 SDA1/I2C3_SDA/AGPIO20 CZL@
    C KBRST# AY15 10K_0404_4P2R_5% C
    {35} KBRST# ESPI_RESET_L/KBRST_L/AGPIO129
    BC19
    {35} GATEA20 GA20IN/AGPIO126
    1

    AD7 AL5
    {35} EC_SCI# ODD_DA# LPC_PME_L/AGPIO22 AGPIO3 AGPIO3 {11}
    RC72 BB13 AL6 AGPIO4
    LPC_SMI_L/AGPIO86 AGPIO4
    RC95 2 1 0_0402_5% 10K_0402_5% Delete Zero ODD circuit ODD_DA# 10/20 AGPIO5
    AJ1 AGPIO5
    @ CZL@ AC_PRESENT AG3 AJ3 LDT_RST_L @1 TC67 +3VS_APU
    {35} AC_PRESENT AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST_L
    Type2 1.8V, Type1 3 3.3V BOARD_ID0 AD5 AH1 LDT_PWROK @1 TC68
    2

    BOARD_ID1 AL8 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK AJ4 AGPIO8 RPC9


    DC2
    IR_TX1/USB_OC6_L/AGPIO14 AGPIO8
    1 2 @ SYS_PWRGD_R Delete Zero ODD circuit ODD_EN 10/20 AN8 AK5 APU_SMB_CLK 3 2

    g.
    {35} EC_SYS_PWRGD ODD_EN IR_RX1/AGPIO15 AGPIO9 APU_SMB_DATA
    1 AE2 AD8 4 1
    IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39
    1

    PCH_WLAN_OFF# BC15 AG8 AGPIO40


    LRB751V-40T1G_SOD323-2 {31} PCH_WLAN_OFF# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40
    RC82 CC22 BB17 AW15 AGPIO64 2.2K_0404_4P2R_5%
    {31} WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ1_L/AGPIO115 AGPIO64
    @ 100K_0402_5% 0.1U_0201_6.3V6-K BC17 AU15 RPC6
    2 {28} LAN_CLKREQ# PCH_BT_OFF# CLK_REQ2_L/AGPIO116 AGPIO65
    BB18 KBRST# 8 1
    {31} PCH_BT_OFF# GPU_CLKREQ# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 APU_SHUTDOWN#
    BB16 AT15 7 2
    {16} GPU_CLKREQ# APU_SHUTDOWN# {16}
    2

    BOARD_ID2 AH9 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L AU12 PCH_BT_OFF# 6 3


    USB_OC1# AG1 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AT14 AGPIO69 RC116 1 CZLPX@2 0_0402_5% PCH_WLAN_OFF# 5 4
    {32} USB_OC1# USB_OC2# USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD PXS_RST# {8,15}
    AH2 AR14
    AL9 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT BC13 10K_0804_8P4R_5%

    an
    USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN RPC21
    HDA_BITCLK AU6 BA17 ODD_DA# 1 4 @
    AZ_BITCLK/I2S_BCLK_MIC SPKR/AGPIO91 PCH_BEEP {34}
    RC201 2 1 0_0402_5% HDA_SDIN0_R AR8 ODD_DETECT# 2 3
    {34} HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/I2S_DATA_MIC0
    @ AP6 AN5
    HDA_SDIN2 AZ_SDIN1/I2S_LR_PLAYBACK BLINK/USB_OC7_L/AGPIO11 BLINK {11}
    AR5 10K_0404_4P2R_5%
    HDA_RST# AU9 AZ_SDIN2/I2S_DATA_MIC1 BB14 HVB_EN
    HDA_SYNC AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89 VR_VGA_PWRGD HVB_EN {11,35} LAN_CLKREQ#
    AT9 BA19 RC67 1 2 10K_0402_5%
    HDA_SDOUT AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 VR_VGA_PWRGD {15,48} WLAN_CLKREQ#
    RPC3 STN@ AR7 RC78 1 2 10K_0402_5%
    1 8 I2C1SDA AZ_SDOUT/I2S_DATA_PLAYBACK BC18 PXS_PWREN_R RC109 1 PX@ 2 1K_0402_5% GPU_CLKREQ# RC64 1 UMA@2 10K_0402_5%
    FANIN0/AGPIO84 PXS_PWREN {19,48} APU_SHUTDOWN#
    2 7 I2C1SCL I2C0SCl BB10 BB19 RC96 1 2 10K_0402_5%
    I2C0_SCL/EGPIO145 FANOUT0/AGPIO85

    Hu
    PCIE_WAKE#_RA RC88 2 1 0_0402_5% 3 6 I2C0SCl I2C0SDA BB9 CZL@
    @ 4 5 I2C0SDA I2C1SCL BB7 I2C0_SDA/EGPIO146 AY9
    I2C1SDA BC7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AW8
    AGPIO5 2 @ 1 RC92 10K_0804_8P4R_5% I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AV5
    APU_SHUTDOWN# +3VALW_APU
    PCIE_WAKE# {28,31,35}
    0_0402_5% AG7 UART0_RTS_L/EGPIO137 AV8 inter pull down for Cz,pull high for Czl
    {11,31} SUSCLK RTCCLK UART0_TXD/EGPIO138 AW9
    2 1 DC3 UART0_INTR/AGPIO139 RPC15
    32K_X1 AT1 AV11 PCIE_WAKE#_RA 1 8
    SDM10U45LP-7_DFN1006-2-2 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AU7 AC_PRESENT 2 7
    B UART1_RXD/BT_I2S_SDI/EGPIO141 B
    @ DC4 AT11 AGPIO5 3 6
    SYS_RESET# 1 2 @ SYS_PWRGD_R UART1_RTS_L/EGPIO142 AR11 PBTN_OUT# 4 5
    +3VALW_APU RC102 32K_X2 AT2 UART1_TXD/BT_I2S_SDO/EGPIO143 AP9
    1 2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144 10K_0804_8P4R_5%
    LRB751V-40T1G_SOD323-2 FP4 REV 0.93
    1 20M_0402_5% RPC16
    YC1 @ USB_OC1# 1 4
    AMD-CARRIZO_FP4-BGA968
    2

    CC38 1 2 USB_OC2# 2 3
    r
    RC84 RC85 RC20 0.1U_0201_6.3V6-K Max ESR < 65K ohm !!
    2 202983-PG14 10K_0404_4P2R_5%
    2.2K_0402_5% 1K_0402_5% 2.2K_0402_5%
    20P_0402_50V8

    20P_0402_50V8

    ODD_EN RC141 1 2 10K_0402_5%


    @ @ @
    PM_SLP_S3# RC203 1 @ 2 2.2K_0402_5%
    1 1
    change YC1 from SIWARD SJ10000M500 to Micro crystalSJ10000M900, SIWARD as 2nd source
    1

    PM_SLP_S5#
    CC23

    CC24

    TEST0 RC208 1 @ 2 2.2K_0402_5%


    Fo
    TEST1 AGPIO40 RC145 1 STN@ 2 10K_0402_5%
    TEST2 PXS_PWREN AGPIO4 RC94 1 @ 2 10K_0402_5%
    2 2 APU_S5_MUX_CTRL RC248 1 2 100K_0402_5%
    2

    RC195 RC196 RC197 STN@


    15K_0402_5% 15K_0402_5% 15K_0402_5%
    AGPIO4 RC86 1 CZL@ 2 10K_0402_5%
    AGPIO64 RC93 1 CZL@ 2 10K_0402_5%
    1

    QC15 D RPC4
    RC170 1 @ 2 2
    {35} VGA_GATE# G HDA_RST#
    0_0402_5% 1 8 AGPIO8 RC83 1 STN@ 2 10K_0402_5%
    {34} HDA_RST_AUDIO# HDA_SYNC
    1 2 7
    S {34} HDA_SYNC_AUDIO HDA_BITCLK
    L2N7002KWT1G_SOT323-3 3 6
    {34} HDA_BITCLK_AUDIO
    3

    CC96 4 5 HDA_SDOUT
    @ {34} HDA_SDOUT_AUDIO SD_LED
    0.1U_0201_6.3V6-K RC97 1 CZL@ 2 10K_0402_5%
    2 @ 33_0804_8P4R_5%
    AGPIO10 RC80 1 2 10K_0402_5%
    +3VS_APU
    APU_SHUTDOWN# RC68 1 @ 2 10K_0402_5%
    GPU_CLKREQ# RC65 1 PX@ 2 2K_0402_5%
    RC98 1 PX@ 2 10K_0402_5% PXS_PWREN_R
    RC99 1 @ 2 10K_0402_5% PXS_RST# HDA_BITCLK RC90 1 @ 2 10K_0402_5%
    RC100 1 @ 2 10K_0402_5% VR_VGA_PWRGD HDA_SDIN0_R RC91 1 @ 2 10K_0402_5%

    A RC101 1 @ 2 100K_0402_5% PXS_PWREN_R A


    RC103 1 PX@ 2 2K_0402_5% PXS_RST# RSMRST#_R RC87 1 2 100K_0402_5%
    RC104 1 UMA@2 2K_0402_5% VR_VGA_PWRGD SYS_PWRGD_R RC89 1 2 100K_0402_5%

    HDA_SDIN2 RC241 1 @ 2 10K_0402_5%


    CRB: CARRIZO NEED 10K PD ON UNUSED SDIN HDA_SDIN1 RC242 1 @ 2 10K_0402_5%
    DG: 10K PD
    PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k
    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (GEVENT/GPIO/SD/AZ)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 7 of 50
    5 4 3 2 1
    5 4 3 2 1

    UC2E
    CLK/SATA/USB/SPI/LPC
    SATA_PTX_DRX_P0 AU3 AP8
    {33} SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_TX0P USBCLK/25M_48M_OSC
    AU4
    {33} SATA_PTX_DRX_N0 SATA_TX0N USB_RCOMP
    HDD AP5 RC112 1 2 11.8K_0402_1%
    SATA_PRX_DTX_N0 AV1 USB_ZVSS
    {33} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_RX0N USB20_P0
    AV2 AR2
    {33} SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_N0 USB20_P0 {32}
    AR1 Left USB2.0
    SATA_PTX_DRX_P1 USB_HSD0N USB20_N0 {32}
    AY2
    {33} SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_TX1P
    AY1 AR3
    +3VS_APU {33} SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P
    ODD AR4 RIGHT USB (2.0)
    SATA_PRX_DTX_N1 AW4 USB_HSD1N
    {33} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_RX1N
    AW3 AN2
    D {33} SATA_PRX_DTX_P1 SATA_RX1P USB_HSD2P D
    AN1
    +0.95VS RC113 1 2 1K_0402_1% SATA_CALRN AW1 USB_HSD2N
    RC114 1 2 1K_0402_1% SATA_CALRP AW2 SATA_ZVSS AN3 USB20_P3
    RPC13 SATA0_DEVSLP_R SATA_ZVDDP USB_HSD3P USB20_N3 USB20_P3 {24}
    AT17 AN4 Card Reader
    DEVSLP0/EGPIO67 USB_HSD3N USB20_N3 {24}
    3 2 EGPIO70 EGPIO70 AT12
    4 1 SATA0_DEVSLP_R APU_TS_ON# BB15 DEVSLP1/EGPIO70 AM1 USB20_P4
    SATA_ACT_L/AGPIO130 USB_HSD4P USB20_N4 USB20_P4 {31}
    AM2 Blue Tooth
    USB_HSD4N USB20_N4 {31}
    10K_0404_4P2R_5% AU2
    STN@
    Nano not support Touch 10/20 SATA_X1 AL2 USB20_P5
    USB_HSD5P USB20_P5 {23}
    AGPIO130 CZ STN OD output, CZL output USB_HSD5N
    AL1 USB20_N5
    USB20_N5 {23} Camera
    RC147 1 2 10K_0402_5% APU_TS_ON# AU1 AL3 USB20_P6
    SATA_X2 USB_HSD6P USB20_N6 USB20_P6 {32}
    AL4 LEFT USB (3.0) upper
    USB_HSD6N USB20_N6 {32}
    CLK_PCIE_GPU RC117 1 2 0_0402_5% CLK_PCIE_GPU_R U4 AK2
    {15} CLK_PCIE_GPU CLK_PCIE_GPU# GFX_CLKP USB_HSD7P
    RC118 1 @ 2 0_0402_5% CLK_PCIE_GPU#_R U3 AJ2
    {15} CLK_PCIE_GPU# GFX_CLKN USB_HSD7N
    @
    U1
    U2 GPP_CLK0P
    GPP_CLK0N
    CLK_PCIE_WLAN RC119 1 2 0_0402_5% CLK_PCIE_WLAN_R W4
    CarrizoL don't support USB_SS_[1:0]
    {31} CLK_PCIE_WLAN GPP_CLK1P
    {31} CLK_PCIE_WLAN#
    CLK_PCIE_WLAN# RC120 1 @ 2 0_0402_5% CLK_PCIE_WLAN#_R W3
    GPP_CLK1N
    Note: Route USB 3.0 ports starting from the lowest numbered port,
    @
    {28} CLK_PCIE_LAN
    CLK_PCIE_LAN RC121 1 2 0_0402_5% CLK_PCIE_LAN_R W1 for example, Port0, Port1, Port2.
    CLK_PCIE_LAN# 2 0_0402_5% CLK_PCIE_LAN#_R GPP_CLK2P
    RC122 1 @ W2 All unused ports should be the highest numbered ports.

    a
    {28} CLK_PCIE_LAN# GPP_CLK2N
    @
    Y2
    GPP_CLK3P
    For CZ and CZL Co-lay, can start from Port2
    Y1
    GPP_CLK3N

    hu
    TC53 @ 1 X14M_25M_48M_OSC BC10
    X25M_48M_OSC AD2 USBSS_CALRN RC123 1 2 1K_0402_1% +0.95VALW
    USB_SS_ZVSS AD1 USBSS_CALRP RC124 1 2 1K_0402_1%
    C 48M_X1 T2 USB_SS_ZVDDP C
    X48M_X1 AA3
    USB_SS_0TXP AA4
    USB_SS_0TXN USB3.0 port0 must map to USB2.0 port4,
    48M_X2 T1
    X48M_X2 USB_SS_0RXP
    W9 USB3.0 port1 must map to USB2.0 port5,

    g.
    W8
    {30} TPM_CLK RC125 1 TPM@ 2 22_0402_5% USB_SS_0RXN USB3.0 port2 must map to USB2.0 port6,
    {11,35} CLK_PCI_EC
    RC126
    RC127
    1
    1
    2 3.3_0402_1%
    2 0_0402_5%
    LPCCLK0
    LPCCLK1
    AW14
    AY13 LPCCLK0/EGPIO74 USB_SS_1TXP
    AA2
    AA1
    USB3.0 port0 must map to USB2.0 port7
    {11} LPC_CLK1 LPCCLK1/EGPIO75 USB_SS_1TXN
    @
    BB11 W5
    Less than two USB 3.0 ports can be utilized provided
    {30,35} LPC_AD0 LAD0 USB_SS_1RXP
    {30,35} LPC_AD1
    BA11
    LAD1 USB_SS_1RXN
    W6 the unused ports are higher-numbered consecutive
    {30,35} LPC_AD2 AY11
    {30,35} LPC_AD3 BA13 LAD2 AC1 USB30_TX_P2 ports. 10.15
    LAD3 USB_SS_2TXP USB30_TX_P2 {32}

    an
    AV14 AC2 USB30_TX_N2
    {11,30,35} LPC_FRAME# LFRAME_L USB_SS_2TXN USB30_TX_N2 {32}
    TC54 @ 1 BA1 LEFT USB (3.0) upper
    BC14 ESPI_ALERT_L/LDRQ0_L Y6 USB30_RX_P2
    {30,35} SERIRQ SERIRQ/AGPIO87 USB_SS_2RXP USB30_RX_P2 {32}
    BC11 Y7 USB30_RX_N2
    LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN USB30_RX_N2 {32}
    RC149 1 2 10K_0402_5% AGPIO21 AE9
    LPC_PD_L/AGPIO21 AC4
    USB_SS_3TXP AC3
    SPI_CLK RC209 1 @ 2 0_0402_5% SPI_CLK_R BC6 USB_SS_3TXN
    {35} SPI_CLK SPI_CS0# SPI_CS0#_R SPI_CLK/ESPI_CLK/EGPIO117
    RC202 1 @ 2 0_0402_5% BB8 AB5

    Hu
    {35} SPI_CS0# SPI_CS1_L/EGPIO118 USB_SS_3RXP
    RC144 1 STN@2 10K_0402_5% EGPIO119 AW7 AB6
    SPI_SO RC199 1 @ 2 0_0402_5% SPI_SO_R BA9 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN
    {35} SPI_SO SPI_SI SPI_SI_R SPI_DI/ESPI_DATA/EGPIO120
    RC198 1 @ 2 0_0402_5% AY7
    {35} SPI_SI SPI_WP# SPI_WP#_R SPI_DO/EGPIO121
    RC132 1 @ 2 0_0402_5% AW11
    SPI_HOLD# RC133 1 @ 2 0_0402_5% SPI_HOLD#_R BA7 SPI_WP_L/EGPIO122
    RC143 1 @ 2 10K_0402_5% AGPIO76 AW12 SPI_HOLD_L/EGPIO133
    SPI_TPM_CS_L/AGPIO76
    FP4 REV 0.93
    RC243 1 STNPX@2 0_0402_5%
    {7,15} PXS_RST#
    @
    B 48MHz/10pF Crystal AMD-CARRIZO_FP4-BGA968 B
    Reference CG412, only reserved for Stoney
    48M_X1
    r
    +VCC_SPI
    48M_X2
    +VCC_SPI

    8M ROM 1
    Fo
    RC140 1 2 1M_0402_5% +3VALW_APU
    CC27 +1.8VS
    0.1U_0201_6.3V6-K +VCC_SPI RC1351 CZL@ 2 0_0402_5%
    YC2 UC3 2 SPI_CLK
    SPI_CS0# 1 8 RC1921 STN@ 2 0_0402_5%
    1 4 CS# VCC
    OSC1 NC2

    2
    SPI_SO 2 7 SPI_HOLD#
    2 3 DO HOLD# +VCC_SPI
    NC1 OSC2 SPI_WP# 3 6 SPI_CLK RC139
    WP# CLK 10_0402_5%
    1 1
    48MHZ 10PF X1E000021083400 4 5 SPI_SI RPC8 EMC_NS@

    1
    CC28 CC29 GND DI SPI_WP# 1 4
    12P_0402_50V8-J 12P_0402_50V8-J SPI_HOLD# 2 3
    2 2 W25Q64FVSSIQ_SO8 2
    10K_0404_4P2R_5% CC26
    CZL@ 10P_0402_50V8J
    SPI_CS0# RC138 1 2 10K_0402_5% EMC_NS@
    1
    with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ EMC

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (SATA/USB/LPC/SPI)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 8 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.35V UC2F +APU_CORE +APU_CORE


    POWER

    3A P25 U8
    +1.35V VDDIO_MEM_S3_1 VDDCR_CPU_1

    180P_0402_50V8-J
    P28 W7
    T24 VDDIO_MEM_S3_2 VDDCR_CPU_2 W12
    T27 VDDIO_MEM_S3_3 VDDCR_CPU_3 W15
    VDDIO_MEM_S3_4 VDDCR_CPU_4 1 1 1 1 1 1 1 1 1

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    180P_0402_50V8-J

    CC137
    U25 W18
    VDDIO_MEM_S3_5 VDDCR_CPU_5

    CC129

    CC130

    CC131

    CC132 SIVCD@

    CC133

    CC134

    CC135 SIVCD@

    CC136
    1 1 1 1 1 1 1 U28 W21
    +1.35V VDDIO_MEM_S3_6 VDDCR_CPU_6

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    CC165
    V30 Y8
    VDDIO_MEM_S3_7 VDDCR_CPU_7 2 2 2 2 2 2 2 2 2

    CC157

    CC158

    CC159 SIVCD@

    CC160

    CC161 SIVCD@

    CC163
    V33 Y10
    W24 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y13
    2 2 2 2 2 2 2 W27 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y16
    VDDIO_MEM_S3_10 VDDCR_CPU_10
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    Y25 Y19
    Y28 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y22
    1 1 1 1 1 1 1 1 1 1 1 VDDIO_MEM_S3_12 VDDCR_CPU_12 OK
    CC42

    CC54

    CC55

    CC56

    CC57

    CC58

    CC59

    CC60

    CC53

    CC61

    CC62
    SIVCD@ Y30 AB7
    AB24 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB9
    OK AB27 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB12
    D D
    @ 2 2 2 2 2 2 2 2 @ 2 @ 2 2 AB30 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB15
    AB33 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB18
    AD25 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB21
    SIVCD@ SIVCD@ AD28 VDDIO_MEM_S3_18 VDDCR_CPU_18 AD6
    AD30 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD10
    +VAUDIO +VDDIO_AZ_APU AE24 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD13
    RC212 1 2 0_0402_5% AE27 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD16
    Wake-on-Ring not supported: VDDIO_MEM_S3_22 VDDCR_CPU_22

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    @ AF30 AD19
    +VDDIO_AZ_APU Connect to +1.5V S0 rail 1 1 1 AF33 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD22
    VDDIO_MEM_S3_24 VDDCR_CPU_24

    CC184

    CC185

    CC193
    AG25 AE7
    FP4 Type 3 (Stoney) processors do not use the VDDP_GFX AG28 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE12
    AH24 VDDIO_MEM_S3_26 VDDCR_CPU_26 AK9
    power rail so leave VDDP_GFX unconnected. 2 2 2 AH27 VDDIO_MEM_S3_27 VDDCR_CPU_42 AG10
    +0.95VS +0.95VS_GFX_APU AH30 VDDIO_MEM_S3_28 VDDCR_CPU_31 AK10
    RC210 1 CZLPX@2 0_0805_5% AK25 VDDIO_MEM_S3_29 VDDCR_CPU_43 AG13
    place near SVC/SVD/SVT Bus
    VDDIO_MEM_S3_30 VDDCR_CPU_32

    10U_0603_6.3V6M
    SIVCD@ AK28 AK13
    VDDIO_MEM_S3_31 VDDCR_CPU_44

    100_0402_5%
    1 1 AK30 AG16
    VDDIO_MEM_S3_32 VDDCR_CPU_33

    0.22U_0201_6.3V6-K
    CC180
    If P_GFX[7:0] are not used, AK33 AK16
    VDDIO_MEM_S3_33 VDDCR_CPU_45 +1.35V

    CC181 CZLPX@
    RC229
    AL27 AG19 DECOUPLING BETWEEN PROCESSOR AND DIMMs
    VDDP_GFX power balls can be connected to VSS. AM30 VDDIO_MEM_S3_34 VDDCR_CPU_34 AK19
    2
    CZLPX@ 2 VDDIO_MEM_S3_35 VDDCR_CPU_46 AG22 ACROSS VDDIO AND VSS SPLIT
    CZLUMA@ AR19 VDDCR_CPU_35 AK22
    0.2A

    2
    VDDIO_AUDIO VDDCR_CPU_47

    180P_0402_50V8-J

    180P_0402_50V8-J
    AH7
    AE6 VDDCR_CPU_36 AE18
    1.5A VDDP_GFX_2 VDDCR_CPU_28 1 1 1 1 1 1

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    CC179

    CC176
    AE5 AE21
    +3VS RC214 +3VS_APU VDDP_GFX_1 VDDCR_CPU_29

    CC168

    CC169

    CC170 SIVCD@

    CC172
    AH21
    1 2 AP19 VDDCR_CPU_40 AG6
    @
    0.2A AP21 VDD_33_1 VDDCR_CPU_30 AH12 2 2 2 2 2 2
    1 VDD_33_2 VDDCR_CPU_37
    +1.8VS
    10U_0603_6.3V6M
    CC187

    0_0402_5% AN6
    AP16 VDDCR_CPU_49 AH15
    1.5A VDD_18_1 VDDCR_CPU_38

    a
    10U_0603_6.3V6M

    AP18 AH18
    2 +1.8VALW VDD_18_2 VDDCR_CPU_39 AL7
    1 1 VDDCR_CPU_48
    0.22U_0201_6.3V6-K
    CC186

    0.5A AP10 AK6


    VDD_18_S5_1 VDDCR_CPU_41
    CC173

    AR9 AE15
    +3VALW_APU VDD_18_S5_2 VDDCR_CPU_27
    10U_0603_6.3V6M

    2 2 AP15
    0.2A

    hu
    1 1 VDD_33_S5_1
    0.22U_0201_6.3V6-K
    CC188

    AR15 L8
    +0.95VALW VDD_33_S5_2 VDDCR_GFX_14
    CC189

    10U_0603_6.3V6M
    L13 Design Guide G FP4 CRB
    SIVCD@ AN12 VDDCR_GFX_15 L16
    2 2 1 1 0.8A VDDP_S5_1 VDDCR_GFX_16

    0.22U_0201_6.3V6-K

    10U_0603_6.3V6M
    CC190
    AP12 L19 9*22uf 0603 9*22uf 0805 13*22uf 0603
    +VDDCR_FCH_S5 VDDP_S5_2 VDDCR_GFX_17

    CC191
    C 1 1 L22 VDDCR_CPU 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402 C
    VDDCR_GFX_18

    0.22U_0201_6.3V6-K
    CC182
    0.2A AP13 N7 1*180pf 0402 1*180pf 0402 1*180pf 0402
    +0.95VS 2 2 VDDCR_FCH_S5_1 VDDCR_GFX_19

    CC183
    AR12 N12 4*22uf 0603 4*22uf 0805 6*22uf 0603
    +0.95VS VDDCR_FCH_S5_2 VDDCR_GFX_20 N15 8*0.22uf 0402 8*0.22uf 0402 8*0.22uf 0402 split *5
    2 2 VDDCR_GFX_21 VDDCR_NB
    7A AW19 N18 1*180pf 0402 1*180pf 0402 1*180pf 0402
    VDDP_6 VDDCR_GFX_22
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0402_6.3V6M

    10U_0402_6.3V6M

    180P_0402_50V8-J

    AU17 N21 9*22uf 0603 10*22uf 0805 13*22uf 0603


    AU19 VDDP_1 VDDCR_GFX_23 P8 9*0.22uf 0402 9*0.22uf 0402 9*0.22uf 0402

    g.
    1 1 1 1 1 1 1 1 1 1 1 VDDP_2 VDDCR_GFX_24 VDDCR_GFX
    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    CC175

    CC174

    CC171

    CC167

    CC177

    AV17 P13 1*180pf 0402 1*180pf 0402 1*180pf 0402


    VDDP_3 VDDCR_GFX_25
    CC178

    CC197

    CC198

    CC201

    CC202

    CC203

    AV19 P16 8*22uf 0603 8*22uf 0603 8*22uf 0603


    AW17 VDDP_4 VDDCR_GFX_26 P19 6*0.22uf 0402 split*4 6*0.22uf 0402 split*4 8*0.22uf 0402 split*4
    2 2 2 2 2 2 2 2 2 2 2 +APU_CORE_NB VDDP_5 VDDCR_GFX_27 VDDIO_MEM_S3
    P22 1*180pf 0402 split*2 1*180pf 0402 split*2 1*180pf 0402 split*2
    AL12 VDDCR_GFX_28 T7 2*10uf 0402 2*10uf 0603 2*10uf 0603
    12A AL13 VDDCR_NB_1 VDDCR_GFX_29 F12 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    VDDCR_NB_2 VDDCR_GFX_1 VDDCR_FCH_S5
    SIVCD@ AL15 F15
    AL18 VDDCR_NB_3 VDDCR_GFX_2 G11 4*10uf 0402 4*10uf 0603 4*10uf 0603
    OK AL21 VDDCR_NB_4 VDDCR_GFX_3 G14 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    VDDCR_NB_5 VDDCR_GFX_4 VDDP
    AN13 J8 1*180pf 0402 1*180pf 0402 1*180pf 0402
    VDDCR_NB_6 VDDCR_GFX_5

    an
    AN16 J9 1*10uf 0402 1*10uf 0603 1*10uf 0603
    +APU_CORE_NB AN19 VDDCR_NB_7 VDDCR_GFX_6 J11 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    VDDCR_NB_8 VDDCR_GFX_7 VDDP_GFX
    AN22 K7
    VDDCR_NB_9 VDDCR_GFX_8 K12 1*10uf 0402 1*10uf 0603 1*10uf 0603
    +RTCBATT +RTCBATT_APU VDDCR_GFX_9 K13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    VDDCR_GFX_10 VDDP_S5
    180P_0402_50V8-J

    RC6 1 2 AR17 K15


    1K_0402_5% VDDBT_RTC_G VDDCR_GFX_11 K16 1*22uf 0603 1*22uf 0603 1*22uf 0603
    1 1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_GFX_12
    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    CC145

    T12 VDD_18 1*10uf 0402 1*10uf 0402 1*10uf 0603


    VDDCR_GFX_30
    CC138

    CC139

    CC140

    CC141 SIVCD@

    CC142

    CC143

    CC144 SIVCD@

    CC146

    CC195 @

    CC196 @

    CC199 @

    CC200 @

    T15
    VDDCR_GFX_31 T18 1*10uf 0402 1*10uf 0603 1*10uf 0603
    2 2 2 2 2 2 2 2 2 2 2 2 2 1 VDDCR_GFX_32

    0.22U_0201_6.3V6-K
    T21 VDD_18_S5 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    VDDCR_GFX_33

    Hu CC192
    U13
    VDDCR_GFX_34 U16
    2 VDDCR_GFX_35 U19 1*10uf 0402 1*10uf 0603 1*10uf 0603
    VDDCR_GFX_36 VDD_33
    OK follow CRB reserve U22
    VDDCR_GFX_37 K19 1*10uf 0402 1*10uf 0403 1*10uf 0603
    VDDCR_GFX_13 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    FP4 REV 0.93
    VDD_33_S5
    UC5
    +VCCRTC @ AMD-CARRIZO_FP4-BGA968 3*1uf 0402 3*1uf 0402 3*1uf 0402
    VDDIO_AUDIO
    RC231 1 2 10K_0402_5% 1
    Vin
    3 +RTCBATT VDDBT_RTC_G 1*0.22uf 0402 1*0.22uf 0402 1*0.22uf 0402
    Vout
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    B 2 B
    1 GND 1
    1
    CC37

    CC194

    JCMOS1 RC8 @
    SHORT PADS 470_0603_5%
    AP2138N-1.5TRG1_SOT23-3 @
    r
    2

    2 2
    12

    D QC7
    2 EC_RTCRST#_ON QC1/QC2/QC3/QC4 Rds on should less possible, CRB is 11.8mohm,
    G EC_RTCRST#_ON {35}
    there is no load swtich for 0.775V power, so it need mos
    1

    Fo
    S
    L2N7002KWT1G_SOT323-3 RC15
    3

    100K_0402_5%
    @
    @
    2

    +APU_CORE_NB +VDDCR_FCH_S5
    UC7
    1 8
    VIN1_1 VOUT_1
    10U_0603_6.3V6M

    2 7
    VIN1_2 VOUT_2
    1

    +0.775VALW
    CC207

    0.22U_0201_6.3V6-K
    10U_0603_6.3V6M

    10U_0603_6.3V6M
    3 6 APU_S5_MUX_CTRL
    +5VALW VIN2 SEL APU_S5_MUX_CTRL {7}
    10U_0603_6.3V6M

    1 1 1
    2

    CC162

    CC164

    CC166
    STN@ 4 5
    VCC EN
    1
    CC208

    1U_0402_6.3V6K

    1 9
    GND 2 2 2
    CC209
    2

    STN@
    G5018RD1U_TDFN8_3X3
    2
    STN@ STN@ STN@ STN@
    STN@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (POWER&DECOUPLING)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 9 of 50
    5 4 3 2 1
    5 4 3 2 1

    UC2G UC2H
    GND GND
    A8 L28 AE10 AV30
    A12 VSS_1 VSS_63 M4 AE13 VSS_125 VSS_187 AV33
    A16 VSS_2 VSS_64 M30 AE16 VSS_126 VSS_188 AW22
    A20 VSS_3 VSS_65 N10 AE19 VSS_127 VSS_189 AY4
    A24 VSS_4 VSS_66 N13 AE22 VSS_128 VSS_190 AY6
    A28 VSS_5 VSS_67 N16 AF1 VSS_129 VSS_191 AY8
    D D
    A32 VSS_6 VSS_68 N19 AF4 VSS_130 VSS_192 AY10
    B2 VSS_7 VSS_69 N22 AG9 VSS_131 VSS_193 AY12
    B8 VSS_8 VSS_70 N27 AG12 VSS_132 VSS_194 AY14
    B12 VSS_9 VSS_71 P1 AG15 VSS_133 VSS_195 AY16
    B33 VSS_10 VSS_72 P2 AG18 VSS_134 VSS_196 AY20
    C3 VSS_11 VSS_73 P4 AG21 VSS_135 VSS_197 AY22
    D4 VSS_12 VSS_74 P5 AH4 VSS_136 VSS_198 AY24
    D6 VSS_13 VSS_75 P12 AH10 VSS_137 VSS_199 AY26
    D8 VSS_14 VSS_76 P15 AH13 VSS_138 VSS_200 AY28
    D10 VSS_15 VSS_77 P18 AH16 VSS_139 VSS_201 AY30
    D12 VSS_16 VSS_78 P21 AH19 VSS_140 VSS_202 BB1
    D14 VSS_17 VSS_79 P30 AH22 VSS_141 VSS_203 BB33
    D16 VSS_18 VSS_80 P33 AK1 VSS_142 VSS_204 BC4
    D18 VSS_19 VSS_81 T4 AK4 VSS_143 VSS_205 BC8
    D20 VSS_20 VSS_82 T10 AK12 VSS_144 VSS_206 BC12
    D22 VSS_21 VSS_83 T13 AK15 VSS_145 VSS_207 BC16
    D24 VSS_22 VSS_84 T16 AK18 VSS_146 VSS_208 BC20
    D26 VSS_23 VSS_85 T19 AL16 VSS_147 VSS_209 BC24

    a
    D28 VSS_24 VSS_86 T22 AL19 VSS_148 VSS_210 BC28
    D30 VSS_25 VSS_87 T30 AL22 VSS_149 VSS_211 BC32
    F1 VSS_26 VSS_88 U5 AM4 VSS_150 VSS_212
    VSS_27 VSS_89 VSS_151

    hu
    F2 U12 AN9
    F4 VSS_28 VSS_90 U15 AN10 VSS_152
    F9 VSS_29 VSS_91 U18 AN15 VSS_153
    C
    F19 VSS_30 VSS_92 U21 AN18 VSS_154 C
    F22 VSS_31 VSS_93 U24 AN21 VSS_155
    F25 VSS_32 VSS_94 V1 AN25 VSS_156
    F30 VSS_33 VSS_95 V2 AN28 VSS_157

    g.
    F33 VSS_34 VSS_96 V4 AP1 VSS_158
    G7 VSS_35 VSS_97 W10 AP2 VSS_159
    G17 VSS_36 VSS_98 W13 AP4 VSS_160
    G20 VSS_37 VSS_99 W16 AP7 VSS_161
    G23 VSS_38 VSS_100 W19 AP22 VSS_162
    G26 VSS_39 VSS_101 W22 AP27 VSS_163
    H4 VSS_40 VSS_102 Y4 AP30 VSS_164

    an
    H30 VSS_41 VSS_103 Y5 AP33 VSS_165
    VSS_42 VSS_104 VSS_166 UC2J
    J5 Y12 AR6
    J15 VSS_43 VSS_105 Y15 AR25 VSS_167
    J19 VSS_44 VSS_106 Y18 AR28 VSS_168 @ TC4 1 U30
    J22 VSS_45 VSS_107 Y21 AT4 VSS_169 @ TC6 1 U31 RSVD_2
    J25 VSS_46 VSS_108 Y24 AT19 VSS_170 @ TC5 1 AN30 RSVD_3
    VSS_47 VSS_109 VSS_171 RSVD_4

    Hu
    J28 AB1 AT22
    K1 VSS_48 VSS_110 AB2 AT30 VSS_172
    K2 VSS_49 VSS_111 AB4 AU5 VSS_173
    K4 VSS_50 VSS_112 AB10 AU8 VSS_174
    K10 VSS_51 VSS_113 AB13 AU11 VSS_175
    K22 VSS_52 VSS_114 AB16 AU14 VSS_176
    K27 VSS_53 VSS_115 AB19 AU20 VSS_177
    K30 VSS_54 VSS_116 AB22 AU23 VSS_178 FP4 REV 0.93
    B B
    K33 VSS_55 VSS_117 AD4 AU27 VSS_179
    L5 VSS_56 VSS_118 AD9 AV4 VSS_180 @
    VSS_57 VSS_119 VSS_181 AMD-CARRIZO_FP4-BGA968
    r
    L12 AD12 AV7
    L15 VSS_58 VSS_120 AD15 AV9 VSS_182
    L18 VSS_59 VSS_121 AD18 AV12 VSS_183 L24
    VSS_60 VSS_122 VSS_184 VSS_213
    Fo
    L21 AD21 AV15 AL10
    L25 VSS_61 VSS_123 AD24 AV25 VSS_185 VSS_215 AK21
    VSS_62 VSS_124 VSS_186 VSS_214
    FP4 REV 0.93 FP4 REV 0.93
    @ AMD-CARRIZO_FP4-BGA968 @ AMD-CARRIZO_FP4-BGA968

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (VSS)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 10 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VS +3VALW_APU +3VS +3VALW_APU +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

    2
    RC152 RC169 RC153 RC200 RC154 RC173 RC155 RC156 RC157 RC158 RC81
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    @ @ @ @ @ @
    D D

    1
    {8,30,35} LPC_FRAME#

    {8} LPC_CLK1

    {8,35} CLK_PCI_EC

    {7} AGPIO3

    {7} SYS_RESET#

    {7,31} SUSCLK

    {7} BLINK

    a
    {7,35} HVB_EN

    1
    hu
    RC79
    C RC159 RC160 RC161 RC162 RC163 RC164 RC165 C
    2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
    @ @ @ @ @ @

    2
    STRAP PINS

    g.
    LFRAME_L LPCCLK1 LPCCLK0 GEVENT2_L/AGPIO3 SYS_RESET_L RTCCLK BLINK(for CZL strap) HVB_EN
    Signal

    an
    Int pull-up Int pull-up Int pull-up Int pull-up

    Type II II II II I I I I
    CZL CZ
    SPI ROM Internal Boot Fail Timer Normal Power Up Coin Battery PWROK and RST_L floating
    PULL Enhanced reset

    Hu
    CLK Gen Enabled &Reset Timing pin routed to APU
    HIGH 1.8V SPI logic (for quicker Disable HVB
    Default Default S5 resume) on FP4 platforms
    Default Default Default
    Default Default
    B B
    Boot Fail Timer Default to Reserved Direct DC Reserved connected to VSS
    PULL LPC ROM Reserved Disabled 3.3VSPI traditional
    LOW reset logic Enable HVB
    Default Default on FP4 platforms
    r
    Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
    Fo
    Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
    Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
    If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

    All Strap pins must be configured with either external pull-up or pull-down resistors.
    Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘1’ for CZ AGPIO3

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 FP4 (STRAPS)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 11 of 50
    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQ[0..63]
    DDRB_DQ[0..63] {5}
    DDR3 SO-DIMM A DDRB_DQS[0..7]
    DDRB_DQS[0..7] {5}
    DDRB_DQS#[0..7]
    DDRB_DQS#[0..7] {5}
    DDRB_MA[0..15]
    +VREF_DQ DDRB_MA[0..15] {5}
    JDDR1
    1 2 DDRB_DM[0..7]
    VREF_DQ VSS1 DDRB_DM[0..7] {5}
    3 4 DDRB_DQ4
    DDRB_DQ0 5 VSS2 DQ4 6 DDRB_DQ5
    DDRB_DQ1 7 DQ0 DQ5 8
    D 9 DQ1 VSS3 10 DDRB_DQS#0 D
    DDRB_DM0 11 VSS4 DQS0# 12 DDRB_DQS0
    13 DM0 DQS0 14
    DDRB_DQ2 15 VSS5 VSS6 16 DDRB_DQ6 +1.35V +1.35V
    DDRB_DQ3 17 DQ2 DQ6 18 DDRB_DQ7
    19 DQ3 DQ7 20
    VSS7 VSS8

    1
    DDRB_DQ8 21 22 DDRB_DQ12
    DDRB_DQ9 23 DQ8 DQ12 24 DDRB_DQ13 RD10 RD12
    25 DQ9 DQ13 26 +VREF_DQ 1K_0402_1% +VREF_CA
    VSS9 VSS10 1K_0402_1%
    DDRB_DQS#1 27 28 DDRB_DM1
    DDRB_DQS1 29 DQS1# DM1 30 MEM_MB_RST#
    MEM_MB_RST# {5} 15mil 15mil

    2
    31 DQS1 RESET# 32 R251 1 @ 2 0_0402_5%
    DDRB_DQ10 VSS11 VSS12 DDRB_DQ14 {5} APU_M_VREFDQ
    33 34
    DQ10 DQ14

    1
    CD120 0.1U_0201_6.3V6-K
    DDRB_DQ11 35 36 DDRB_DQ15 1
    DQ11 DQ15

    CD116 0.1U_0201_6.3V6-K

    CD118 0.1U_0201_6.3V6-K
    37 38 RD11 1 1 RD25 1 1
    DDRB_DQ16 39 VSS13 VSS14 40 DDRB_DQ20 1K_0402_1% CD117 1K_0402_1% CD119
    DDRB_DQ17 41 DQ16 DQ20 42 DDRB_DQ21 1000P_0201_50V7-K 1000P_0201_50V7-K
    43 DQ17 DQ21 44 2 @
    for MEM_MB_RST# overshoot issue

    2
    DDRB_DQS#2 45 VSS15 VSS16 46 DDRB_DM2 2 2 2 2
    DDRB_DQS2 47 DQS2# DM2 48
    49 DQS2 VSS17 50 DDRB_DQ22
    DDRB_DQ18 51 VSS18 DQ22 52 DDRB_DQ23
    DDRB_DQ19 53 DQ18 DQ23 54
    55 DQ19 VSS19 56 DDRB_DQ28
    DDRB_DQ24 57 VSS20 DQ28 58 DDRB_DQ29

    a
    DDRB_DQ25 59 DQ24 DQ29 60
    61 DQ25 VSS21 62 DDRB_DQS#3
    DDRB_DM3 63 VSS22 DQS3# 64 DDRB_DQS3
    65 DM3 DQS3 66

    hu
    DDRB_DQ26 67 VSS23 VSS24 68 DDRB_DQ30
    DDRB_DQ27 69 DQ26 DQ30 70 DDRB_DQ31
    +1.35V DQ27 DQ31 +1.35V 3A@1.5V
    71 72
    C VSS25 VSS26 +1.35V C
    Layout Note:
    {5} DDRB_CKE0
    DDRB_CKE0 73
    75 CKE0 CKE1
    74
    76
    DDRB_CKE1
    DDRB_CKE1 {5} Place near DIMM1
    77 VDD1 VDD2 78 DDRB_MA15
    NC1 A15

    22P_0402_50V8-J
    DDRB_BS2# DDRB_MA14

    g.
    {5} DDRB_BS2# 79 80
    BA2 A14

    CD17 0.1U_0201_6.3V6-K

    CD20 0.1U_0201_6.3V6-K

    CD22 0.1U_0201_6.3V6-K

    CD21 0.1U_0201_6.3V6-K

    CD23 0.1U_0201_6.3V6-K

    CD58 0.1U_0201_6.3V6-K

    CD59 0.1U_0201_6.3V6-K

    CD60 0.1U_0201_6.3V6-K

    CD61 0.1U_0201_6.3V6-K
    81 82 1 1 1 CD19 1 1 1 1 1 1 1 1 1
    DDRB_MA12 83 VDD3 VDD4 84 DDRB_MA11
    DDRB_MA9 85 A12/BC# A11 86 DDRB_MA7 CD16 CD18
    87 A9 A7 88
    VDD5 VDD6 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    DDRB_MA8 89 90 DDRB_MA6 2 2 @ 2 @ 2 2 2 2 @ 2 @ 2 @ 2 2 @ 2 @
    DDRB_MA5 91 A8 A6 92 DDRB_MA4 RF@
    93 A5 A4 94
    DDRB_MA3 95 VDD7 VDD8 96 DDRB_MA2
    A3 A2

    an
    DDRB_MA1 97 98 DDRB_MA0
    99 A1 A0 100
    DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1 +1.35V
    {5} DDRB_CLK0 CK0 CK1 DDRB_CLK1 {5}
    DDRB_CLK0# 103 104 DDRB_CLK1#
    {5} DDRB_CLK0# CK0# CK1# DDRB_CLK1# {5}
    105 106
    DDRB_MA10 107 VDD11 VDD12 108 DDRB_BS1#
    DDRB_BS0# A10/AP BA1 DDRB_RAS# DDRB_BS1# {5}
    {5} DDRB_BS0# 109 110
    BA0 RAS# DDRB_RAS# {5}

    CD12 22P_0402_50V8-J

    CD122 22P_0402_50V8-J
    22U_0805_6.3V6M

    22U_0603_6.3V6-M
    111 112
    VDD13 VDD14

    10U_0805_10V6K

    10U_0805_10V6K

    CD5

    CD6

    CD7

    CD11 22P_0402_50V8-J

    CD121 22P_0402_50V8-J
    DDRB_WE# 113 114 DDRB_CS0#

    Hu
    {5} DDRB_WE# WE# S0# DDRB_CS0# {5} 1 1 1 1 1 1 1 1 1 1 1
    DDRB_CAS# 115 116 DDRB_ODT0 CD62 CD63 CD66 CD67
    {5} DDRB_CAS# CAS# ODT0 DDRB_ODT0 {5}
    117 118
    VDD15 VDD16

    .047U_0201_6.3V6K

    .047U_0201_6.3V6K

    .047U_0201_6.3V6K
    DDRB_MA13 119 120 DDRB_ODT1 @ @ @ @
    A13 ODT1 DDRB_ODT1 {5} 2 2 2 2 2 2 2 2 2 2 2

    RF@

    RF@

    RF@

    RF@
    DDRB_CS1# 121 122
    {5} DDRB_CS1# S1# NC2 +VREF_CA
    123 124
    125 VDD17 VDD18 126
    127 TEST VREF_CA 128
    DDRB_DQ32 VSS27 VSS28 DDRB_DQ36
    RF
    129 130
    DDRB_DQ33 131 DQ32 DQ36 132 DDRB_DQ37
    B 133 DQ33 DQ37 134 B
    DDRB_DQS#4 135 VSS29 VSS30 136 DDRB_DM4
    DDRB_DQS4 137 DQS4# DM4 138
    139 DQS4 VSS31 140 DDRB_DQ38
    r
    DDRB_DQ34 141 VSS32 DQ38 142 DDRB_DQ39
    DDRB_DQ35 143 DQ34 DQ39 144
    145 DQ35 VSS33 146 DDRB_DQ44
    DDRB_DQ40 147 VSS34 DQ44 148 DDRB_DQ45
    Layout Note:
    Fo
    DDRB_DQ41 149 DQ40 DQ45 150
    DQ41 VSS35
    DDRB_DM5
    151
    153 VSS36 DQS5#
    152
    154
    DDRB_DQS#5
    DDRB_DQS5
    +0.675VS
    Place near DIMM1
    155 DM5 DQS5 156
    DDRB_DQ42 157 VSS37 VSS38 158 DDRB_DQ46
    DDRB_DQ43 159 DQ42 DQ46 160 DDRB_DQ47
    DQ43 DQ47

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    4.7U_0603_6.3V6K

    CD123 22P_0402_50V8-J
    161 162
    DDRB_DQ48 163 VSS39 VSS40 164 DDRB_DQ52
    DQ48 DQ52 1 1 1 1 1
    DDRB_DQ49 165 166 DDRB_DQ53 CD24 CD25 CD26 CD27
    167 DQ49 DQ53 168
    DDRB_DQS#6 169 VSS41 VSS42 170 DDRB_DM6 @ @
    DQS6# DM6 2 2 2 2 2

    RF@
    DDRB_DQS6 171 172
    173 DQS6 VSS43 174 DDRB_DQ54
    DDRB_DQ50 175 VSS44 DQ54 176 DDRB_DQ55
    DDRB_DQ51 177 DQ50 DQ55 178
    179 DQ51 VSS45 180 DDRB_DQ60
    DDRB_DQ56 181 VSS46 DQ60 182 DDRB_DQ61
    DDRB_DQ57 183 DQ56 DQ61 184
    185 DQ57 VSS47 186 DDRB_DQS#7
    DDRB_DM7 187 VSS48 DQS7# 188 DDRB_DQS7
    189 DM7 DQS7 190
    DDRB_DQ58 191 VSS49 VSS50 192 DDRB_DQ62
    DDRB_DQ59 193 DQ58 DQ62 194 DDRB_DQ63
    195 DQ59 DQ63 196
    A 197 VSS51 VSS52 198 MEM_MB_EVENT# A
    SA0 EVENT# MEM_MB_EVENT# {5}
    199 200 APU_SMB_DATA
    +3VS VDDSPD SDA APU_SMB_CLK APU_SMB_DATA {7,31}
    201 202
    SA1 SCL APU_SMB_CLK {7,31}
    CD29 0.1U_0201_6.3V6-K

    1 1 203 204 +0.675VS


    VTT1 VTT2
    CD28 205 206 1 0.65A@0.75V Title
    2.2U_0402_6.3V6M 207 GND1 GND2 208 Security Classification LC Future Center Secret Data
    2 2 BOSS1 BOSS2 CD70
    22P_0402_50V8-J
    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM A
    SIVCD@ LCN_DAN06-K4406-0103 2 RF@
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    ME@ Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    RF DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 12 of 50

    5 4 3 2 1
    5 4 3 2 1

    D D

    a
    C C

    hu
    g.
    an
    Hu
    B B

    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DDRIII SO-DIMM B
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 13 of 50
    5 4 3 2 1
    5 4 3 2 1

    Power-Up/Down Sequence
    "Topaz" has the following requirements with regards to power-supply sequencing to
    avoid damaging the ASIC:
    D D
    All the ASIC supplies must reach their respective nominal voltages within 20 ms
    of the start of the ramp-up sequence, though a shorter ramp-up duration is
    preferred. The maximum slew rate on all rails is 50 mV/μs. VRAM ID config
    It is recommended that the 3.3-V rail ramp up first.
    The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μs Memory Type
    VRAM ID PU resistor PD resistor
    before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
    The power rails that are shared with other components on the system should be
    gated for the dGPU so that when the dGPU is powered down (for example
    NA 100 4.53K 4.99K
    AMD PowerXpress idle state), all the power rails are removed from the dGPU.
    The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μs).
    For power down, reversing the ramp-up sequence is recommended. 128Mx16
    NA 111 4.75K NC

    NA 110 3.4K 10K


    0 ~ 20ms
    Hynix

    a
    VDDR3(+3VGS) H5TC4G63CFR-N0C 4Gb 900(1G)
    000 NC 4.75K
    0 ~ 20ms
    C C
    Micron

    hu
    VDD_CT(+1.8VGS) 256Mx16
    MT41J256M16LY-091G:N 4Gb 900(1G)
    010 4.53K 2K

    Samsung
    PCIE_VDDC(+0.95VGS) K4W4G1646E-BC1A 4Gb 900(1G)
    001 8.45K 2K

    10us min.

    g.
    VDDR1(+1.35VGS)

    VDDC/VDDCI(+VGA_CORE) 100ms min.

    an
    PERSTb(GPU_RST#) 100us min.

    REFCLK(CLK_PCIE_VGA)

    Hu
    B B

    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 14 of 50
    5 4 3 2 1
    5 4 3 2 1

    PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0]
    {4} PCIE_CTX_C_GRX_P[3..0] PCIE_CRX_GTX_P[3..0] {4}
    UV1A
    PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0]
    {4} PCIE_CTX_C_GRX_N[3..0] PCIE_CRX_GTX_N[3..0] {4}

    PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 CV1 CZLPX@1 PCIE_CRX_GTX_P0


    2 0.1U_0201_6.3V6-K
    PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 CV2 CZLPX@1 PCIE_CRX_GTX_N0
    2 0.1U_0201_6.3V6-K
    PCIE_RX0N PCIE_TX0N
    D D
    PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 CV3 CZLPX@1 PCIE_CRX_GTX_P1
    2 0.1U_0201_6.3V6-K
    PCIE_CTX_C_GRX_N1 AD28 PCIE_RX1P PCIE_TX1P AF28 PCIE_CRX_C_GTX_N1 CV4 CZLPX@1 PCIE_CRX_GTX_N1
    2 0.1U_0201_6.3V6-K
    PCIE_RX1N PCIE_TX1N

    PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 CV5 CZLPX@1 PCIE_CRX_GTX_P2


    2 0.1U_0201_6.3V6-K
    PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 CV6 CZLPX@1 PCIE_CRX_GTX_N2
    2 0.1U_0201_6.3V6-K
    PCIE_RX2N PCIE_TX2N

    PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 CV7 CZLPX@1 PCIE_CRX_GTX_P3


    2 0.1U_0201_6.3V6-K
    PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 CV8 CZLPX@1 PCIE_CRX_GTX_N3
    2 0.1U_0201_6.3V6-K
    PCIE_RX3N PCIE_TX3N

    AB30 AC25
    AA31 PCIE_RX4P PCIE_TX4P AB25
    PCIE_RX4N PCIE_TX4N

    AA29 Y23
    Y28 PCIE_RX5P PCIE_TX5P Y24
    PCIE_RX5N PCIE_TX5N

    a
    Y30 AB27
    W31 PCIE_RX6P PCIE_TX6P AB26
    PCIE_RX6N PCIE_TX6N

    hu
    W29 Y27
    V28 PCIE_RX7P PCIE_TX7P Y26
    PCIE_RX7N PCIE_TX7N
    C C

    V30 W24
    U31 NC#V30 NC#W24 W23
    NC#U31 NC#W23

    g.
    U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
    T28 NC#U29 NC#V27 U26
    NC#T28 NC#U26

    PCI EXPRESS INTERFACE


    T30 U24
    R31 NC#T30 NC#U24 U23
    NC#R31 NC#U23

    an
    R29 T26
    P28 NC#R29 NC#T26 T27
    NC#P28 NC#T27

    P30
    NC#P30 NC#T24
    T24 change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
    N31 T23
    NC#N31 NC#T23

    Hu
    N29
    NC#N29 NC#P27
    P27 11/4 change to PC sample SA000074V10
    M28 P26
    NC#M28 NC#P26

    M30 P24
    L31 NC#M30 NC#P24 P23
    B NC#L31 NC#P23 B

    L29 M27
    NC#L29 NC#M27
    r
    K30 N26
    NC#K30 NC#N26
    Fo
    CLOCK
    CLK_PCIE_GPU AK30
    {8} CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
    AK32
    {8} CLK_PCIE_GPU# PCIE_REFCLKN
    +0.95VGS
    CALIBRATION
    Y22 RV3 1 PX@ 2 1.69K_0402_1%
    PCIE_CALR_TX
    1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
    TEST_PG PCIE_CALR_RX

    GPU_RST# AL27
    {16} GPU_RST# PERSTB
    1

    AMD R16M-M1-30 DV3 PX@


    RV7 1 @ 2 0_0402_5% RV6 EXO@ GPU_RST# 2
    100K_0402_5% 1 VGA_PWROK
    VR_VGA_PWRGD VGA_PWROK {48}
    +3VGS PX@ 3
    {7,48} VR_VGA_PWRGD
    2

    BAT54AWT1G_SOT323-3
    5

    A A
    UV2
    VCC

    1
    {7,8} PXS_RST# IN1 GPU_RST#
    4
    2 OUT
    Title
    GND

    {7,28,31} PLT_RST# IN2 Security Classification LC Future Center Secret Data


    MC74VHC1G08DFT2G_SC70-5 Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_PCIE
    3

    PX@
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 15 of 50
    5 4 3 2 1
    5 4 3 2 1
    RECOMMENDED SETTINGS
    CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
    1 = INSTALL 10K RESISTOR
    UV1B ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
    GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

    AF2
    NC#AF2 RECOMMENDED
    NC#AF4
    AF4 MLPS Bit Strap Name Description
    SETTINGS
    N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
    L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
    AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
    DBG_DATA14 DPA
    Y11 AH3 100 = 256MB
    AE8 DBG_DATA13 NC#AH3 AH1
    AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
    AC10 DBG_DATA11 AK3
    AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
    AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. X
    DVO
    AC7 DBG_DATA8 AK5
    AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
    AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 0= Not support X
    AB7 DBG_DATA5 AK6
    AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
    AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
    DPB
    Y8 DBG_DATA2 AJ7
    D
    Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0 D
    DBG_DATA0 NC#AH6
    AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
    NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
    NC#AL7
    0 = Tx deemphasis disabled.
    W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
    V6 NC#W6
    NC#V6 V4 PS_2[1] N/A Reserved. NA
    AC6 NC#V4 U5
    AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. NA
    NC#AC5
    Reserve NC#W3
    W3 VGA_VSSI_SEN 1 TV10 PAD @
    AA5 V2 0 = Disable the external BIOS ROM device.
    AA6 NC#AA5 NC#V2 PS_2[3] STRAP_BIOS_ROM_EN 1 = Enable the external BIOS ROM device. 0= Disable X
    DPC
    +3VGS +1.8VGS NC#AA6 Y4
    NC#Y4 W5 0 = VGA controller capacity enabled.
    NC#W5 PS_2[4] STRAP_BIF_VGA_DIS 1 = The device will not be recognized as the system’s VGA 0
    10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
    10K_0402_5% 1 @ 2 RV1011 GPU_GPIO17 4.7K_0402_5% TV11 @ 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2 16.2K_0402_1% PS_2[5] N/A Reserved NA
    RV95 1 2 TOPAZ@ PAD BP_1 U3 NC#W1 NC#Y2
    4.7K_0402_5% Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
    NC#Y6 NC#J8 Reserve for Topaz
    10K_0402_5% 1 @ 2 RV9 GPU_GPIO0 TV12 @ 1 PLL_ANALOG_IN AA1 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
    10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
    10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G
    10K_0402_5% 1 @ 2 RV14 GPU_GPIO10
    10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 Determines the maximum number of digital display audio endpoints
    10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 I2C that will be presented to the OS and user.(Combine with PS_0[5])
    10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 111 = No usable endpoints.
    10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 R1 AUD_PORT_CONN_ 110 = One usable endpoint.
    10K_0402_5% 1 @ 2 RV97 GPU_VID1 R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
    10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 SDA TOPAZ@ 100 = Three usable endpoints. X
    10K_0402_5% 1 @ 2 RV99 GPU_VID5 AM26 DIECRACKMON RV120 1 2 PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
    10K_0402_5% 1 @ 2 RV106 GPU_VID2 NC_R AK26 10K_0402_5% PINSTRAP[2] 010 = Five usable endpoints.
    GPU_GPIO0 NC_AVSSN#AK26 001 = Six usable endpoints.
    U6 GENERAL PURPOSE I/O
    000 = All endpoints are usable.
    GPIO_0
    Reserve U10 +VGA_CORE_GPIO1
    NC_GPIO_1 NC_G
    AL25
    T10 +VGA_CORE_GPIO2 AJ25
    LRB751V-40T1G_SOD323-2 U8 VGA_SMB_DATA NC_GPIO_2 NC_AVSSN#AJ25
    U7 VGA_SMB_CLK SMBDATA AH24
    DV1

    a
    +VGA_CORE 1 2 @ T9 GPU_GPIO5 SMBCLK NC_B AG25 +1.8VGS +1.8VGS
    {35} VGA_AC_DET GPU_VID5 GPIO_5_AC_BATT NC_AVSSN#AG25
    T8
    RV100 1 2 0_0402_5% +VGA_CORE_GPIO1 T7 GPIO_6 DAC1 AH26
    NC_GPIO_7 NC_HSYNC

    1
    TOPAZ@ GPU_VR_HOT# RV104 1 @ 2 0_0402_5% GPU_GPIO8 P10 AJ27 4.7K_0402_5% 1 TOPAZ@2 RV22
    RV101 1 2 0_0402_5% +VGA_CORE_GPIO2 GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC RV71 RV74
    TOPAZ@ GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
    GPIO_10_ROMSCK

    hu
    RV102 1 2 0_0402_5% +VGA_CORE_GPIO14 GPU_GPIO11 N6 AD22 Pull down for none OBFF design PX@ STNPX@
    TOPAZ@ @ PAD TV3 1 GPU_GPIO12 N5 NC_GPIO_11 NC_RSET

    2
    RV108 1 2 0_0402_5% +VGA_CORE_GPIO18 GPU_GPIO13 N3 NC_GPIO_12 AG24 PS_0 PS_1
    TOPAZ@ +VGA_CORE_GPIO14 Y9 NC_GPIO_13 NC_AVDD AE22
    NC_GPIO_14 NC_AVSSQ

    1
    CV15

    CV16
    GPU_SVD 0_0402_5% 1 EXO@2 RV103 GPU_VID3 N1 1 1
    10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 GPIO_15_PWRCNTL_0 AE23 RV77 RV80
    C C
    0_0402_5% 1 PX@ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% 4.75K_0402_1%
    {48} GPU_VR_HOT# +VGA_CORE_GPIO18 W10 GPIO_17_THERMAL_INT NC_VSS1DI PX@ @ CZLPX@ @
    PX@ 2 RV68 NC_GPIO_18 2 2

    0.01U_0201_6.3V7-K

    0.01U_0201_6.3V7-K
    10K_0402_5% 1 GPIO_19_CTF M2 FutureASIC/SEYMOUR/PARK

    2
    GPU_SVC 0_0402_5% 1 EXO@2 RV105 GPU_VID4 P8 GPIO_19_CTF AM12 CEC_1 1 @ TV5
    GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD
    GPU_GPIO22 N8 GPIO_21
    RV1012 GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
    GPU_VR_HOT# 0_0402_5% 1 GPIO_29 NC_SVI2#AK12 GPU_SVD {48}
    @ 2GPU_VID1 AM10 AL11 GPU_SVT_R RV109 1TOPAZ@ 2 0_0402_5%

    g.
    GPU_CLKREQ#_R GPIO_30 NC_SVI2#AL11 GPU_SVC_R GPU_SVT {48}
    0_0402_5% 1 @ 2 RV124 N7 AJ11 RV111 1TOPAZ@ 2 0_0402_5%
    {7} GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC {48}

    1
    JTAG_TRSTB L6 RV60 RV63
    +3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
    JTAG_TCK L3 JTAG_TDI @ @
    PAD JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1 TV1 PAD @

    2
    10K_0402_5% 1 @ 2 RV72 JTAG_TRSTB TV7 @ 1JTAG_TDO K4 JTAG_TMS NC_GENLK_CLK AJ13 GENLK_VSYNC 1 TV2 PAD @ PS_2 PS_3
    10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
    TESTEN

    1
    CV18

    CV19
    10K_0402_5% 1 @ 2 RV78 JTAG_TMS 1K_0402_5% AF24 1 1
    NC#AF24

    0.01U_0201_6.3V7-K

    0.01U_0201_6.3V7-K
    AG13 RV69 RV70
    10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% 2K_0402_1%
    0_0402_5% 1 2 RV112 AB13 NC_SWAPLOCKB PX@ @ @ @
    +VGA_CORE NC_GENERICA 2 2
    TOPAZ@ W8

    an 2

    2
    0_0402_5% 1 2 RV113 W9 NC_GENERICB
    TOPAZ@ W7 NC_GENERICC AC19 PS_0
    0_0402_5% 1 2 RV114 AD10 NC_GENERICD PS_0
    TOPAZ@ AJ9 NC_GENERICE_HPD4 AD19 PS_1
    AL9 NC#AJ9 PS_1
    DBG_CNTL0 PS_2
    Bit BOM
    AE17 MLPS
    PS_2
    PX_EN
    AC14
    NC_HPD1 PS_3
    5 4 3 2 1 R_pu(　) R_pd(　) C(nF)
    PAD TV6 @ 1 AB16 AE20
    PX_EN PS_3
    PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
    4.7K_0402_5% 1 @ 2RV54
    PX@ 2 1 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 0 RV74=NC RV77=4.75K CV16=NC
    AC16 TS_A
    8P_0402_50V8-D NC_DBG_VREFG
    PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC

    Hu
    PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=X76
    DDC/AUX
    2

    AE6
    27MHZ_10PF_7V27000050

    NC_DDC1CLK
    YV1 PLL/CLOCK AE5 with BOM strcture control, R_pu (Ω) R_pd (Ω) Bits [3:1]
    GND1

    OSC1

    PX@ NC_DDC1DATA
    RV63,RV70 change to different value to
    1

    AD2 +VGA_CORE NC 4750 000


    RV46 NC_AUX1P AD4
    1
    adjust VRAM config
    1M_0402_5% NC_AUX1N RV24 8450 2000 001
    with BOM strcture control,
    GND2
    OSC2

    PX@ AC11 RV115 1 TOPAZ@2 0_0402_5% when config PEG3


    NC_DDC2CLK AC13 RV116 1 2 0_0402_5% 0_0402_5% 4530 2000 010
    RV74 change to 8.45K,
    2

    NC_DDC2DATA TOPAZ@ EXO@


    2

    XTALIN AM28 AD13 RV80 change to 2K 6980 4990 011


    3

    XTALOUT AK28 XTALIN NC_AUX2P AD11


    XTALOUT NC_AUX2N
    B XO_IN VGA_VSS_SEN_R
    Capacitor Value (nF) Bits [5:4] 4530 4990 100
    B
    10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@2 0_0402_5%
    XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN {48}
    10K_0402_5% 1 PX@ 2 RV50 AB22 AC20 RV126 1 2 0_0402_5% 680 00 3240 5620 101
    XO_IN2 NC#AC20 VGA_CORE_SEN {48}
    TOPAZ@
    PX@ 2 1 CV32 XTALOUT AE16 82 01 3400 10000 110
    NC#AE16 AD16
    r
    8P_0402_50V8-D NC#AD16 10 10 4750 NC 111
    1

    SEYMOUR/FutureASIC AC1
    NC_DDCVGACLK
    no symbol for 8pf cap, PLM has PN,change the PN PAD TV13@ 1 GPU_DPLUS
    GPU_DMINUS
    T4
    DPLUS THERMAL NC_DDCVGADATA
    AC3 RV23 NC 11 Note: 0402 1% resistors are required.
    PAD TV14@ 1 T2
    DMINUS 0_0402_5%
    EXO@ +3VGS +VDDIO_GPU
    2

    RV41 1 @ 2 GPIO_28_FDO R5
    Fo
    +3VGS GPIO28_FDO
    10K_0402_5% +1.8VGS LV3 1 2 PX@ +TSVDD AD17
    TSVDD SVC SVD Output Voltage (V) RV234 1 2 EXO@
    PBY100505T-121Y-N_2P AC17 +1.8VGS 0_0402_5%
    TSVSS +VGA_CORE
    CV21

    0 0 1.1
    1U_0402_6.3V6K
    2

    (1.8V@20mA TSVDD) 1 RV203 1 2 TOPAZ@


    RV42 0 1 1.0 0_0402_5%
    10K_0402_5% AMD R16M-M1-30
    EXO@ 2
    EXO@ For Topaz, RV16/RV19 stuff 100ohm 1 0 0.9
    PX@

    for EXO, RV16/RV19 stuff 0hm.


    1

    2
    1 1 0.8
    RV205 RV204 RV209
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    Connect GPIO_28 to 10K pull @ PX@ @
    down to enable MLPS.

    1
    GPU_SVD
    GPU_SVC
    GPU_SVT
    RV242 2 @ 1 0_0402_5% WRST# {35}

    2
    2
    RV206 RV210
    RV243 2 @ 1 0_0402_5% 10K_0402_5% RV207 10K_0402_5%
    APU_SHUTDOWN# {7}
    PX@ 10K_0402_5% @
    @

    1
    1
    1
    C

    @ QV13
    GPU_RST# 1 2 DV2 RV135 1 @ 2 0_0402_5% RV128 1 @ 2 2 B LMBT3904WT1G_SOT323-3 Internal VGA Thermal Sensor 
    {15} GPU_RST#
    2.2K_0402_5%
    SDM10U45LP-7_DFN1006-2-2
    1

    +3VGS
    CV215 0.1U_0201_6.3V6-K

    1 @
    RV131 +3VGS
    3

    GPIO_19_CTF 1 @ 2 RV132 1K_0402_5%


    47K_0402_5% @
    1

    2
    @

    A A
    2

    RV43 RV44
    2

    47K_0402_5% 47K_0402_5%
    G

    PX@ PX@ QV4A


    2

    VGA_SMB_CLK 1 6
    S

    EC_SMB_CK2 {6,30,35}
    D

    L2N7002KDW1T1G_SOT363-6
    G

    PX@ QV4B

    VGA_SMB_DATA 4 3
    S

    EC_SMB_DA2 {6,30,35}
    D

    L2N7002KDW1T1G_SOT363-6
    PX@
    Security Classification LC Future Center Secret Data Title
    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Main_MSIC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 16 of 50
    5 4 3 2 1
    5 4 3 2 1

    UV1F
    +VGA_CORE

    D D
    AB11 RV117 1 2 0_0402_5% TOPAZ@
    NC_VARY_BL AB12 RV119 1 2 0_0402_5% TOPAZ@
    NC_DIGON

    AL15
    NC_UPHYAB_TMDPA_TX0N AK14
    NC_UPHYAB_TMDPA_TX0P
    AH16
    NC_UPHYAB_TMDPA_TX1N AJ15
    NC_UPHYAB_TMDPA_TX1P
    AL17
    NC_UPHYAB_TMDPA_TX2N AK16
    NC_UPHYAB_TMDPA_TX2P
    AH18
    NC_UPHYAB_TMDPA_TX3N AJ17
    NC_UPHYAB_TMDPA_TX3P
    AL19
    NC_TXOUT_L3P AK18
    NC_TXOUT_L3N
    C C
    TMDP

    a
    AH20
    NC_UPHYAB_TMDPB_TX0N AJ19
    NC_UPHYAB_TMDPB_TX0P
    AL21
    NC_UPHYAB_TMDPB_TX1N

    hu
    AK20
    NC_UPHYAB_TMDPB_TX1P
    AH22
    NC_UPHYAB_TMDPB_TX2N AJ21
    NC_UPHYAB_TMDPB_TX2P
    AL23
    NC_UPHYAB_TMDPB_TX3N AK22
    NC_UPHYAB_TMDPB_TX3P

    g.
    AK24
    NC_TXOUT_U3P AJ23
    NC_TXOUT_U3N

    AMD R16M-M1-30
    B EXO@ B

    an
    Hu
    r
    A A
    Fo
    Security Classification LC Future Center Secret Data Title
    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_TMDP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 17 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.8VGS (1.8V@425mA DP_VDDR)


    RV48 1 2 0_0603_5% +DP_VDDR
    UV1G UV1E

    PX@

    PX@
    PX@

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    DP POWER NC/DP POWER
    1 1
    AG15 AE11 AA27 A3
    AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
    D D
    AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
    2 2 NC_DP_VDDR#AF16 NC#AE13 GND_3 GND_67

    CV39

    CV40
    AG17 AF13 AC24 AA16
    AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
    AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
    AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
    DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
    AE27 GND_8 GND_72 AD6
    +0.95VGS GND_9 GND_73
    (0.95V@560mA DP_VDDC) AF32
    GND_10 GND_74
    AD8
    AG27 AE7
    RV47 1 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
    NC_DP_VDDC#AG20 NC#AF6 GND_12 GND_76

    CV38
    AG21 AF7 K28 AH10
    AF22 NC_DP_VDDC#AG21 NC#AF7 AF8 K32 GND_13 GND_77 AH28
    PX@
    NC_DP_VDDC#AF22 NC#AF8 GND_14 GND_78

    CV37 0.1U_0201_6.3V6-K
    1U_0402_6.3V6K
    AG22 AF9 L27 B10
    AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
    1 1 DP_VDDC#AD14 GND_16 GND_80
    N25 B14
    N27 GND_17 GND_81 B16
    P25 GND_18 GND_82 B18
    2 2 AG14 AE1 P32 GND_19 GND_83 B20
    NC_DP_VSSR_1 NC#AE1 GND_20 GND_84
    PX@

    PX@
    AH14 AE3 R27 B22
    AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
    AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
    AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
    AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
    NC_DP_VSSR_6 NC#AF10 GND_25 GND_89

    a
    AG23 AG9 V32 C1
    C
    AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32 C
    AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28
    AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
    NC_DP_VSSR_10 NC#AM8 GND_29 GND_93

    hu
    AF19 AG7 Y25 F12
    AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
    AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
    DP_VSSR_13 GND_96 F18
    GND_97 F2
    GND_98 F20
    RV49 1 2 @ AF17 AE10 M6 GND_99 F22
    150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24

    g.
    N16 GND_33 GND_101 F26
    N18 GND_34 GND_102 F6
    AMD R16M-M1-30 N21 GND_35 GND
    GND_103 F8
    EXO@ P6 GND_36 GND_104 G10
    P9 GND_37 GND_105 G27
    R12 GND_38 GND_106 G31
    R15 GND_39 GND_107 G8
    R17 GND_40 GND_108 H14

    an
    R20 GND_41 GND_109 H17
    T13 GND_42 GND_110 H2
    T16 GND_43 GND_111 H20
    T18 GND_44 GND_112 H6
    T21 GND_45 GND_113 J27
    T6 GND_46 GND_114 J31
    B B
    U15 GND_47 GND_115 K11
    U17 GND_48 GND_116 K2

    Hu
    U20 GND_49 GND_117 K22
    U9 GND_50 GND_118 K6
    V13 GND_51 GND_119
    V16 GND_52
    V18 GND_53
    Y10 GND_54
    Y15 GND_55
    Y17 GND_56
    Y20 GND_57
    R11 GND_58 A32
    T11 GND_59 VSS_MECH_1 AM1
    GND_60 VSS_MECH_2
    r
    AA11 AM32
    M12 GND_61 VSS_MECH_3
    N11 GND_62
    V11 GND_63
    GND_64
    Fo
    AMD R16M-M1-30
    EXO@

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_DP Power
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 18 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.35VGS
    For DDR3/GDDR5, 1500mA@1.5V

    CV48

    CV51

    CV52

    CV53

    CV54

    CV55
    10U_0603_6.3V6M

    CV56 0.1U_0201_6.3V6-K
    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M
    1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
    (1.8V@100mA PCIE_PVDD)
    CV501 CV217 AM30
    PCIE_PVDD

    PCIE
    MEM I/O

    CV46

    CV47
    33P_0402_50V8J 0.01U_0201_6.3V7-K
    2 2 2 2 2 2 2 2 2

    10U_0603_6.3V6M
    1U_0402_6.3V6K
    RF_PXNS@ PX@ H13 AB23
    VDDR1_1 NC#AB23

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    H16 AC23 1 1
    H19 VDDR1_2 NC#AC23 AD24
    RF VDDR1_3 NC#AD24
    J10 AE24
    J23 VDDR1_4 NC#AE24 AE25
    VDDR1_5 NC#AE25

    PX@

    PX@
    J24 AE26 2 2
    J9 VDDR1_6 NC#AE26 AF25
    K10 VDDR1_7 NC#AF25 AG26
    VDDR1_8 NC#AG26
    +1.8VGS (1.8V@13mA VDD_CT) +VDD_CT K23
    VDDR1_9
    +0.95VGS
    K24
    VDDR1_10 (0.95V@2500mA PCIE_VDDC)
    D LV7 1 @ 2 0_0402_5% K9 L23 D
    VDDR1_11 PCIE_VDDC_1

    CV144
    L11 L24
    VDDR1_12 PCIE_VDDC_2

    CV64

    CV65

    CV66

    CV67

    CV68

    CV69

    CV71
    1U_0402_6.3V6K
    L12 L25
    VDDR1_13 PCIE_VDDC_3

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    1 L13 L26
    L20 VDDR1_14 PCIE_VDDC_4 M22
    VDDR1_15 PCIE_VDDC_5 1 1 1 1 1 1 1 1
    L21 N22
    L22 VDDR1_16 PCIE_VDDC_6 N23 CV502
    VDDR1_17 PCIE_VDDC_7

    PX@
    2 N24 33P_0402_50V8J
    PCIE_VDDC_8

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    R22 2 2 2 2 2 2 2 2 RF_PXNS@
    PCIE_VDDC_9 T22
    LEVEL PCIE_VDDC_10 RF
    U22
    TRANSLATION PCIE_VDDC_11 V22
    AA20 PCIE_VDDC_12 +VGA_CORE
    AA21 VDD_CT_1
    AB20 VDD_CT_2 AA15
    VDD_CT_3 CORE VDDC_1
    +3VGS (3.3V@25mA VDDR3) AB21
    VDD_CT_4 VDDC_2
    N15

    CV141

    CV143

    CV146

    CV148

    CV150

    CV152

    CV159

    CV133

    CV137

    CV151
    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M
    CV73

    CV74

    CV75

    CV76

    CV77

    CV84
    N17
    LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13
    I/O VDDC_4

    CV149
    R16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    VDDC_5

    1U_0402_6.3V6K
    AA17 R18
    AA18 VDDR3_1 VDDC_6 Y21
    1 VDDR3_2 VDDC_7
    change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122) AB17
    VDDR3_3 VDDC_8
    T12

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    AB18 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    as DFC suggest, footprint with VDDR3_4 VDDC_9 T17
    MURAT_BLM15PD121SN1D_2P VDDC_10

    PX@
    2 V12 T20
    Y12 NC_VDDR4_1 VDDC_11 U13
    +1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
    NC_VDDR4_3 VDDC_13
    (1.8V@130mA MPLL_PVDD) VDDC_14
    U18
    PX@ V21
    LV4 1 2 +MPLL_PVDD VDDC_15 V15
    VDDC_16
    CV26

    CV34

    CV27

    CV139

    CV153

    CV156

    CV160

    CV134

    CV135
    BLM15AG221SN1 V17
    VDDC_17

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    V20
    VDDC_18
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    POWER
    1U_0402_6.3V6K

    a
    Y13 1 1 1 1 1 1 1
    VDDC_19
    CV24 0.1U_0201_6.3V6-K

    1 1 1 Y16
    VDDC_20 Y18 CV503
    1 VDDC_21 AA12 33P_0402_50V8J
    VDDC_22

    PX@

    PX@

    PX@
    2 2 2 2 2 2 2

    SIVCD@

    SIVCD@

    SIVCD@
    For EMC M11 RF_PX@
    2 2 2 VDDC_23 N12

    hu
    2 VDDC_24 U11
    VDDC_25
    PX@

    PX@

    PX@
    @

    RF
    PLL
    C +0.95VGS C
    (0.95V@1400mA BIF_VDDC)
    +1.8VGS R21
    BIF_VDDC_1
    (1.8V@75mA SPLL_PVDD) BIF_VDDC_2
    U21
    1
    LV5 1 2 PX@ +SPLL_PVDD +MPLL_PVDD L8 CV41
    MPLL_PVDD
    CV29

    CV30

    g.
    PBY100505T-121Y-N_2P +VGA_CORE 1U_0402_6.3V6K
    ISOLATED PX@
    2
    10U_0603_6.3V6M

    (GDDR3/DDR3 8.8A@1.12V VDDCI)


    1U_0402_6.3V6K

    CORE I/O
    CV28 0.1U_0201_6.3V6-K

    1 1 M13
    +SPLL_PVDD H7 VDDCI_1 M15
    1 SPLL_PVDD VDDCI_2 M16
    +0.95VGS VDDCI_3

    CV158

    CV132

    CV136

    CV138
    For EMC M17
    2 2 VDDCI_4

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    CV218 0.1U_0201_6.3V6-K

    CV219 0.1U_0201_6.3V6-K
    (0.95V@100mA SPLL_VDDC)

    CV220
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    M18
    2 PX@ VDDCI_5 M20 +VGA_CORE
    VDDCI_6 1 1 1 1 1 1 1 1
    PX@

    PX@
    @

    LV6 1 2 +SPLL_VDDC H8 M21


    SPLL_VDDC VDDCI_7
    CV35

    PBY100505T-121Y-N_2P N20 CV504


    VDDCI_8

    1
    J7 33P_0402_50V8J

    an
    SPLL_PVSS

    PX@

    PX@

    PX@

    PX@
    2 2 2 2 2 2 2 2
    CV36 0.1U_0201_6.3V6-K
    1U_0402_6.3V6K

    SIVCD@
    RF_PX@ RV166
    CV33 0.1U_0201_6.3V6-K

    PX@

    PX@
    1 1 470_0603_5%
    1 RF @
    AMD R16M-M1-30

    1 2
    For EMC EXO@
    2 2 QV19 D
    2
    PX@

    PXS_PWREN# 2
    PX@
    @

    S
    L2N7002KWT1G_SOT323-3

    3
    @

    Hu
    +3VS
    Need OPEN +3VGS
    +1.35V TO +1.35VGS +1.35V +1.35VGS
    +3.3VS TO +3VGS Need OPEN +/- 3% 6A
    JV1 1 2 @
    1 2 JV2 1 2 @
    1 2
    10U_0603_6.3V6M

    1U_0402_10V6K

    JUMP_43X39 CV140 CV142 CV214 CV210 CV211


    1

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    CV212 0.1U_0201_6.3V6-K
    330U_D2_2V_Y
    1 1 CV208 CV209 JUMP_43X118 1

    1
    RV51 1 1 AON6414AL_DFN8-5 1 1 1
    B 470_0603_5% + RV91 B
    S

    QV6 3 1 PX@ @ 1 470_0603_5%


    PX@

    PX@

    LP2301ALT1G_SOT23-3 2 2 2 @
    2

    PX@

    PX@

    PX@
    2 2 @2 2 2 2

    @
    5 3

    1 2
    PX@
    G
    2

    r
    1

    +5VALW D QV7 D QV10


    2 PXS_PWREN# 2 PXS_PWREN#
    V20B+ QV9 PX@

    4
    1 PX@ 2 RV52 PXS_PWREN# 1 PX@ 2 RV53 G G
    20K_0402_5% 20K_0402_5% PX@
    1 S
    L2N7002KWT1G_SOT323-3 1 2 RV92 S
    L2N7002KWT1G_SOT323-3
    3

    3
    499K_0402_1%
    Fo
    @ @
    1

    CV213 0.1U_0201_6.3V6-K
    QV8 CV145
    PXS_PWREN 2 0.1U_0201_6.3V6-K 1 1
    {7,48} PXS_PWREN
    1

    G 2 PX@ QV11 D RV118


    PXS_PWREN# 2 499K_0402_1%
    1

    S
    L2N7002KWT1G_SOT323-3 G PX@
    3

    RV1000 2
    PX@
    2

    PX@
    100K_0402_5% L2N7002KWT1G_SOT323-3
    3

    PX@
    PX@
    2

    +0.95VALW to +0.95VGS
    +1.8VALW to +1.8VGS AON7408L_DFN8-5
    +/- 1.5% +0.95VALW QV3 +0.95VGS AON4304
    +/- 3% 2A VDS=30V VGS=20V, ID=18A,
    +/- 2% +1.8VALW +1.8VGS Rds=6mohm @ VGS=10V
    QV2
    +/- 3% 0.5A S1
    1 10U_0603_6.3V6M VGS(th)=2.4V Max
    5 2 1 1 1
    AO3402_SOT-23-3 D S2
    10U_0603_6.3V6M

    1 3
    S3
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    PX@ 1 1 1 CV161 CV163 CV164 CV162


    G

    1 1 3 10U_0805_25V6K 1U_0603_25V6M
    CV165 D S CV170 CV168 CV166 PX@ 2 PX@ 2 PX@ 2 PX@
    4

    10U_0805_25V6K 1U_0603_25V6M 2
    PX@
    G

    @ 2 PX@ 2@ 2 PX@ +0.95VGS


    2
    2

    +1.8VGS

    1
    RV165
    1

    AON6414AL 470_0603_5%
    A AON6414AL VDS=30V VGS=20V, ID=50A, 2 R208 1 A
    RV171
    V20B+ @
    CV167 0.1U_0201_6.3V6-K

    VDS=30V VGS=20V, ID=50A, 470_0603_5% Rds=8mohm @ VGS=10V PX@ 150K_0402_5%

    1 2
    2 R195 1
    Rds=8mohm @ VGS=10V V20B+ @ VGS(th)=2.5V Max 1
    1

    VGS(th)=2.5V Max PX@100K_0402_5% D QV17 QV18 D


    1 2
    1
    CV169 0.1U_0201_6.3V6-K

    RV208 2 PXS_PWREN# 2
    1

    1 RV196 D QV15 QV16 D 120K_0402_5% G G


    120K_0402_5% 2 PXS_PWREN# 2 2 PX@
    G G S L2N7002KWT1G_SOT323-3 L2N7002KWT1G_SOT323-3 S
    PX@

    PX@
    2

    3
    PX@
    @
    2

    2 S
    L2N7002KWT1G_SOT323-3 S
    L2N7002KWT1G_SOT323-3
    3

    3
    PX@

    PX@ @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_Power


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 19 of 50
    5 4 3 2 1
    5 4 3 2 1

    UV1C
    FBA_D[63..0]
    FBA_D[63..0] {21,22} GDDR5/DDR3 GDDR5/DDR3
    FBA_D0 K27 K17 FBA_MA0
    FBA_MA[15..0] FBA_D1 J29 DQA0_0 MAA0_0/MAA_0 J20 FBA_MA1
    FBA_MA[15..0] {21,22} FBA_D2 DQA0_1 MAA0_1/MAA_1 FBA_MA2
    H30 H23
    FBA_BA[2..0] FBA_D3 H32 DQA0_2 MAA0_2/MAA_2 G23 FBA_MA3
    FBA_BA[2..0] {21,22} FBA_D4 DQA0_3 MAA0_3/MAA_3 FBA_MA4
    G29 G24
    FBA_D5 F28 DQA0_4 MAA0_4/MAA_4 H24 FBA_MA5
    FBA_D6 F32 DQA0_5 MAA0_5/MAA_5 J19 FBA_MA6
    D DQA0_6 MAA0_6/MAA_6 D
    FBA_D7 F30 K19 FBA_MA7
    FBA_D8 C30 DQA0_7 MAA0_7/MAA_7 G20 FBA_MA13
    FBA_D9 F27 DQA0_8 MAA0_8/MAA_13 L17 FBA_MA15
    FBA_D10 A28 DQA0_9 MAA0_9/MAA_15
    FBA_D11 C28 DQA0_10 J14 FBA_MA8
    FBA_D12 E27 DQA0_11 MAA1_0/MAA_8 K14 FBA_MA9
    FBA_D13 G26 DQA0_12 MAA1_1/MAA_9 J11 FBA_MA10
    FBA_D14 D26 DQA0_13 MAA1_2/MAA_10 J13 FBA_MA11
    FBA_D15 F25 DQA0_14 MAA1_3/MAA_11 H11 FBA_MA12
    FBA_D16 A25 DQA0_15 MAA1_4/MAA_12 G11 FBA_BA2
    FBA_D17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 FBA_BA0
    FBA_D18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 FBA_BA1
    FBA_D19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 FBA_MA14
    FBA_D20 E23 DQA0_19 MAA1_8/MAA_14 L16

    MEMORY INTERFACE
    FBA_D21 F23 DQA0_20 MAA1_9/RSVD
    FBA_D22 DQA0_21 FBA_DQM0 FBA_DQM[7..0] {21,22}
    D22 E32
    FBA_D23 F21 DQA0_22 WCKA0_0/DQMA0_0 E30 FBA_DQM1
    FBA_D24 E21 DQA0_23 WCKA0B_0/DQMA0_1 A21 FBA_DQM2
    FBA_D25 D20 DQA0_24 WCKA0_1/DQMA0_2 C21 FBA_DQM3
    FBA_D26 F19 DQA0_25 WCKA0B_1/DQMA0_3 E13 FBA_DQM4
    FBA_D27 A19 DQA0_26 WCKA1_0/DQMA1_0 D12 FBA_DQM5
    FBA_D28 D18 DQA0_27 WCKA1B_0/DQMA1_1 E3 FBA_DQM6
    FBA_D29 F17 DQA0_28 WCKA1_1/DQMA1_2 F4 FBA_DQM7
    FBA_D30 A17 DQA0_29 WCKA1B_1/DQMA1_3
    FBA_D31 DQA0_30 FBA_DQS0 FBA_DQS[7..0] {21,22}
    C17 H28
    FBA_D32 E17 DQA0_31 EDCA0_0/QSA0_0 C27 FBA_DQS1

    a
    FBA_D33 D16 DQA1_0 EDCA0_1/QSA0_1 A23 FBA_DQS2
    C DQA1_1 EDCA0_2/QSA0_2 C
    +1.35VGS FBA_D34 F15 E19 FBA_DQS3
    FBA_D35 A15 DQA1_2 EDCA0_3/QSA0_3 E15 FBA_DQS4
    FBA_D36 D14 DQA1_3 EDCA1_0/QSA1_0 D10 FBA_DQS5
    DQA1_4 EDCA1_1/QSA1_1

    hu
    1

    FBA_D37 F13 D6 FBA_DQS6


    RV61 FBA_D38 A13 DQA1_5 EDCA1_2/QSA1_2 G5 FBA_DQS7
    40.2_0402_1% FBA_D39 C13 DQA1_6 EDCA1_3/QSA1_3
    FBA_D40 DQA1_7 FBA_DQS#0 FBA_DQS#[7..0] {21,22}
    PX@ E11 H27
    FBA_D41 A11 DQA1_8 DDBIA0_0/QSA0_0B A27 FBA_DQS#1
    2

    +VDD_MEM15_REFDA FBA_D42 C11 DQA1_9 DDBIA0_1/QSA0_1B C23 FBA_DQS#2


    FBA_D43 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 FBA_DQS#3
    DQA1_11 DDBIA0_3/QSA0_3B
    1

    1 FBA_D44 A9 C15 FBA_DQS#4


    RV65 CV154 FBA_D45 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 FBA_DQS#5

    g.
    100_0402_1% 1U_0402_6.3V6K FBA_D46 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 FBA_DQS#6
    PX@ PX@ FBA_D47 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 FBA_DQS#7
    2 FBA_D48 E7 DQA1_15 DDBIA1_3/QSA1_3B
    2

    FBA_D49 A7 DQA1_16 L18 FBA_ODTA0


    FBA_D50 DQA1_17 ADBIA0/ODTA0 FBA_ODTA1 FBA_ODTA0 {21}
    C7 K16
    FBA_D51 DQA1_18 ADBIA1/ODTA1 FBA_ODTA1 {22}
    F7
    FBA_D52 A5 DQA1_19 H26 FBA_CLKA0
    FBA_D53 DQA1_20 CLKA0 FBA_CLKA0# FBA_CLKA0 {21}
    E5 H25
    DQA1_21 CLKA0B FBA_CLKA0# {21}

    an
    FBA_D54 C3
    FBA_D55 E1 DQA1_22 G9 FBA_CLKA1
    FBA_D56 DQA1_23 CLKA1 FBA_CLKA1# FBA_CLKA1 {22}
    G7 H9
    FBA_D57 DQA1_24 CLKA1B FBA_CLKA1# {22}
    +1.35VGS G6
    FBA_D58 G1 DQA1_25 G22 FBA_RASA0#
    FBA_D59 DQA1_26 RASA0B FBA_RASA1# FBA_RASA0# {21}
    G3 G17
    DQA1_27 RASA1B FBA_RASA1# {22}
    1

    B
    FBA_D60 J6 B
    RV62 FBA_D61 J1 DQA1_28 G19 FBA_CASA0#
    FBA_D62 DQA1_29 CASA0B FBA_CASA1# FBA_CASA0# {21}
    40.2_0402_1% J3 G16

    Hu
    FBA_D63 DQA1_30 CASA1B FBA_CASA1# {22}
    PX@ J5
    DQA1_31 H22 FBA_CSA0#
    FBA_CSA0# {21}
    2

    +VDD_MEM15_REFSA +VDD_MEM15_REFDA K26 CSA0B_0 J22


    +VDD_MEM15_REFSA J26 MVREFDA CSA0B_1
    MVREFSA
    1

    1 G13 FBA_CSA1#
    CSA1B_0 FBA_CSA1# {22}
    RV66 CV157 J25 K13
    100_0402_1% 1U_0402_6.3V6K RV55 1 2 PX@ K25 NC#J25 CSA1B_1
    PX@ PX@ 120_0402_1% MEM_CALRP0 K20 FBA_CKEA0
    2 CKEA0 FBA_CKEA1 FBA_CKEA0 {21}
    J17
    FBA_CKEA1 {22}
    2

    CKEA1
    G25 FBA_WEA0#
    WEA0B FBA_WEA1# FBA_WEA0# {21}
    DRAMRST L10 H10
    DRAM_RST WEA1B FBA_WEA1# {22}
    r
    PAD @ TV8 1 CLKTESTA K8
    PAD @ TV9 1 CLKTESTB L7 CLKTESTA
    CLKTESTB
    Fo
    AMD R16M-M1-30
    EXO@

    A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A


    FBA_RST# {21,22}
    10_0402_5% 51.1_0402_1%
    1

    RV58 1
    4.99K_0402_1% CV147
    PX@ 120P_0402_50V8-J
    Security Classification LC Future Center Secret Data Title
    PX@
    2

    2
    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_MEM IF
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 20 of 50
    5 4 3 2 1
    5 4 3 2 1

    FBA_MA[15..0] {20,22}

    FBA_BA[2..0] {20,22}

    FBA_DQS[3..0] {20}

    FBA_DQM[3..0] {20}

    Memory Partition A - Lower 32 bits FBA_DQS#[3..0]

    FBA_D[31..0]
    {20}

    {20}

    UV6
    D UV5 D
    +FBA_VREFC0_L M8 E3 FBA_D19
    +FBA_VREFC0_U M8 E3 FBA_D1 H1 VREFCA DQL0 F7 FBA_D16 +1.35VGS +1.35VGS
    H1 VREFCA DQL0 F7 FBA_D6 VREFDQ DQL1 F2 FBA_D23
    VREFDQ DQL1 F2 FBA_D2 FBA_MA0 N3 DQL2 F8 FBA_D21
    DQL2 A0 DQL3 Group2 (IN1)

    1
    FBA_MA0 N3 F8 FBA_D7 FBA_MA1 P7 H3 FBA_D22
    FBA_MA1 P7 A0 DQL3 H3 FBA_D0 FBA_MA2 P3 A1 DQL4 H8 FBA_D18 RV18 RV20
    FBA_MA2 A1 DQL4 FBA_D5
    Group0 (IN3) FBA_MA3 A2 DQL5 FBA_D20
    P3 H8 N2 G2 4.99K_0402_1% 4.99K_0402_1%
    FBA_MA3 N2 A2 DQL5 G2 FBA_D3 FBA_MA4 P8 A3 DQL6 H7 FBA_D17 PX@ PX@
    FBA_MA4 P8 A3 DQL6 H7 FBA_D4 FBA_MA5 P2 A4 DQL7

    2
    FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5 +FBA_VREFC0_U +FBA_VREFC0_L
    FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D9
    FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D10
    A7 DQU0 A8 DQU1

    1
    CV100 0.1U_0201_6.3V6-K

    CV101 0.1U_0201_6.3V6-K
    FBA_MA8 T8 C3 FBA_D27 FBA_MA9 R3 C8 FBA_D13 1 1
    FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D12 RV19 RV21
    FBA_MA10 A9 DQU2 FBA_D25 FBA_MA11 A10/AP DQU3 FBA_D8
    Group1 (TOP)
    L7 C2 R7 A7 4.99K_0402_1% 4.99K_0402_1%
    FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D14 PX@ PX@
    A11 DQU4 Group3 (BOT) A12/BC DQU5 2 2

    @
    FBA_MA12 N7 A2 FBA_D24 FBA_MA13 T3 B8 FBA_D15

    2
    FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D11
    FBA_MA14 T7 A13 DQU6 A3 FBA_D26 A14 DQU7
    A14 DQU7 +1.35VGS
    +1.35VGS
    FBA_BA0 M2 B2
    FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
    FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7
    FBA_BA2 M3 BA1 VDD_2 G7 BA2 VDD_3 K2
    BA2 VDD_3 VDD_4

    a
    K2 K8
    VDD_4 K8 VDD_5 N1
    VDD_5 N1 FBA_CLKA0 J7 VDD_6 N9
    FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1
    {20} FBA_CLKA0 FBA_CLKA0# CK VDD_7 FBA_CKEA0 CK VDD_8
    K7 R1 K9 R9

    hu
    {20} FBA_CLKA0# FBA_CKEA0 CK VDD_8 CKE VDD_9
    K9 R9
    {20} FBA_CKEA0 CKE VDD_9
    FBA_ODTA0 K1 A1
    FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8
    C {20} FBA_ODTA0 FBA_CSA0# ODT VDDQ_1 FBA_RASA0# CS VDDQ_2 C
    L2 A8 J3 C1
    {20} FBA_CSA0# FBA_RASA0# CS VDDQ_2 FBA_CASA0# RAS VDDQ_3
    J3 C1 K3 C9
    {20} FBA_RASA0# FBA_CASA0# RAS VDDQ_3 FBA_WEA0# CAS VDDQ_4
    K3 C9 L3 D2
    {20} FBA_CASA0# FBA_WEA0# CAS VDDQ_4 WE VDDQ_5
    L3 D2 E9
    {20} FBA_WEA0# WE VDDQ_5 VDDQ_6
    E9 F1
    VDDQ_6 VDDQ_7

    g.
    F1 FBA_DQS2 F3 H2
    FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS1 C7 DQSL VDDQ_8 H9
    FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
    DQSU VDDQ_9
    FBA_DQM2 E7 A9
    FBA_DQM0 E7 A9 FBA_DQM1 D3 DML VSS_1 B3
    FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1
    DMU VSS_2 E1 VSS_3 G8
    VSS_3 G8 FBA_DQS#2 G3 VSS_4 J2
    VSS_4 DQSL VSS_5

    an
    FBA_DQS#0 G3 J2 FBA_DQS#1 B7 J8
    FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
    DQSU VSS_6 M1 VSS_7 M9
    VSS_7 M9 VSS_8 P1
    VSS_8 P1 FBA_RST# T2 VSS_9 P9 FBA_CLKA0
    FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
    {20,22} FBA_RST# RESET VSS_10 VSS_11
    T1 L8 T9
    VSS_11 ZQ VSS_12

    1
    L8 T9
    ZQ VSS_12 RV26
    J1 B1 40.2_0402_1%

    Hu
    NC1 VSSQ_1
    1

    1
    J1 B1 L1 B9 PX@
    RV15 RV16 L1 NC1 VSSQ_1 B9 RV17 J9 NC2 VSSQ_2 D1

    2
    10K_0402_5% 243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% L9 NC3 VSSQ_3 D8 CV104
    @ PX@ L9 NC3 VSSQ_3 D8 PX@ FBA_MA15 M7 NC4 VSSQ_4 E2 1 2
    FBA_MA15 M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
    2

    NC5 VSSQ_5 E8 VSSQ_6 F9 PX@ .01U_0402_16V7-K


    VSSQ_6 VSSQ_7

    1
    F9 G1
    VSSQ_7 G1 VSSQ_8 G9 RV27
    VSSQ_8 G9 VSSQ_9 40.2_0402_1%
    VSSQ_9 96-BALL PX@
    B 96-BALL SDRAM DDR3 B

    2
    SDRAM DDR3 K4W4G1646B-HC11_FBGA96
    K4W4G1646B-HC11_FBGA96 FBA_CLKA0#
    r
    @
    @
    +1.35VGS UV5 SIDE +1.35VGS UV6 SIDE
    Fo
    CV78 CV79 CV80 CV81 CV82 CV83 CV89 CV90 CV91 CV92 CV93 CV94
    10U_0603_6.3V6M

    1U_0402_10V6K

    10U_0603_6.3V6M
    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K
    1 1 1 1 1 1 1 1 1 1 1 1
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    2 2 2 2 2 2 2 2 2 2 2 2

    +1.35VGS
    UV5 SIDE +1.35VGS UV6 SIDE
    CV155 0.1U_0201_6.3V6-K

    CV85 0.1U_0201_6.3V6-K

    CV86 0.1U_0201_6.3V6-K

    CV87 0.1U_0201_6.3V6-K

    CV88 0.1U_0201_6.3V6-K

    CV95 0.1U_0201_6.3V6-K

    CV96 0.1U_0201_6.3V6-K

    CV97 0.1U_0201_6.3V6-K

    CV98 0.1U_0201_6.3V6-K

    CV99 0.1U_0201_6.3V6-K

    1 1 1 1 1 1 1 1 1 1 1 1
    CV505
    33P_0402_50V8J CV506
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    RF_PXNS@ 33P_0402_50V8J
    2 2 2 2 2 2 2 2 2 2 2 2 RF_PXNS@

    RF RF
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_A


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 21 of 50
    5 4 3 2 1
    5 4 3 2 1

    FBA_MA[15..0] {20,21}

    FBA_BA[2..0] {20,21}

    FBA_DQS[7..4] {20}

    FBA_DQM[7..4] {20}
    Memory Partition A - Upper 32 bits FBA_DQS#[7..4] {20}

    FBA_D[63..32] {20}
    UV7 UV8

    +FBA_VREFC1_U M8 E3 FBA_D38 +FBA_VREFC1_L M8 E3 FBA_D56


    H1 VREFCA DQL0 F7 FBA_D35 H1 VREFCA DQL0 F7 FBA_D59
    D D
    VREFDQ DQL1 F2 FBA_D37 VREFDQ DQL1 F2 FBA_D57
    FBA_MA0 N3 DQL2 F8 FBA_D32 FBA_MA0 N3 DQL2 F8 FBA_D61 +1.35VGS +1.35VGS
    FBA_MA1 P7 A0 DQL3 H3 FBA_D36 FBA_MA1 P7 A0 DQL3 H3 FBA_D60
    FBA_MA2 A1 DQL4 FBA_D34
    Group4 (IN1) FBA_MA2 A1 DQL4 FBA_D62
    Group7 (IN3)
    P3 H8 P3 H8
    A2 DQL5 A2 DQL5

    1
    FBA_MA3 N2 G2 FBA_D39 FBA_MA3 N2 G2 FBA_D63 RV30
    FBA_MA4 P8 A3 DQL6 H7 FBA_D33 FBA_MA4 P8 A3 DQL6 H7 FBA_D58 RV32
    FBA_MA5 P2 A4 DQL7 FBA_MA5 P2 A4 DQL7 4.99K_0402_1% 4.99K_0402_1%
    FBA_MA6 R8 A5 FBA_MA6 R8 A5 PX@ PX@
    FBA_MA7 R2 A6 D7 FBA_D40 FBA_MA7 R2 A6 D7 FBA_D55

    2
    FBA_MA8 T8 A7 DQU0 C3 FBA_D45 FBA_MA8 T8 A7 DQU0 C3 FBA_D51 +FBA_VREFC1_U +FBA_VREFC1_L
    FBA_MA9 R3 A8 DQU1 C8 FBA_D43 FBA_MA9 R3 A8 DQU1 C8 FBA_D54
    FBA_MA10 L7 A9 DQU2 C2 FBA_D44 FBA_MA10 L7 A9 DQU2 C2 FBA_D48
    A10/AP DQU3 A10/AP DQU3

    1
    CV127 0.1U_0201_6.3V6-K

    CV128 0.1U_0201_6.3V6-K
    FBA_MA11 R7 A7 FBA_D42 Group5 (TOP) FBA_MA11 R7 A7 FBA_D52 Group6 (BOT) 1 1
    FBA_MA12 N7 A11 DQU4 A2 FBA_D46 FBA_MA12 N7 A11 DQU4 A2 FBA_D50 RV31 RV33
    FBA_MA13 T3 A12/BC DQU5 B8 FBA_D41 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D53 4.99K_0402_1% 4.99K_0402_1%
    FBA_MA14 T7 A13 DQU6 A3 FBA_D47 FBA_MA14 T7 A13 DQU6 A3 FBA_D49 PX@ PX@
    A14 DQU7 A14 DQU7 2 2

    PX@
    2

    2
    +1.35VGS +1.35VGS

    FBA_BA0 M2 B2 FBA_BA0 M2 B2
    FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA1 N8 BA0 VDD_1 D9
    FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA2 M3 BA1 VDD_2 G7
    BA2 VDD_3 K2 BA2 VDD_3 K2
    VDD_4 K8 VDD_4 K8
    VDD_5 N1 VDD_5 N1
    VDD_6 VDD_6

    a
    FBA_CLKA1 J7 N9 FBA_CLKA1 J7 N9
    {20} FBA_CLKA1 FBA_CLKA1# K7 CK VDD_7 FBA_CLKA1# CK VDD_7
    R1 K7 R1
    {20} FBA_CLKA1# FBA_CKEA1 K9 CK VDD_8 FBA_CKEA1 CK VDD_8
    R9 K9 R9
    {20} FBA_CKEA1 CKE VDD_9 CKE VDD_9

    hu
    FBA_ODTA1 K1 A1 FBA_ODTA1 K1 A1
    {20} FBA_ODTA1 FBA_CSA1# ODT VDDQ_1 FBA_CSA1# ODT VDDQ_1
    L2 A8 L2 A8
    {20} FBA_CSA1# FBA_RASA1# CS VDDQ_2 FBA_RASA1# CS VDDQ_2
    J3 C1 J3 C1
    {20} FBA_RASA1# FBA_CASA1# RAS VDDQ_3 FBA_CASA1# RAS VDDQ_3
    K3 C9 K3 C9
    C {20} FBA_CASA1# FBA_WEA1# CAS VDDQ_4 FBA_WEA1# CAS VDDQ_4 C
    L3 D2 L3 D2
    {20} FBA_WEA1# WE VDDQ_5 WE VDDQ_5
    E9 E9
    VDDQ_6 F1 VDDQ_6 F1
    FBA_DQS4 F3 VDDQ_7 H2 FBA_DQS7 F3 VDDQ_7 H2
    FBA_DQS5 C7 DQSL VDDQ_8 H9 FBA_DQS6 C7 DQSL VDDQ_8 H9
    DQSU VDDQ_9 DQSU VDDQ_9

    g.
    FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
    FBA_DQM5 D3 DML VSS_1 B3 FBA_DQM6 D3 DML VSS_1 B3
    DMU VSS_2 E1 DMU VSS_2 E1
    VSS_3 G8 VSS_3 G8
    FBA_DQS#4 G3 VSS_4 J2 FBA_DQS#7 G3 VSS_4 J2
    FBA_DQS#5 B7 DQSL VSS_5 J8 FBA_DQS#6 B7 DQSL VSS_5 J8
    DQSU VSS_6 M1 DQSU VSS_6 M1
    VSS_7 VSS_7

    an
    M9 M9
    VSS_8 P1 VSS_8 P1
    FBA_RST# T2 VSS_9 P9 FBA_RST# T2 VSS_9 P9
    {20,21} FBA_RST# RESET VSS_10 RESET VSS_10 FBA_CLKA1
    T1 T1
    L8 VSS_11 T9 L8 VSS_11 T9
    ZQ VSS_12 ZQ VSS_12

    1
    1

    1
    J1 B1 J1 B1 RV38
    RV28 L1 NC1 VSSQ_1 B9 RV29 L1 NC1 VSSQ_1 B9 40.2_0402_1%
    243_0402_1% J9 NC2 VSSQ_2 D1 243_0402_1% J9 NC2 VSSQ_2 D1 PX@

    Hu
    PX@ L9 NC3 VSSQ_3 D8 PX@ L9 NC3 VSSQ_3 D8

    2
    FBA_MA15 M7 NC4 VSSQ_4 E2 FBA_MA15 M7 NC4 VSSQ_4 E2 CV131
    2

    2
    NC5 VSSQ_5 E8 NC5 VSSQ_5 E8 1 2
    VSSQ_6 F9 VSSQ_6 F9
    VSSQ_7 G1 VSSQ_7 G1 PX@ .01U_0402_16V7-K
    VSSQ_8 VSSQ_8

    1
    G9 G9
    VSSQ_9 VSSQ_9 RV39
    96-BALL 96-BALL 40.2_0402_1%
    SDRAM DDR3 SDRAM DDR3 PX@
    K4W4G1646B-HC11_FBGA96 K4W4G1646B-HC11_FBGA96

    2
    B B
    FBA_CLKA1#
    @ @
    r
    +1.35VGS UV7 SIDE +1.35VGS UV8 SIDE
    Fo
    CV105 CV106 CV107 CV108 CV109 CV110 CV116 CV117 CV118 CV119 CV120 CV121
    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K

    1U_0402_10V6-K
    1 1 1 1 1 1 1 1 1 1 1 1
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    2 2 2 2 2 2 2 2 2 2 2 2

    +1.35VGS UV7 SIDE +1.35VGS UV8 SIDE


    CV111 0.1U_0201_6.3V6-K

    CV112 0.1U_0201_6.3V6-K

    CV113 0.1U_0201_6.3V6-K

    CV115 0.1U_0201_6.3V6-K

    CV114 0.1U_0201_6.3V6-K

    CV122 0.1U_0201_6.3V6-K

    CV123 0.1U_0201_6.3V6-K

    CV124 0.1U_0201_6.3V6-K

    CV125 0.1U_0201_6.3V6-K

    CV126 0.1U_0201_6.3V6-K

    1 1 1 1 1 1 1 1 1 1 1 1
    CV507 CV508
    33P_0402_50V8J 33P_0402_50V8J
    RF_PXNS@ RF_PXNS@
    2 2 2 2 2 2 2 2 2 2 2 2
    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    PX@

    RF RF
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 ATI_JET-LE_VRAM_B


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 22 of 50
    5 4 3 2 1
    5 4 3 2 1

    LCD POWER CIRCUIT B+ to +LEDVDD POWER CMOS Camera


    V20B+ +LEDVDD +3VS
    Need Short
    J1 @
    +3VS +LCDVDD_CON 1 2
    U7 2A 80 mil 2A 80 mil 1 2
    2 R22 1

    C1106 22P_0402_50V8-J

    4.7U_0805_25V6-K

    0.1U_0201_25V6-K
    5 1 0_0805_5% C25 JUMP_43X39
    IN OUT
    1 1 1 C23
    1U_0402_6.3V6K
    1 2 1
    GND
    C1
    C23 0.1u for G HSW panel blink issue LP2301ALT1G_SOT23-3 +3VS_CMOS
    PCH_ENVDD 4
    EN OCB
    3 C2
    4.7U_0603_6.3V6K2 2 2 W=40 mils

    RFNS@

    D
    Q7 3 1
    D 2 2 D
    W=40mils
    SY6288C20AAC_SOT23-5 1

    G
    1 1

    2
    C3
    C5 @ C6 0.1U_0201_6.3V6-K
    PCH_ENVDD 0.1U_0201_6.3V6-K 2
    0.1U_0201_6.3V6-K
    {6} PCH_ENVDD @

    1
    2 2
    @ @
    R35
    100K_0402_5% R5 1 2
    {35} CMOS_ON#
    100K_0402_5%
    +3VS
    2 2 @ 1
    C10
    C14 For EMI
    0.01U_0201_6.3V7-K Close to R5 0.1U_0201_6.3V6-K

    2
    @ 1 2
    CZL enable is 3.3V, CZ is 1.8V, AP228002AW is 3.3V @
    R8 R9
    100K_0402_1% 100K_0402_1%

    @ @

    1
    +3VS EDP_AUX
    EDP_AUX#
    2

    a
    2

    2
    R10
    PCH_ENBKL R11 1 @ 2 4.7K_0402_5% R13 R15
    0_0402_5% @ 100K_0402_1% 100K_0402_1%
    1

    hu
    C @ @ JEDP1 C

    1
    R12 1 2 0_0402_5% DISPOFF# +LEDVDD 1
    {35} BKOFF# 1
    @ 2
    3 2
    R14 1 2 0_0402_5% ENBKL 4 3
    {6} PCH_ENBKL ENBKL {35} APU_EDP_TX0+ EDP_TX0+ 4
    @ C19 1 2 0.1U_0201_6.3V6-K 5
    {6} APU_EDP_TX0+ 5
    1

    APU_EDP_TX0- C16 1 2 0.1U_0201_6.3V6-K EDP_TX0- 6


    {6} APU_EDP_TX0- 6
    R16 7
    100K_0402_5% APU_EDP_TX1+ C17 1 2 0.1U_0201_6.3V6-K EDP_TX1+ 8 7

    g.
    INVT_PWM {6} APU_EDP_TX1+ APU_EDP_TX1- EDP_TX1- 8
    R19 1 2 0_0402_5% C18 1 2 0.1U_0201_6.3V6-K 9
    {6} PCH_EDP_PWM {6} APU_EDP_TX1- 9
    @ 10
    2

    APU_EDP_AUX C20 1 2 0.1U_0201_6.3V6-K EDP_AUX 11 10


    {6} APU_EDP_AUX 11

    1
    APU_EDP_AUX# C21 1 2 0.1U_0201_6.3V6-K EDP_AUX# 12
    {6} APU_EDP_AUX# 12
    can cost down R20 for CZ R20
    100K_0402_5% DISPOFF#
    13
    14 13
    CZL@ 15 14
    INVT_PWM 16 15

    2
    16

    an
    17
    +3VS 18 17
    19 18
    {6} APU_EDP_HPD 19
    R21 1 @ 2 20
    0_0402_5% 21 20
    1 +LCDVDD_CON 21
    C22
    W=60mils 22
    23 22
    +3VS 23
    680P_0402_50V7K {34} DMIC_DATA 24
    @ 2 25 24

    Hu
    {34} DMIC_CLK 25
    26
    27 26
    R182 1 @ 2 0_0402_5% USB20_P5_R 28 27
    {8} USB20_P5 28
    R183 1 @ 2 0_0402_5% USB20_N5_R 29
    B {8} USB20_N5 29 B
    +3VS_CMOS 30
    31 30
    1 G1
    C24
    .047U_0201_6.3V6K
    W=40mils 32
    G2

    EMC@
    DRAPH_FC5AF301-3181H
    2
    ME@
    r
    L12 EMC_NS@
    USB20_P5 1 2 USB20_P5_R
    1 2
    Fo
    USB20_N5 4 3 USB20_N5_R
    4 3
    EXC24CH900U_4P
    DMIC_CLK DISPOFF# INVT_PWM
    C11

    100P_0402_50V8J

    C12

    C13
    EMC_NS@
    1 1 1

    EMC_NS@

    EMC_NS@
    470P_0201_50V7-K

    470P_0201_50V7-K
    2 2 2

    A A

    EMC

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 eDP/CMOS/Touch screen
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 23 of 50
    5 4 3 2 1
    5 4 3 2 1

    UW1

    RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1


    USB20_N3 RW9 1 2 0_0402_5% USB20_N3_R 2 RREF V18 23
    {8} USB20_N3 DM XD_D7
    USB20_P3 RW10 1 2 0_0402_5% USB20_P3_R 3 22
    {8} USB20_P3 DP SP14
    +3VS 4 21 SD_D2_R
    CARD_3V3 5 3V3_IN SP13 20 SD_D3_R
    D SDREG 6 CARD_3V3 SP12 19 D
    7 SDREG SP11 18 SD_CMD_R
    1 1 XD_CD# SP10
    CW2 CW3 SD_WP 8 17
    4.7U_0402_6.3V6M 0.1u_0201_10V6K 9 SP1 GPIO0 16
    SD_D1_R 10 SP2 SP9 15 SD_CLK_R
    2 2 1 SP3 SP8
    LW1 CW4 SD_D0_R 11 14
    USB20_N3 1 2 USB20_N3_R 1U_0402_6.3V6K 12 SP4 SP7 13 SD_CD#
    1 2 SP5 SP6
    2 25
    USB20_P3 4 3 USB20_P3_R GND
    4 3
    EXC24CH900U_4P RTS5170-GRT_QFN24_4X4
    EMC_NS@
    FOR EMI

    a
    SD / MMC
    C C

    hu
    SD_D0_R RW3 1 2 0_0402_5% SD_D0
    CW5 1 2 5.6P_0402_50V8-D CARD_3V3
    JREAD1
    EMC@ 4
    VDD

    0.1u_0201_10V6K
    4.7U_0402_6.3V6M
    1 1 SD_D0 7
    SD_D1_R RW4 1 2 0_0402_5% SD_D1 SD_D1 8 DAT0
    DAT1

    g.
    CW6 1 2 5.6P_0402_50V8-D CW9 CW17 SD_D2 9
    @ SD_D3 1 DAT2
    2 2 CD/DAT3
    EMC@
    SD_CD# 11
    SD_WP 10 C/D
    SD_D2_R RW5 1 2 0_0402_5% SD_D2 W/P
    CW7 1 2 5.6P_0402_50V8-D Close to Connector SD_CMD 2
    CMD

    an
    SD_CLK 5
    CLK
    EMC@
    3 12
    6 VSS1 GND_1 13
    SD_D3_R RW6 1 2 0_0402_5% SD_D3 VSS2 GND_2
    CW8 1 2 5.6P_0402_50V8-D DEREN_404232501111RHF_NR
    ME@

    Hu
    EMC@
    B Close to Connector B

    SD_CMD_R RW7 1 2 0_0402_5% SD_CMD


    CW11 1 2 5.6P_0402_50V8-D
    CARD_3V3
    EMC@

    1
    SD_CLK_R RW8 1 2 0_0402_5% SD_CLK DW1

    AZ5123-01F.R7GR_DFN1006P2X2
    CW12 1 2 5.6P_0402_50V8-D
    r
    EMC_NS@
    EMC@

    2
    Fo
    2

    FOR ESD

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 CardReader
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 24 of 50
    5 4 3 2 1
    5 4 3 2 1

    D3
    HDMI_DET 1 1 10 9 HDMI_DET
    L2 EMC_NS@
    HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@ HDMIDAT_R 2 2 9 8 HDMIDAT_R
    1 2 C26 3.3P_0402_50V8-C
    HDMICLK_R 4 4 7 7 HDMICLK_R
    HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@ +3VS
    4 3 5 5
    C27 3.3P_0402_50V8-C +5VS_HDMI 6 6 +5VS_HDMI
    EXC24CH900U_4P
    D 3 3 D
    L3 EMC_NS@
    HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@ 8
    1 2

    5
    C28 3.3P_0402_50V8-C

    G
    Q1B
    HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@ AZ1045-04F_DFN2510P10E-10-9
    4 3 C29 3.3P_0402_50V8-C EMC_NS@
    EXC24CH900U_4P APU_DDC_CLK 4 3 HDMICLK_R

    S
    {6} APU_DDC_CLK

    D
    EMC
    L4 EMC_NS@ L2N7002KDW1T1G_SOT363-6

    2
    HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2 EMC_NS@

    G
    1 2 C30 3.3P_0402_50V8-C Q1A

    HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@


    4 3 C31 3.3P_0402_50V8-C APU_DDC_DATA 1 6 HDMIDAT_R

    S
    {6} APU_DDC_DATA

    D
    EXC24CH900U_4P
    L2N7002KDW1T1G_SOT363-6
    L5 EMC_NS@
    HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@
    1 2 C32 3.3P_0402_50V8-C +5VS_HDMI
    +5VS +5VS_HDMI_F +5VS_HDMI
    HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@ D5
    4 3

    2
    C33 3.3P_0402_50V8-C 2 F1
    EXC24CH900U_4P D4 1 1 2
    3

    a
    +3VS RB491D_SOT23-3 0.5A_6V_1206L050YRHF
    EMC
    @ LBAT54SWT1G_SOT323-3 @

    1
    1 3 Q22

    S
    hu
    1
    LP2301ALT1G_SOT23-3 1
    Follow Zx05 and beema C34

    C
    Q43

    G
    2

    4
    3
    C LMBT3904WT1G_SOT323-3 B 2 R202 1 2 150K_0402_5% 0.1U_0201_6.3V6-K C
    RP2 2
    {37} SUSP

    1
    2.2K_0404_4P2R_5%

    E
    HDMI_CLK-_C R29 1 2 499_0402_1% R257
    {6} APU_HDMI_HPD
    100K_0402_5%

    1
    2
    1
    3
    HDMI_CLK+_C

    g.
    R30 1 2 499_0402_1%
    R260 JHDMI1

    2
    HDMI_TX0-_C R31 1 2 499_0402_1% 100K_0402_5% HDMI_DET 19
    18 HP_DET
    HDMI_TX0+_C R32 1 2 499_0402_1% 17 +5V

    2
    HDMIDAT_R 16 DDC/CEC_GND
    HDMI_TX1-_C R33 1 2 499_0402_1% HDMICLK_R 15 SDA
    14 SCL
    HDMI_TX1+_C R34 1 2 499_0402_1% 13 Reserved
    CEC

    an
    C35 1 2 0.1U_0201_6.3V6-K HDMI_CLK-_C R43 2 1 0_0402_5% HDMI_CLK-_CON 12 20
    HDMI_TX2-_C {6} APU_HDMI_CLK- CK- GND1
    R37 1 2 499_0402_1% 11 21
    C36 1 2 0.1U_0201_6.3V6-K HDMI_CLK+_C R44 2 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 22
    HDMI_TX2+_C {6} APU_HDMI_CLK+ HDMI_TX0-_C R45 2 HDMI_TX0-_CON CK+ GND3
    R38 1 2 499_0402_1% C37 1 2 0.1U_0201_6.3V6-K 1 0_0402_5% 9 23
    {6} APU_HDMI_TX0- D0- GND4
    8
    C38 1 2 0.1U_0201_6.3V6-K HDMI_TX0+_C R46 2 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield
    {6} APU_HDMI_TX0+ HDMI_TX1-_C R47 2 HDMI_TX1-_CON D0+
    C39 1 2 0.1U_0201_6.3V6-K 1 0_0402_5% 6
    {6} APU_HDMI_TX1- D1-
    1

    Q13 D 5
    2 C40 1 2 0.1U_0201_6.3V6-K HDMI_TX1+_C R48 2 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield

    Hu
    +3VS {6} APU_HDMI_TX1+ D1+
    G C41 1 2 0.1U_0201_6.3V6-K HDMI_TX2-_C R49 2 1 0_0402_5% HDMI_TX2-_CON 3
    {6} APU_HDMI_TX2- D2-
    2
    L2N7002KWT1G_SOT323-3 S C42 1 2 0.1U_0201_6.3V6-K HDMI_TX2+_C R50 2 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
    {6} APU_HDMI_TX2+
    3

    D2+
    R42 1 @ 2 SINGA_2HE3Y37-000111F
    ME@
    100K_0402_5%

    B B
    r
    D6 D7
    HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON
    Fo
    HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

    HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

    HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

    3 3 3 3

    8 8

    AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
    EMC_NS@ EMC_NS@

    EMC

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 HDMI_CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 25 of 50
    5 4 3 2 1
    5 4 3 2 1

    D D

    a
    hu
    C C

    g.
    an
    B

    Hu B
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 DP to CRT Convert(IT6515FN)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 26 of 50
    5 4 3 2 1
    5 4 3 2 1

    D D

    a
    hu
    C C

    g.
    an
    B

    Hu B
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 CRT
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 27 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VALW TO +3VALW_LAN
    +3VALW_LAN rising time (10%~90%): 
    +3VALW +3VALW_LAN
    0.5ms＜spec＜100ms +3VALW_LAN +LAN_VDDREG
    Need short
    @ 40mil
    JL1 1 2 @ width : 40 mils RL1 1 2
    1 2 0_0603_5%
    JUMP_43X79
    D D
    1 1
    CL1

    4.7U_0603_6.3V6K

    4.7U_0603_6.3V6K

    CL6

    CL7
    1 1 1 1 4.7U_0603_6.3V6K CL2
    CL4 CL5 @ 0.1U_0201_6.3V6-K
    2 2

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    @
    2 2 2 2

    SIVCD@ SIVCD@

    Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32


    +3VALW_LAN +3VS

    +3VALW_LAN

    2
    RL4
    change the Lan Chip PN to RTL8107ECG

    G
    2
    10K_0402_5%
    RL5 @
    10K_0402_5%

    1
    @ LAN_CLKREQ#_R 1 3
    LAN_CLKREQ# {7}

    S
    a
    UL1
    1
    RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R QL1
    {7,31,35} PCIE_WAKE# L2N7002KWT1G_SOT323-3
    {31,35} LAN_WAKE# RL10 1 @ 2 0_0402_5%
    33 RL18 1 @ @ 2 0_0402_5%
    GND

    hu
    C 32 +3VALW_LAN 16 CLK_PCIE_LAN# C
    AVDD33 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# {8}
    RL8 1 2 31 RSET 15
    +LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N2 CLK_PCIE_LAN {8}
    2.49K_0402_1% 30 14
    LAN_XTALO AVDD10_1 HSIN PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 {4}
    29 13
    LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P2 {4}
    28 12
    +3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
    +3VALW_LAN LAN_DISABLE# 26 LED0 NC_4 10 LAN_MDI3-
    GPO NC_3 LAN_MDI3+ LAN_MDI3- {29}
    TL4 @ 1 25 9
    LED1 NC_2 LAN_MDI3+ {29}
    1

    +LAN_REGOUT 24 8 +LAN_VDD10

    g.
    NC_6 AVDD10_0
    2

    RL9 +LAN_VDDREG 23 7 LAN_MDI2-


    +LAN_VDD10 DVDD33 NC_1 LAN_MDI2+ LAN_MDI2- {29}
    1K_0402_1% RL21 22 6
    PCIE_WAKE#_R NC_5 NC_0 LAN_MDI1- LAN_MDI2+ {29}
    10K_0402_5% 21 5
    LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- {29}
    ISOLATE# 20 4
    LAN_MDI1+ {29}
    2

    @ PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10


    {7,15,31} PLT_RST#
    1

    CL10 1 2 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_N2 18 PERSTB NC_7 2 LAN_MDI0-


    {4} PCIE_PRX_DTX_N2 HSON MDIN0 LAN_MDI0- {29}
    ISOLATE# CL11 1 2 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_P2 17 1 LAN_MDI0+
    {4} PCIE_PRX_DTX_P2 HSOP MDIP0 LAN_MDI0+ {29}
    LAN_DISABLE#

    an
    CL10 close to Pin18
    1

    RL11 PLT_RST# CL11 close to Pin17


    @ 15K_0402_5% RTL8106E-CG_QFN32_4X4
    1
    CL34
    2

    0.1u_0201_10V6K
    EMC_NS@
    2

    Hu
    B B

    For RTL8111H (LDO mode)
    +LAN_VDD10
    r
    +LAN_REGOUT RL6 1 2 0_0805_5%
    60mil
    CL33 0.1U_0201_6.3V6-K

    CL17 0.1U_0201_6.3V6-K

    CL18 0.1U_0201_6.3V6-K

    CL19 0.1U_0201_6.3V6-K

    CL20 0.1U_0201_6.3V6-K

    CL22 0.1U_0201_6.3V6-K
    60mil @@
    Fo
    1 1 1 1 1 1 1 1 1
    LAN_XTALI LL1 1 2
    2.2UH_NLC252018T-2R2J-N_5% CL15 CL16 CL21
    YL1 LAN_XTALO 1U_0402_6.3V6K
    4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K
    2 @ @ 2 2 2 2 2 2 2 @ 2 @
    1 4 @
    OSC1 GND2
    2 3 Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
    GND1 OSC2
    1 1
    CL12 25MHZ_10PF_7V25000014 CL13
    Layout Note: RL6,CL16 must be
    12P_0402_50V8-J 12P_0402_50V8-J within 200mil to Pin36, @ @
    2 2 +LAN_REGOUT: Width =60mil

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_RTL8111H_CG
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 28 of 50
    5 4 3 2 1
    5 4 3 2 1

    DL1/DL2
    1'S PN:SC300003M00
    EMC@ TL1
    MCT 1 24 TCT
    D TCT1 MCT1 D
    DL1 LAN_MDI0+ 2 23 LAN_MDO0+
    LAN_MDI2+ LAN_MDI2+ {28} LAN_MDI0+ TD1+ MX1+
    1 10
    LINE1IN LINE1OUT LAN_MDI0- 3 22 LAN_MDO0-
    {28} LAN_MDI0- TD1- MX1-

    1
    LAN_MDI2- 2 9 LAN_MDI2-
    LINE2IN LINE2OUT 4 21 RL17
    3 8 TCT2 MCT2 20_0603_5%
    GND1 GND2

    1
    LAN_MDI1+ 5 20 LAN_MDO1+
    {28} LAN_MDI1+ TD2+ MX2+
    LAN_MDI3+ 4 7 LAN_MDI3+ DL3

    1
    2
    LINE3IN LINE3OUT LAN_MDI1- 6 19 LAN_MDO1- PDT5061_DO-214AA
    {28} LAN_MDI1- TD2- MX2- EMC@
    LAN_MDI3- 5 6 LAN_MDI3- EMC@
    LINE4IN LINE4OUT

    2
    7 18 EMC
    11 13 TCT3 MCT3

    2
    GND3 GND5 LAN_MDI2+ 8 17 LAN_MDO2+
    {28} LAN_MDI2+ TD3+ MX3+
    12
    GND4 LAN_MDI2- 9 16 LAN_MDO2-
    {28} LAN_MDI2- TD3- MX3-
    AZ3133-08F.R7G_DFN3020P10E10
    EMC_NS@ 10 15
    TCT4 MCT4
    1 1
    LAN_MDI3+ 11 14 LAN_MDO3+ CL32 CL25
    {28} LAN_MDI3+ TD4+ MX4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
    LAN_MDI3- LAN_MDO3-

    a
    1 12 13 EMC@ EMC@
    {28} LAN_MDI3- TD4- MX4- 2 2
    DL2 CL24 EMC
    LAN_MDI1- 1 10 LAN_MDI1- 68P_0402_50V8J
    C LINE1IN LINE1OUT C
    EMC@ TST1284A

    hu
    LAN_MDI1+ 2 9 LAN_MDI1+ 2
    LINE2IN LINE2OUT
    EMC
    3 8
    GND1 GND2
    LAN_MDI0- 4 7 LAN_MDI0-
    LINE3IN LINE3OUT CHASSIS1_GND
    LAN_MDI0+ 5 6 LAN_MDI0+
    LINE4IN LINE4OUT

    g.
    11 13
    GND3 GND5
    12 JRJ1
    GND4
    AZ3133-08F.R7G_DFN3020P10E10 LAN_MDO0+ 1
    EMC_NS@ PR1+

    an
    LAN_MDO0- 2
    PR1-
    Place Close to TL1 LAN_MDO1+ 3
    PR2+
    LAN_MDO2+ 4
    PR3+
    LAN_MDO2- 5
    PR3-

    Hu
    B LAN_MDO1- 6 B
    PR2-
    LAN_MDO3+ 7
    PR4+
    EMC_NS@ LAN_MDO3- 8
    RL14 1 2 0_0603_5% PR4- 9
    EMC_NS@ GND_1
    RL15 1 2 0_0603_5% 10
    EMC_NS@ GND_2
    RL16 1 2 0_0603_5% Don't short
    r
    J13 @
    EMC TCT 1 2 ALLTO_C100JH-10839-L
    1 2
    ME@
    Fo
    JUMP_43X79
    CHASSIS1_GND
    CHASSIS1_GND
    CHASSIS1_GND

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 LAN_Transformer
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 29 of 50
    5 4 3 2 1
    5 4 3 2 1

    R175 1 @ 2 0_0402_5% REMOTE1+

    Close to U1 REMOTE2+
    REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+
    Near GPU&VRAM Near CPU core

    1
    REMOTE+_R

    1
    1

    C
    C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 1 1 Q16

    C
    2200P_0402_50V7K C45 Q15 C46 2 B LMBT3904WT1G_SOT323-3
    100P_0402_50V8J 2 B LMBT3904WT1G_SOT323-3 100P_0402_50V8J
    2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- @ @
    @ 2 2

    E
    @

    E
    @

    3
    D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: D

    3
    REMOTE2-
    Trace width/space:10/10 mil REMOTE1-
    Trace length:<8"

    SMSC thermal sensor


    placed near DIMM +3VALW
    +3VALW
    Near CPU
    +3VS
    U1

    1
    1 8 EC_SMB_CK2
    VDD SCL EC_SMB_CK2 {6,16,35}
    R17 R25
    1 REMOTE+_R 2 7 EC_SMB_DA2 13.7K_0402_1% 13.7K_0402_1%
    D+ SDA EC_SMB_DA2 {6,16,35}
    C47 REMOTE-_R 3 6

    2
    D- ALERT# NTC_V1 NTC_V2
    0.1U_0201_6.3V6-K
    2 @ +3VS R51 2 @ 1 4 5
    T_CRIT# GND

    1
    10K_0402_5% @
    NCT7718W_MSOP8 R1 R3
    100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ
    Address 1001_101xb

    a
    PX@

    2
    2

    2
    hu
    R184 R185 R191 R192
    +5VLP +5VLP 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
    C +5VLP PX@ C
    @ @

    1
    HW thermal sensor

    2
    1 R252 R253

    g.
    21.5K_0402_1% 21.5K_0402_1% EC_AGND EC_AGND
    C4 @ @
    0.1U_0201_6.3V6-K

    1
    2 @ @
    U4
    1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
    VCC TMSNS1 NTC_V1 {35}
    2 7 PHYST1 R6 1 @ 2 10K_0402_5%
    GND RHYST1

    an
    3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
    {45} EC_ON_R OT1 TMSNS2 NTC_V2 {35}
    4 5 PHYST2 R7 1 @ 2 10K_0402_5%
    OT2 RHYST2
    G718TM1U_SOT23-8

    over temperature threshold: +3VS

    Hu
    RSET=3*RTMH +3VS_TPM

    CTPM3
    1A RTPM11 TPM@ 2 0_0603_5%
    92+/-30C 1 1
    Hysteresis temperature threshold. CTPM1
    RHYST=(RSET*RTML)/(3*RTML-RSET) TPM

    0.1U_0201_6.3V6-K
    10U_0603_6.3V6M
    2 TPM@ 2 TPM@
    56+/-30C
    B B
    r
    +3VS_TPM
    UTPM1 TPM@
    1 24
    2 NC_1 VPS_1 10
    Fo
    3 NC_2 VPS_2
    +5VS 7 NC_3 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
    JFAN1 PP LPCPD# 27
    +5VS_FAN SERIRQ SERIRQ {8,35}
    R52 1 @ 2 0_0603_5% 1 6 26
    1 NC_4 LAD0 LPC_AD0 {8,35}
    {35} EC_FAN_SPEED 2 9 23
    2 VNC_1 LAD1 LPC_AD1 {8,35}
    1 1 {35} EC_FAN_PWM 3 22
    C50 3 LFRAME# LPC_FRAME# {8,11,35}
    4 4 20
    4 GND_1 LAD2 LPC_AD2 {8,35}
    C49 5 11 17
    0.1u_0201_10V6K GND1 GND_2 LAD3 LPC_AD3 {8,35}
    10U_0805_10V6K 6 18
    2 GND2 GND_3
    @ 2 +3VS_TPM 25 +3VS_TPM
    ACES_85205-04001 5 NC_11 21 RTPM3 1 TPM@ 2 0_0402_5%
    NC_5 LCLK TPM_CLK {8}
    ME@ 8 19
    12 VNC_2 NC_10 15 RTPM4 1 TPM@ 2 0_0402_5%
    13 NC_6 NC_9
    14 NC_7 16
    NC_8 LRESET# APU_LPC_RST# {7,35}
    ST33ZP24AR28PVSP_TSSOP28

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Thermal sensor/FAN CONN/TPM
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 30 of 50
    5 4 3 2 1
    A B C D E

    Mini-Express Card(WLAN/WiMAX)
    +3VS_WLAN

    JWLAN1
    1 1
    1 2
    3 GND1 3.3VAUX1 4
    {8} USB20_P4 USB_D+ 3.3VAUX2
    5 6 1 @ T2
    {8} USB20_N4 USB_D- LED#1
    7 8
    9 GND2 PCM_CLK 10
    11 SDIO_CLK PCM_SYNC 12
    13 SDIO_CMD PCM_IN 14
    15 SDIO_DAT0 PCM_OUT 16 1 @ T3
    17 SDIO_DAT1 LED#2 18
    19 SDIO_DAT2 GND11 20
    21 SDIO_DAT3 UART_WAKE 22
    23 SDIO_WAKE UART_RX
    SDIO_RESET

    KEY E
    25 PIN24~PIN31 NC PIN 24
    27 26
    29 28
    31 30

    33 32
    35 GND3 UART_TX 34

    a
    {4} PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
    37 36
    {4} PCIE_PTX_C_DRX_N1 PETN0 UART_RTS EC_TX_RSVD
    39 38 R62 1 @ 2 0_0402_5%
    41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
    {4} PCIE_PRX_DTX_P1 PERP0 RSRVD11
    43 42

    hu
    {4} PCIE_PRX_DTX_N1 PERN0 RSRVD9
    45 44 R88 1 2 0_0402_5%
    GND5 COEX3 EC_RX {35}
    47 46 @
    {8} CLK_PCIE_WLAN REFCLKP0 COEX2
    49 48
    {8} CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
    2 51 50 R55 1 2 0_0402_5% 2
    WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK {7,11}
    53 52 @
    CLKEQ0# PERSTO# BT_OFF# PLT_RST# {7,15,28}
    55 54 R53 1 2 1K_0402_5%
    {7,28,35} PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 WLAN_OFF# PCH_BT_OFF# {7}
    57 56 R56 1 2 0_0402_5%
    GND7 W_DISABLE#1 PCH_WLAN_OFF# {7}
    R57 1 @ 2 0_0402_5% @
    {28,35} LAN_WAKE#

    g.
    59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%
    RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R R59 APU_SMB_DATA {7,12}
    61 60 1 @ 2 0_0402_5%
    RSRVD/PETN1 I2C_CLK APU_SMB_CLK {7,12}
    63 62
    65 GND8 ALERT 64 EC_TX_R R89 1 2 0_0402_5%
    RSRVD/PERP1 RSRVD6 EC_TX {35}
    67 66 @
    69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
    GND9 RSRVD8

    1
    71 70
    RSRVD1 RSRVD12

    an
    73 72 R186
    75 RSRVD2 3.3VAUX3 74 100K_0402_5%
    GND10 3.3VAUX4
    77 76

    2
    GND15 GND14

    LCN_DAN05-67406-0102
    ME@

    Hu Need short
    3
    r
    Not support AOAC, delete AOAC power circuit 1015 +3VS
    @
    +3VS_WLAN
    J2
    1 2
    1 2
    Fo
    JUMP_43X79

    R61 1 2 0_0402_5% WLAN_CLKREQ_Q#


    {7} WLAN_CLKREQ#
    @

    If support AOAC, NC R61;


    if not support AOAC, stuff R61.

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 NGFF WLAN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 31 of 50
    A B C D E
    A B C D E

    +USB_VCCA USB20_N0_R USB20_P0_R

    2
    D9
    AZC199-02S.R7G_SOT23-3

    1
    EMC_NS@
    D11

    1
    EMC_NS@
    AZ5725-01F_DFN1006P2X2

    LEFT SIDE USB PORT X2

    2
    1 1

    1
    +5VALW +USB_VCCA
    U2
    5 1
    IN OUT
    1
    C58 2
    1U_0402_6.3V6K GND D12 EMC_NS@
    4 3 USB_OC1# USB30_RX_R_N2 9 10 1 1USB30_RX_R_N2 USB20_N6_R USB20_P6_R
    2 {35} USB_ON# ENB OCB USB_OC1# {7}

    2
    SY6288D20AAC_SOT23-5 USB30_RX_R_P2 8 9 2 2 USB30_RX_R_P2
    1 C61 D13
    USB30_TX_R_N2 7 7 4 4 USB30_TX_R_N2 AZC199-02S.R7G_SOT23-3
    Low Active 2A 1000P_0201_50V7-K EMC_NS@
    EMC_NS@ USB30_TX_R_P2 6 6 5 5 USB30_TX_R_P2
    2
    3 3

    a
    AZ1045-04F_DFN2510P10E-10-9

    1
    hu
    EMC solution need double check 1015
    2 2

    +USB_VCCA

    g.
    C55 1 2

    +
    220U_6.3V_M
    1 1
    1 C83 1 2
    C65 C60 @ 1U_0603_25V6M
    C64 22U_0805_6.3V6M 22U_0805_6.3V6M
    L17 EMC_NS@ 22U_0805_6.3V6M 2 2 C88 1 2
    @ @

    an
    USB20_N0 1 2 USB20_N0_R 2 470P_0201_50V7-K
    1 2 @
    @
    USB20_P0 4 3 USB20_P0_R JUSB1
    4 3 1
    EXC24CH900U_4P USB20_N0 R65 2 1 0_0402_5% USB20_N0_R 2 VBUS
    {8} USB20_N0 USB20_P0 0_0402_5% USB20_P0_R D-
    R64 2 1 3
    {8} USB20_P0 D+
    4 5

    Hu
    GND GND1 6
    GND2 7
    GND3 8
    GND4
    L13 EMC_NS@ ALLTO_C107X3-10439-L
    USB30_RX_P2 1 2 USB30_RX_R_P2 ME@
    1 2 +USB_VCCA
    3 3
    USB30_RX_N2 4 3 USB30_RX_R_N2
    4 3 C62 1 2
    EXC24CH900U_4P @ 1U_0603_25V6M
    r
    C63 1 2
    L16 EMC_NS@ @ 470P_0402_50V7K
    USB30_TX_C_P2 1 2 USB30_TX_R_P2
    Fo
    1 2

    USB30_TX_C_N2 4 3 USB30_TX_R_N2
    4 3
    EXC24CH900U_4P JUSB2 ME@
    USB30_TX_P2 C84 1 2 0.1U_0201_6.3V6-KUSB30_TX_C_P2 R95 2 1 0_0402_5% USB30_TX_R_P2 9
    {8} USB30_TX_P2 StdA_SSTX+
    L8 EMC_NS@ 1
    USB20_P6 1 2 USB20_P6_R USB30_TX_N2 C89 1 2 0.1U_0201_6.3V6-KUSB30_TX_C_N2 R96 2 1 0_0402_5% USB30_TX_R_N2 8 VBUS
    1 2 {8} USB30_TX_N2 USB20_P6 0_0402_5% USB20_P6_R StdA_SSTX-
    R97 2 1 3
    {8} USB20_P6 D+
    7
    USB20_N6 4 3 USB20_N6_R USB20_N6 R93 2 1 0_0402_5% USB20_N6_R 2 GND_DRAIN 10
    4 3 {8} USB20_N6 0_0402_5% D- GND_1
    USB30_RX_P2 R94 2 1 USB30_RX_R_P2 6 11
    {8} USB30_RX_P2 StdA_SSRX+ GND_2
    EXC24CH900U_4P 4 12
    USB30_RX_N2 R92 2 1 0_0402_5% USB30_RX_R_N2 5 GND_5 GND_3 13
    {8} USB30_RX_N2 StdA_SSRX- GND_4
    EMC
    SUYIN_020053GR009M2736L

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 P32-USB3.0 PORT (LEFT)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 32 of 50
    A B C D E
    A B C D E F G H

    SATA HDD Conn.


    FOR 14"
    JHDD1

    1
    SATA ODD Conn.
    SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_P0 2 GND_1
    {8} SATA_PTX_DRX_P0 A+
    SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_N0 3
    {8} SATA_PTX_DRX_N0 A-
    4
    1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_N0 5 GND_2 1
    {8} SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_P0 6 B-
    {8} SATA_PRX_DTX_P0 7 B+
    GND_3 SATA_PTX_DRX_P1
    {8} SATA_PTX_DRX_P1
    SATA_PTX_DRX_N1
    {8} SATA_PTX_DRX_N1
    8
    9 V33_1 SATA_PRX_DTX_N1
    10 V33_2 {8} SATA_PRX_DTX_N1 SATA_PRX_DTX_P1
    11 V33_3 {8} SATA_PRX_DTX_P1
    Need short +5VS_HDD 12 GND_4
    J3 @ 13 GND_5
    1 2 14 GND_6
    +5VS 1 2 V5_1
    15
    JUMP_43X79 16 V5_2
    17 V5_3
    18 GND_7
    19 DAS/DSS
    +5VS_HDD 20 GND_8 23
    21 V12_1 GND1 24
    22 V12_2 GND2
    V12_3

    C1107 22P_0402_50V8-J

    C1108 22P_0402_50V8-J
    C78 10U_0805_10V6K
    1 1 1 1 1 1 1
    C75 0.1U_0201_6.3V6-K

    C76 1U_0603_25V6M

    C77 10U_0805_10V6K

    C74 ALLTO_C166FE-12239-L

    a
    1000P_0201_50V7-K ME@
    @

    EMC_NS@ @
    2 2 2 2 2 2 2
    RFNS@

    RFNS@
    @
    FOR 15"

    hu
    2 EMC 2

    SATA ODD FFC Conn
    JODD2
    1
    +5V_ODD 1

    g.
    2
    3 2
    SATA_PRX_DTX_P1 C79 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_P1_15 4 3
    SATA_PRX_DTX_N1 C80 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_N1_15 5 4
    6 5
    SATA_PTX_DRX_N1 C81 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_N1_15 7 6
    SATA_PTX_DRX_P1 C82 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_P1_15 8 7
    8

    an
    9
    10 GND1
    +5VS to +5V_ODD GND2

    HIGHS_FC5AF081-2931H
    ME@

    Hu
    +5VS +5V_ODD
    Need short
    J4 @
    1 2
    3 1 2 3

    JUMP_43X79
    10U_0805_10V6K

    1 1
    C86
    0.1U_0201_6.3V6-K
    2 2
    r
    C85

    Delete Zero ODD circuit 10/19


    Fo

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 HDD/ODD CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 33 of 50
    A B C D E F G H
    5 4 3 2 1

    +3.3VD
    +3VS
    @
    RA2 1 2 0_0603_5% +5VS +5VS

    2 2
    +1.5VS +VAUDIO

    CA8
    1U_0402_6.3V6K
    2A @
    CA7 RA10 1EMC@ 2 0_0603_5% +5VD +5VA RA7 1 2 0_0603_5%
    Close to Pin1 1 1
    0.1U_0201_6.3V6-K RA11 2 @ 1 0_0402_5%
    LA25 1 2 BLM15PD600SN1D_2P
    +1.5VS

    CA15
    4.7U_0603_6.3V6K

    CA180
    2.2U_0603_6.3V6K
    EMC_NS@ 2 2 1
    +1.8VS

    CA178
    10U_0805_10V6K

    CA18 0.1U_0201_6.3V6-K

    CA19 0.1U_0201_6.3V6-K
    1 2 2
    RA8 1 @ 2 0_0402_5% CA11
    RA213 1 @ 2 0_0402_5% +3.3VD DVDD_IO 0.1U_0201_6.3V6-K
    DVDD_IO 1 1 2
    D 2 1 1 1 D
    CA181 CD@
    1U_0402_6.3V6K
    2
    Close to
    +VAUDIO
    Pin40

    41

    46

    26

    40
    1

    9
    UA1
    LINE1_L CA41 2 1 1U_0402_6.3V6K

    DVDD-IO

    PVDD1

    PVDD2

    AVDD1

    AVDD2
    DVDD
    RA214 2 @ 1 0_0402_5% LINE1_VREF_L RA411 2 4.7K_0402_5%
    LINE1_L 22 43 SPK_L-
    LINE1_R 21 LINE1-L(PORT-C-L) SPK-OUT-L- 42 SPK_L+ HPOUT_L RA21 1 2 47_0402_1% A_HP_OUTL_R
    MICBIASB 1 RA38 2 2.2K_0402_5% LINE1-R(PORT-C-R) SPK-OUT-L+ HPOUT_R RA20 1 2 47_0402_1% A_HP_OUTR_R
    2 1 RA37 2 2.2K_0402_5% LINE2_L CA187 1 2 1U_0402_6.3V6K 24 45
    CA186 1 2 1U_0402_6.3V6K 23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 LINE1_VREF_L RA421 2 4.7K_0402_5%
    CA1 LINE2-R(PORT-E-R) SPK-OUT-R-
    0.1U_0201_6.3V6-K LINE1_R CA42 2 1 1U_0402_6.3V6K
    Close to1 Pin9 RING2_CONN 17
    MIC2-L(PORT-F-L)/RING HPOUT-L(PORT-I-L)
    32 HPOUT_L
    RING3_CONN 18 33 HPOUT_R
    MIC2-R(PORT-F-R)/SLEEVE HPOUT-R(PORT-I-R)
    LINE1_VREF_L 31 10 HDA_SYNC_AUDIO
    LINE1_VREF_R LINE1-VREFO-L SYNC HDA_BITCLK_AUDIO HDA_SYNC_AUDIO {7}
    30 6
    LINE1-VREFO-R BCLK HDA_BITCLK_AUDIO {7}
    5 HDA_SDOUT_AUDIO
    DMIC_DATA DMIC_DATA_R SDATA-OUT SDATA_IN RA16 2 HDA_SDIN0 HDA_SDOUT_AUDIO {7}
    {23} DMIC_DATA 0_0402_5% 2 RA19 @1 2 8 133_0402_5%
    DMIC_CLK DMIC_CLK_R GPIO0/DMIC-DATA SDATA-IN HDA_SDIN0 {7}
    0_0402_5% 2 RA18 @1 3
    {23} DMIC_CLK GPIO1/DMIC-CLK 48
    SPKR_MUTE# 47 SPDIF-OUT/GPIO2

    {7} HDA_RST_AUDIO#
    HDA_RST_AUDIO# 11 PDB
    RESETB
    ALC3248 MONO-OUT
    16

    a
    DA4 29 MICBIASB
    EC_MUTE# 1 2 @ SPKR_MUTE# 100K_0402_1% 1 RA205 2 PC_BEEP 12 MIC2-VREFO
    {35} EC_MUTE# +3VS PCBEEP
    1

    LRB751V-40T1G_SOD323-2 PLUG_IN 200K_0402_1% 2 RA204 1 JSENSE 13 7 CA2 1 2 4.7U_0603_6.3V6K


    RA35 1 @ 2 0_0402_5% RA43 14 HP/LINE1_JD(JD1) LDO3-CAP 39 CA3 1 2 4.7U_0603_6.3V6K
    MIC2/LINE2_JD(JD2) LDO2-CAP

    hu
    10K_0402_5% 27 CA5 1 2 4.7U_0603_6.3V6K
    LDO1-CAP RA471 2 2.2K_0402_5%
    CA14 1 2 1U_0402_6.3V6K 37 @
    2

    +3VS 35 CBP
    CBN
    C C
    36 28 CA17 1 2 1U_0402_6.3V6K
    CPVDD VREF
    2
    CA4 VDD_STB 20 15
    VD33_STB SPDIFO/FRONT_JD(JD3)/GPIO3 34 CA36 1 2 1U_0402_6.3V6K
    4.7U_0603_6.3V6K CPVEE
    1 19

    g.
    DA1
    2 MIC_CAP
    {35} BEEP# 2
    1PC_BEEP1 1 @ 2 CA40 1 2 PC_BEEP 4
    DC_DET
    {7} PCH_BEEP 3 RA211 0_0402_5% 0.1U_0201_6.3V6-K Close to Pin36 CA35 49
    Thermal_PAD AVSS1
    25
    1

    4.7U_0603_6.3V6K 38
    LBAT54CWT1G_SOT323-3 RA14 1 AVSS2
    10K_0402_5%

    ALC3248-CG_MQFN48_6X6
    2

    an
    JSPK1
    15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 1 EMC@ 2 BLM15PX800SN1D SPK_L+_CONN 1
    15_0402_5% 1 CD@ 2 RA33 SPK_L- RA34 1 EMC@ 2 BLM15PX800SN1D SPK_L-_CONN 2 1
    3 2
    C2301 2 0.1U_0201_6.3V6-K +3VL 4 G1
    EMC_NS@ RA203 1 @ 2 VDD_STB G2

    CA29

    CA30
    220P_0201_25V7-K

    220P_0201_25V7-K
    C2311 2 0.1U_0201_6.3V6-K 0_0402_5%

    CA31

    CA32
    EMC_NS@ 2 2 1 1 ACES_50273-0020N-001
    C9 1 2 0.1U_0201_6.3V6-K To solve the background noise while combojack connecting to an ME@
    EMC_NS@

    Hu
    active speaker and system entry into S3/S4/S5 without analog power.

    EMC@

    EMC@
    470P_0201_50V7-K

    470P_0201_50V7-K
    1 1 2 2

    A MIC
    MIC1 CD@ CD@
    RA212 2 1 1K_0402_5% LINE2_L

    1 RA44 2 1 2.2K_0402_5% LINE1_VREF_R


    OUTPUT
    Close to Pin19 GND
    2 RA215 1 2 0_0402_5%
    EMC_NS@
    B B
    RA1 1 2 0_0402_5% NEIM1000032_2P
    EMC_NS@
    RA4 1 2 0_0402_5%
    r
    EMC_NS@
    RA6 1 2 0_0402_5%

    RA9 1 2 0_0402_5% RING3_CONN


    EMC_NS@ RING2_CONN
    Fo
    RA12 1 2 0_0402_5% A_HP_OUTL_R
    EMC_NS@ A_HP_OUTR_R
    RA13 1 2 0_0402_5% PLUG_IN

    GND GNDA
    1

    1
    47P_0201_25V8-J

    Use 250mils wide trace bridging 1 DA5 DA6 DA7 DA8 DA9
    1

    1
    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AGND and DGND at codec C185


    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@
    2 Audio Jack JHP1
    2

    RING3_CONN 3
    2

    A_HP_OUTL_R 1

    PLUG_IN 6
    7
    HDA_RST_AUDIO# A_HP_OUTR_R 2 G1
    HDA_SYNC_AUDIO RING2_CONN 4
    DMIC_CLK HDA_SDOUT_AUDIO
    RA27 1 EMC_NS@2 HDA_BITCLK_AUDIO
    DMIC_DATA HDA_SDIN0

    100P_0201_25V8J

    100P_0201_25V8J
    27_0402_5% LOTES_AJAK00XX-P001A
    A 1 1 ME@ A
    A_HP_OUTL_R
    CA38

    CA39

    CA23

    CA24

    CA25

    CA26

    R266 1 2 C232 1 2
    100P_0201_25V8J

    100P_0201_25V8J

    22P_0201_258J

    22P_0201_258J
    EMC_NS@

    EMC_NS@

    68P_0402_50V8J

    33P_0201_50V8-J

    33P_0201_50V8-J

    1 1 0_0402_5% @ 470P_0201_50V7-K C182 C183


    1 1 1 1 1 R265 1 2 C184 1 @ 2 A_HP_OUTR_R EMC@ EMC@
    2 2
    CA22

    0_0402_5% @ 470P_0201_50V7-K
    2 2 @
    2 2 2 2 2
    EMC@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    For EMI
    For EMI Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Codec_CX11802_33Z


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 34 of 50
    5 4 3 2 1
    5 4 3 2 1

    RE1 1 2 0_0603_5% +3VL


    +3VL_EC +3VL_EC_R

    RE3 1 @ 2 0_0603_5% +3VALW LE1 1 2 0_0603_5%


    Close EC
    1 1
    CE3 0.1U_0201_6.3V6-K +3VL_EC CE4 CE5
    1 2 VCOREVCC 1000P_0201_50V7-K
    0.1U_0201_6.3V6-K
    All capacitors close to EC LE2 1 2 0_0603_5% 2 EC_AGND 2
    +5VS +3VS

    1 1 1 1 1 1 EC_AGND

    2
    +3VS +3VL_EC_R CE21 CE22 CE23 CE24 CE25
    CE11 RE52 RE51
    0.1U_0201_6.3V6-K
    0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0_0402_5% 0_0402_5%
    D 2 2 2 2 2 2 @ D
    @ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K @ @
    RE6 1 2 0_0402_5%

    1
    RPE4
    TP_CLK 1 4
    minimum trace width 12 mil

    114
    121
    127
    TP_DATA 2 3

    12

    11

    26
    50
    92

    74
    3
    UE1
    4.7K_0404_4P2R_5%

    VBAT

    VCORE

    VCC

    VSTBY1
    VSTBY2
    VSTBY3
    VSTBY4
    VSTBY5

    AVCC
    VSTBY(PLL)
    +3VS

    EC_FAN_SPEED RE10 1 2 10K_0402_5%


    EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
    {16} WRST#
    4 24 ENBKL RE9 1 @ 2 100K_0402_5%
    +3VL_EC {7} KBRST# KBRST#/GPB6 PWM0/GPA0 PWR_LED# {36}
    5 25
    {8,30} SERIRQ SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# {36}
    {8,11,30} LPC_FRAME#
    6
    LFRAME#/GPM5 PWM2/GPA2
    28
    BATT_LOW_LED# {36} Delete Zero ODD circuit GPA4 ODD_DA_EC# 10/20
    DE1 7 29
    {8,30} LPC_AD3 LAD3/GPM3 PWM3/GPA3 VGA_AC_DET {16}
    1 2 @ 8 PWM 30
    {8,30} LPC_AD2 LAD2/GPM2 PWM4/GPA4 EC_FAN_PWM
    9 31
    {8,30} LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM {30}
    10 32
    LRB751V-40T1G_SOD323-2 {8,30} LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_APU_ALWEN BEEP# {34} +5VALW
    {8,11} CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 EC_APU_ALWEN {47,50}
    RE8 1 2 100K_0402_5% WRST# 14 120 RE29 1 @ 2 0_0402_5%
    WRST# TMRI0/GPC4 HVB_EN {7,11}
    15 124 SUSP#
    EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# {37,46,47} USB_ON#
    1 16 RE15 1 2 10K_0402_5%
    {31} EC_RX EC_TX PWUREQ#/BBO/SMCLK2ALT/GPC7
    17 66
    CE12 {31} EC_TX APU_LPC_RST# 22 LPCPD#/GPE6 ADC0/GPI0 67 NTC_V1 {30}
    1U_0402_6.3V6K {7,30} APU_LPC_RST# LPCRST#/GPD2 ADC1/GPI1 NTC_V2 {30} +3VL_EC
    23 68
    2 {7} EC_SCI# ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP {43}
    126 ADC 69
    {7} GATEA20 GA20/GPB5 ADC3/GPI3 70
    ENBKL {23} Change LAN_PWR_ON# form PIN118 to pin70 SUSP# RE18 1 @ 2 100K_0402_5%
    IT8586E/AX ADC4/GPI4

    a
    71 LAN_WAKE# RE5 1 2 10K_0402_5%
    ADC5/DCD1#/GPI5 ADP_I {44}
    72
    ADC6/DSR1#/GPI6 EC_RTCRST#_ON {9}
    KSI0 58
    KSI0/STB#
    LQFP-128L ADC7/CTS1#/GPI7
    73 Nano G not support adapt ID( GPI7) 10/20 +3VL

    KSI[0..7] KSI1 59 78
    {36} KSI[0..7] KSI1/AFD# DAC2/TACH0B/GPJ2 MAINPWON1_EC VR_APU_PWRGD {49} LID_SW#
    KSI2 60 79 RE26 1 @ 2 1K_0402_5% RE38 1 2 100K_0402_5%

    hu
    KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPWON {45}
    KSI3 DAC
    {36} KSO[0..17] KSI3/SLIN# DAC4/DCD0#/GPJ4 MAINPWON2_EC
    KSI4 62 81 RE25 1 @ 2 1K_0402_5% RE58 1 2 100K_0402_5%+3VL_EC
    KSI5 63 KSI4 DAC5/RIG0#/GPJ5
    C KSI6 64 KSI5 85 RE57 1 @ 2 0_0402_5% C
    KSI6 PS2CLK0/TMB0/CEC/GPF0 EC_ON {45}
    KSI7 65 86 SUSP# RE19 1 2 100K_0402_5%
    36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# {7} 1 @ TE2
    KSO0 SYSON RE21 1 2 100K_0402_5%
    KSO1 37 KSO0/PD0 GPF2 88 BKOFF# RE40 1 2 10K_0402_5%
    KSO1/PD1 Int. K/B PS2 GPF3 APUALW_PWRGD {47,50}
    KSO2 38 89 TP_CLK
    KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 TP_DATA TP_CLK {36}
    KSO3/PD3 PS2DAT2/GPF5 TP_DATA {36}
    KSO4 40
    KSO4/PD4

    g.
    KSO5 41 EXTERNAL SERIAL FLASH 96
    KSO5/PD5 GPH3/ID3 CAPS_LED# {36}
    KSO6 42 97
    KSO6/PD6 GPH4/ID4 EC_VR_ON {49}
    +3VALW KSO7 43 98
    KSO8 44 KSO7/PD7 GPH5/ID5 99
    ACOFF {44} H_PROCHOT#
    KSO8/ACK# GPH6/ID6 EC_SYS_PWRGD {7}
    KSO9 45
    KSO9/BUSY
    KSO10 46
    KSO10/PE NC1
    101 EC_SPI_CS0# Need EC modify GPH6 to OD output {49} VR_HOT#
    RE34 1 @ 2 0_0402_5% H_PROCHOT# {6}
    KSO11 51 102 EC_SPI_SI
    KSO12 52 KSO11/ERR# NC2 103 EC_SPI_SO
    KSO12/SLCT SPI Flash ROM NC3
    2
    1

    1
    KSO13 53 105 EC_SPI_CLK QE1 D 1
    RPE5 KSO14 54 KSO13 NC4 H_PROCHOT#_EC 2 CE14
    KSO15 55 KSO14 GPG0 def mode GPO H G 47P_0402_50V8J
    2.2K_0404_4P2R_5%

    an
    KSO16 56 KSO15 108 ACIN# GPG1 def mode GPO L internal Pull down @
    KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# L2N7002KWT1G_SOT323-3 S 2
    UART LID_SW# {36}
    3
    4

    3
    EC_SMB_CK3 KSO17/SMISO/GPC5 LID_SW#
    EC_SMB_DA3 @
    ON/OFF 110 82
    {36} ON/OFF PWRSW# EGAD/GPE1 EC_MUTE# {34}
    EC_ON RE59 1 @ 2 0_0402_5% EC_ON_L 111 SM Bus 83
    EC_SMB_CK1 XLP_OUT EGCS#/GPE2 VGA_GATE# {7}
    115 84
    {43,44} EC_SMB_CK1 SMCLK1/GPC1 EGCLK/GPE3 CMOS_ON# {23}
    {43,44} EC_SMB_DA1
    EC_SMB_DA1 116
    SMDAT1/GPC2 Nano G not support adapt ID( GPI7) 10/20 RE89 1 @ 2 0_0402_5%
    117 GPIO 77
    Add SMBUS for POWER {49} EC_SMB_CK3 118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2
    PM_SLP_S5# {7}
    Need EC modify GPJ4 to OD output
    {49} EC_SMB_DA3 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
    core IC 10/20 EC_SMB_CK2 94 106 PIN 106 +20VSB 0 ohm direct connect, so delete PCH_PWR_EN

    Hu
    {6,16,30} EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0
    95 104 1 @ TE1
    +3VL_EC {6,16,30} EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON
    DTR1#/SBUSY/GPG1/ID7 SYSON {46}
    +3VL
    CRX0/GPC0
    119 BKOFF#
    BKOFF# {23} PIN 123Not support AOAC, delete
    123
    RE27 1 @ 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 PM_SLP_S3# {7}
    AOAC_on# power circuit 1015
    VSTBY0 RI1#/GPD0
    {28,31} LAN_WAKE# LAN_WAKE# 125
    GPE4 RI2#/GPD1
    21 PIN 21, NANO is 4 pin FAN, so delete EC_FAN_ANTI
    WAKE UP 76 NOVO# {36}
    TACH2/GPJ0
    2
    1

    48
    RPE2 Change PCH_CMOSP form PIN117 to pin35 TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_FAN_SPEED {30}
    TACH0A/GPD6
    2.2K_0404_4P2R_5% {32} USB_ON#
    USB_ON# 33
    GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0
    19 PIN 48 20 ， CZL and STN have no VDDCR_GFX, so delete VDDFX_PD and EC_GFX_PD
    35 GPIO 20
    B {37} PCH_CMOSP RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# {36} B
    93
    {7} EC_RSMRST#
    3
    4

    EC_SMB_CK1 CLKRUN#/GPH0/ID0
    EC_SMB_DA1 Need EC modify GPH0 to OD output
    2
    {7,28,31} PCIE_WAKE# CK32KE/GPJ7 +3VL
    128
    r
    +3VS {7} AC_PRESENT CK32K/GPJ6 Clock

    1
    RE56
    Fo
    2
    1

    Change GPIO setting, high active


    AVSS
    VSS1

    VSS2
    VSS3
    VSS4
    VSS5
    VSS6

    10K_0402_5%
    RPE3 @
    2.2K_0404_4P2R_5%

    2
    IT8586E-AX_LQFP128_14X14 ACIN# RE88 1 @ 2 0_0402_5%
    1

    27
    49
    91
    113
    122

    75
    3
    4

    EC_SMB_CK2

    1
    EC_SMB_DA2 D QE2
    2
    G ACIN {44}
    EC_AGND
    AMD request SIC/SID（EC_SMB2） pull high 1K L2N7002KWT1G_SOT323-3
    3
    S
    @

    Factory EC flash for STN


    Mirror Core strap CLK_PCI_EC RE2 1 2 10_0402_5% EMC_NS@ CE2 1 2 10P_0402_50V8J
    +3VL_EC EC_SPI_CS0# RE45 1 CZL@ 2 0_0402_5% SPI_CS0# EC_SMB_CK1 PAD 1 @ VR_APU_PWRGD EMC_NS@ +3VS
    SPI_CS0# {8} EC_SMB_DA1 1 IT1 APU_LPC_RST# 1 2 220P_0402_50V7K
    PAD @ EMC_NS@ CE1
    IT2
    PAD 1 @ 1
    EC_SPI_SI SPI_SI IT3
    RE47 1 CZL@ 2 0_0402_5% PAD 1 @ CE20 SYSON EMC_NS@ CE13 1 2 0.1U_0201_6.3V6-K
    SPI_SI {8} IT4
    GPG2 RE44 2 CZL@ 1 10K_0402_5% PAD 1 @ 1U_0402_6.3V6K
    IT5 BATT_TEMP EMC_NS@ CE16 1 2 100P_0402_50V8J 1
    RE46 2 STN@1 10K_0402_5% EC_SPI_SO RE48 1 CZL@ 2 0_0402_5% SPI_SO 2
    SPI_SO {8}
    ACIN# EMC_NS@ CE17 1 2 100P_0402_50V8J CE19
    KSI7 PAD 1 @
    A
    when mirror, GPG2  pull high EC_SPI_CLK RE49 1 CZL@ 2 0_0402_5% SPI_CLK KSI6 PAD 1 @
    IT6
    ON/OFF EMC_NS@ CE18 1 2 1U_0402_6.3V6K 2
    0.1U_0201_6.3V6-K A

    when no mirror, GPG2 pull  low SPI_CLK {8} WRST# PAD 1 @


    IT7 for VR_APU_PWRGD undershoot issue EMC_NS@
    IT8

    EMC

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 EC ITE8586LQFP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 35 of 50
    5 4 3 2 1
    5 4 3 2 1

    ON/OFF switch
    +3VL +3VALW
    JKB1

    2
    32 33
    R82
    100K_0402_5%
    R83
    100K_0402_5% R268 1 2 0_0402_5%
    K/B Connector R269 1 2
    ON/OFFBTN# 31
    30
    32 GND1
    31 GND2
    34
    {35} NUM_LED# PWR_NUM_LED 30
    +3VS R87 1 2 0_0402_5%
    300_0402_5% 29
    KSO17 28 29

    1
    D15 NOVO_BTN# KSI[0..7] KSO16 27 28
    @ KSI[0..7] {35} 27
    NOVO# 2 KSI1 26
    {35} NOVO# 1 NOVO_BTN# KSO[0..17] 26
    @ KSI7 25
    KSO[0..17] {35} 25
    ON/OFF R85 1 2 0_0402_5% 3 KSI6 24
    check based on 14',15' 24

    2
    KSO9 23
    keyboard pindefine 23

    1
    LBAT54CWT1G_SOT323-3 SW5 KSI4 22
    D29 KSI5 21 22
    D @

    1
    D
    AZ5123-01F.R7GR_DFN1006P2X2 KSO0 20 21
    EVQP7L01K SPST EMC@ KSI2 19 20
    KSI3 18 19
    KSO5 17 18

    4
    +3VALW +3VL 17

    2
    KSO1 16
    KSI0 15 16

    2
    KSO2 14 15
    14

    2
    KSO4 13
    R111 R114 EMC_NS@ KSO7 12 13
    100K_0402_5% 100K_0402_5% PWR_CAPS_LED C133 1 2 100P_0201_25V8J KSO8 11 12
    @ CAPS_LED# NUM_LED# ON/OFFBTN# KSO6 10 11
    PWR_NUM_LED C134 1 2 100P_0201_25V8J +3VS KSO3 9 10

    1
    @ KSO12 8 9
    ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF EMC_NS@ KSO13 7 8
    ON/OFF {35} 7

    2
    KSO14 6
    D23 D22 D30 R84 KSO11 5 6

    1
    J5 1 2 @ AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 KSO10 4 5
    0_0402_5% 4
    EMC@ EMC@ EMC_NS@ KSO15 3
    3
    SHORT PADS
    {35} CAPS_LED# R270 1 2 2

    1
    PWR_CAPS_LED 300_0402_5% 1 2
    1

    2
    J6 1 2 @ EMC@
    CAPS_LED# C117 1 2 100P_0201_25V8J

    2
    SHORT PADS CVILU_CF32321D0RONH
    NUM_LED# C118 1 2 100P_0201_25V8J ME@

    EMC_15@ For EMC

    +5VS TP_PWR TP_CLK

    C R160 1 @ 2
    TP/B Connector TP_DATA PWR/B Connector C
    USB I/O Connector

    2
    +3VS 0_0402_5%

    a
    @ JTP1 DT1
    R141 1 2 1
    TP_CLK 2 1

    EMC_NS@
    0_0402_5%
    {35} TP_CLK TP_DATA 2
    3
    {35} TP_DATA 3
    1 4
    TP_Left 5 4
    100P_0402_50V8J

    100P_0402_50V8J

    1 1 5

    hu
    TP_Right 6 7
    EMC_NS@

    EMC_NS@

    C114
    6 GND1 8
    0.1U_0201_6.3V6-K GND2 1
    2
    2 2
    C115

    C116

    ACES_50503-0060N-001 C1105
    U23
    ME@ AZC199-02S.R7G_SOT23-3 0.01U_0201_6.3V7-K

    1
    1 2
    GND
    EMC 1
    LID_SW#
    EMC 3
    OUTPUT LID_SW# {35}
    C1104
    0.01U_0201_6.3V7-K

    1
    2 2
    TP_LEFT Button TP_Left VCC D17

    1
    AZ5123-01F.R7GR_DFN1006P2X2
    R267 1 +VCC_LID
    2 0_0402_5% AH9247-W-7_SC59-3 EMC_NS@

    g.
    +3VL
    1

    2
    SW2
    EVQPLHA15_4P
    A

    A1

    GND2 GND1

    2
    DT3
    1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    For EMC
    B1
    B

    15@
    2
    3

    an
    TP_RIGHT Button TP_Right
    1

    B B
    1

    SW4
    EVQPLHA15_4P
    A

    A1

    GND2 GND1

    DT5
    1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    B1

    Hu
    B

    15@
    3

    EMC
    For 14" For 15"

    LED PWR_LED# LED1 1 2 R142 1 2 1.5K_0402_5%


    {35} PWR_LED# +5VALW
    1

    L-C192WDT-LCFC_WHITE
    D31
    1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    r
    2
    2

    BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%


    {35} BATT_LOW_LED# +3VALW
    Fo
    1

    L-C192JFCT-LCFC_SUPER_AMBER
    D32
    1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    2

    A A
    2

    BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%


    {35} BATT_CHG_LED# +5VALW
    1

    L-C192WDT-LCFC_WHITE
    D33
    1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@

    Security Classification LC Future Center Secret Data Title


    2

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 KBD/PWR/IO/LED/TP Conn.


    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 36 of 50
    5 4 3 2 1
    A B C D E

    +5VLP +5VALW
    Load Switch
    +5VALW To +5VS +3VS, C173 ‐‐> 2.74ms
    +3VALW To +3VS +5VS, C176 ‐‐> 2.03ms

    1
    R156 R157 VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
    100K_0402_5% 100K_0402_5% R4 1 @ 2 0_0402_5% 3VSON +3VALW +3VS
    @ U13 J11 @
    1 1 14 +3VS_LS 1 2 1

    2
    2 IN1_1 OUT1_2 13 1 2
    SUSP IN1_2 OUT1_1 JUMP_43X118
    {25} SUSP 1 1
    3VSON 3 12 C173 1 2 2200P_0201_25V7-K
    SUSP# R2 1 @ 2 0_0402_5% 5VSON C178 EN1 CT1 C175
    1U_0402_6.3V6K 4 11 0.1U_0201_6.3V6-K
    2 +5VALW VBIAS GND 2
    @ 1000P_0201_50V7-K @

    1
    Q6 D 1 1 5VSON 5 10 C176 1 2
    2 +5VALW EN2 CT2 +5VS
    {35,46,47} SUSP# G C180 C179 6 9 J12 @
    1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 +5VS_LS 1 2
    L2N7002KWT1G_SOT323-3 S 2 2 IN2_2 OUT2_1 1 2

    3
    1 15 JUMP_43X118 1
    GPAD
    Need Short
    C177 G5016KD1U_TDFN14_2X3 C174
    1U_0402_6.3V6K 0.1U_0201_6.3V6-K
    2 @ 2 @

    +1.8VALW to +1.8VS AON6414AL


    VDS=30V VGS=20V, ID=50A,
    AON7408L_DFN8-5 Rds=8mohm @ VGS=10V +0.95VALW to +0.95VS AON6414AL
    +1.8VALW Q39 +1.8VS +/- 5% 1.5A VGS(th)=2.5V Max VDS=30V VGS=20V, ID=50A,
    +/- 2% Q41 Rds=8mohm @ VGS=10V
    2
    +0.95VALW +0.95VS +/-5% 3.6A VGS(th)=2.5V Max
    2
    +/- 1.5%

    a
    1 AON6414AL_DFN8-5
    2 1 1
    1 5 3 1
    C141 C140 C142 2 1 1

    hu
    10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M 1 5 3

    1
    @ 2 2 C146 C145 C147
    4

    2 R213 @ 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M

    1
    470_0603_5% @ 2 2

    4
    2 R188 @
    470_0603_5%

    2
    R206

    2
    R211 R194 2 1 1.8VS_GATE

    g.
    1.8VS_GATE_R 1.8VS_GATE 2
    1
    @
    2 1
    @
    2 R214 1
    470K_0402_5% V20B+ R193
    @ 0_0402_5%

    0.95VS_GATE_R 1 20.95VS_GATE 2
    0_0402_5% 0_0402_5% 2 1 R190 R189 1
    V20B+
    1

    1
    1 D Q45 Q46 D @ 0_0402_5% 470K_0402_5%
    C143 R212 2 SUSP 2 0_0402_5% @ @

    1
    0.01U_0201_25V6-K 820K_0402_5% G G 1 D Q37 Q40 D
    C144 R187 2 SUSP 2
    2 S L2N7002KWT1G_SOT323-3 S
    L2N7002KWT1G_SOT323-3 0.01U_0201_25V6-K 820K_0402_5% G G
    2

    an
    @ 2 S L2N7002KWT1G_SOT323-3 S
    L2N7002KWT1G_SOT323-3

    3
    @ @ @
    3 3

    +3VALW to +3VALW_APU +3VALW


    Need Short +3VALW_APU For DisCharge

    Hu
    J7 @
    1 2 +0.675VS
    1 2

    JUMP_43X79

    1
    Id=3.2A R159
    47_0603_5%
    LP2301ALT1G_SOT23-3
    @

    2
    S

    Q29 3 1

    1
    D
    r
    1 1 Q8
    2 SUSP
    G
    2

    C129 C130 G
    0.1U_0201_6.3V6-K 0.01U_0201_6.3V7-K
    2 @ 2 @ S L2N7002KWT1G_SOT323-3
    Fo

    3
    {35} PCH_CMOSP R158 1 @ 2 0_0402_5%
    1

    4 4
    1
    R164 C131
    100K_0402_5% 0.1U_0201_6.3V6-K
    2 @
    @
    Security Classification LC Future Center Secret Data Title
    2

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 DC V TO VS INTERFACE


    reserve to cut off APU 3VALW when clear CMOS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 37 of 50
    A B C D E
    5 4 3 2 1

    EC_APU_ALWEN 1 +0.775VALW

    V V
    PU604 Compare
    UC4
    APUALW_PWRGD 2 V V QC1/QC2/QC3/QC4
    PU603 PU601
    A3 ACIN#
    V

    V
    D D

    AC A1 +VDDCR_FCH_S5
    APU_S5_MUX_CTRL
    MODE VIN +0.95VALW +1.8VALW
    A2 A5 B5
    V V
    PU301 +3VALW

    V
    B+
    BATT B2 PU401 A5 B5
    V V V
    BATT 3
    MODE ALW_PWRGD EC_RSMRST#
    B1

    V
    V +APU_CORE_NB

    V V
    EC 4 PBTN_OUT#
    EC_ON A4

    V
    +APU_CORE
    PM_SLP_S3#
    B4 5
    PM_SLP_S5# APU

    V
    VR_GFX_PWRGD

    V V
    10 EC_SYS_PWRGD

    a
    +APU_GFX
    PLT_RST# 11
    B3

    V
    A5

    hu
    ON/OFF 12 VVVVV
    KBRST#
    B5 V

    V
    C C

    PXS_PWREN
    V
    SYSON 6 PU501
    +VSYSMEM

    g.
    +5VALW +3VGS

    V
    QV6

    V
    7
    V SUSP#,SUSP
    U13 +1.35VGS

    V
    an
    SUSP# 6 U13

    V
    +3VS QV9
    V

    +5VS

    PU10 +1.8VGS

    V
    +1.5VS QV2

    Hu
    PU501
    V

    VGA
    +0.675VS
    Q39 +0.95VGS

    V
    +1.8VS QV3

    +VGA_CORE

    V
    B B

    Q41

    V
    PU701
    +0.95VS
    r
    Fo
    VGA_PWRGD
    VDDGFX_PD
    8
    EC_GFX_ON V +APU_GFX
    V

    PU901
    +APU_GFX

    8 VR_GFX_PWRGD

    EC_VR_ON
    +APU_CORE
    V

    PU801
    +APU_CORE

    +APU_CORE_NB
    V

    A PU801 A
    +APU_CORE_NB

    9
    VR_APU_PWRGD

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power sequence Block


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 38 of 50
    5 4 3 2 1
    5 4 3 2 1

    ZZZ1

    PCB PN
    DAZ11X00100

    UC2 UC2 UC2


    D D
    HDMI@
    ZZZ8

    AMD A8-7410 2.2G 2M 4cBGA APU AMD A6-7310 2.0G 2M 4cBGA APU AMD A4-7210 1.8G 2M 4cBGA APU
    A8@ A6@ A4@
    SA000077R10 SA000074420 SA00007AS00 HDMI PN
    RO00000040J
    HDMI
    UC2
    UC2

    APU type

    AMD E2-7110 1.8G 2M 4cBGA APU


    E2@ AMD E1-7010 1.5G 1M 2cBGA APU
    SA000074820 E1@
    SA000074520

    a
    hu
    ZZZ2 ZZZ3 ZZZ4

    C C

    Hynix Samsung MICRON


    H4GX4@ S4GX4@ M4GX4@
    X7610712002 X7610712001 X7610712003

    g.
    VRAM ID config
    UV5 H4G@ UV6 H4G@ UV7 H4G@ UV8 H4G@ RV70 H4G@

    VRAM ID PU resistor PD resistor


    Memory Type
    PS_3[3:1] RV63 RV70

    an
    H5TC4G63CFR-N0C 4Gb H5TC4G63CFR-N0C 4Gb H5TC4G63CFR-N0C 4Gb H5TC4G63CFR-N0C 4Gb 4.75K_0402_1%
    SA00007DU10 SA00007DU10 SA00007DU10 SA00007DU10 SD03447518J
    VRAM_Hynix_256M*16 000 NA 100 4.53K 4.99K

    UV5 M4G@ UV6 M4G@ UV7 M4G@ UV8 M4G@ RV63 M4G@ RV70 M4G@ 128Mx16
    NA 111 4.75K NC

    Hu
    MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N4.53K_0402_1% 2K_0402_1% NA 110 3.4K 10K
    SA00007QJ00 SA00007QJ00 SA00007QJ00 SA00007QJ00 SD03445318J SD03420018J

    VRAM_Micron_256M*16 010
    Hynix
    000 NC 4.75K
    B H5TC4G63CFR-N0C 4Gb 900(1G) B
    UV5 S4G@ UV6 S4G@ UV7 S4G@ UV8 S4G@ RV63 S4G@ RV70 S4G@
    r
    Micron
    256Mx16 010 4.53K 2K
    MT41J256M16LY-091G:N 4Gb 900(1G)

    K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb K4W4G1646E-BC1A 4Gb 8.45K_0402_1% 2K_0402_1%
    Fo
    SA000063F20 SA000063F20 SA000063F20 SA000063F20 SD000011R00 SD03420018J Samsung
    001 8.45K 2K
    VRAM_Samsung_256M*16 001 K4W4G1646E-BC1A 4Gb 900(1G)

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Virtual symbol
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 39 of 50
    5 4 3 2 1
    5 4 3 2 1

    H1 H2 H3 H4
    HOLEA HOLEA HOLEA HOLEA

    1
    pad_ct8p0d2p3
    D pad_ct8p0b6p0d2p3pad_ct8p0b6p0d2p3 pad_ct8p0b6p0d2p3 D

    @ @ @

    H16 H18
    HOLEA HOLEA

    H5 H6 H7 H8 H9 H10
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    1
    1

    1
    PAD_C2P8D2P8N PAD_O3P3X2P8D3P3X2P8N
    @ @
    CHASSIS1_GND
    pad_c8p0d2p3 pad_c8p0d2p3 pad_c8p0d2p3 pad_c8p0d2p3 pad_c8p0d2p3 pad_c8p0d2p3
    @ @ @ @ @ @

    a
    H11 H12 H13 H14 H15
    HOLEA HOLEA HOLEA HOLEA HOLEA
    C C

    hu
    1

    1
    PAD_C6P0D3P7 PAD_C6P0D3P7 PAD_C6P0D3P7 PAD_C6P0D3P7 pad_ct8p0b6p0d3p2
    @ @ @ @ @

    g.
    an
    PCB Fedical Mark PAD
    FD1 FD2 FD3 FD4 FD5 FD6

    Hu
    B B
    1

    @ @ @ @ @ @
    r
    +VGA_CORE +3VS
    Fo
    For EMC

    1 1
    C168 C169
    0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    2 @ 2 @

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/08 Deciphered Date 2013/08/05 Hole
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG521
    Date: Wednesday, February 24, 2016 Sheet 40 of 50
    5 4 3 2 1
    5 4 3 2 1

    B+
    +5VLP/ 100mA
    Silergy
    D SY8286BRAC +5VALW/5A
    D

    Adaptor Converter
    EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

    +3VLP/ 100mA
    Silergy
    SY8286CRAC
    Converter +3VALW/4A Silergy
    SY8033BDBC
    EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
    Converter +1.8VALW/2.3A
    FOR APU VDDIO
    EC_APU_ALWEN EN PGOOD

    a
    MPS +1.35V/11A ANPEC
    NB685GQ-Z APL5701-ABI-TRG

    hu
    +0.75VSP/200mA
    C O2 SYSON S5 Converter LDO C

    SUSP# S3 +0.675VS/1.3A FOR APU VDDIO


    OZ8682LN_QFN16_3X3 FOR DDR EC_APU_ALWEN EN PGOOD

    Battery Charger PGOOD GMT


    Switch Mode G918T12U +1.5VSP/150mA

    g.
    LDO
    FOR APU VDDIO
    SUSP# EN PGOOD
    Bayhub
    BH5321LN APU Core/22A/35A
    Switch Mode

    an
    SMBus APU Core NB/12A/17A
    FOR APU/NB Core
    EC_VR_ON EN PGOOD VR_APU_PWRGD
    PGOOD_NB

    Hu
    Battery Silergy
    Li-ion SY8288RAC
    B
    4S1P/32WH,41WH Converter +0.95VS/7.68A B

    FOR APU VDD


    EC_APU_ALWEN EN PGOOD APUALW_PWRGD
    r
    Fo
    Richtek
    RT3662EBGQW
    Switch Mode +VGA_CORE/21A
    VIDs
    PXS_PWREN EN FOR GPU VDDC PGOOD VR_VGA_PWRGD

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 Power Diagram
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GAMDFP4
    Date: Wednesday, February 24, 2016 Sheet 41 of 50

    5 4 3 2 1
    5 4 3 2 1

    @
    PJ101
    2 1
    2 1
    VIN PR9408 maybe adjust value
    JUMP_43X79 +3VL PR103 0_0603_5%
    PL707 EMC_NS@ 1 2
    JDCIN1 HCB2012KF-121T50_0805 @ +VCCRTC
    1 APDIN 1 2
    1 2 PD707
    PR101 0_0603_5%
    GND1 3 PL708 EMC_NS@ 1 2 3
    GND2 4 RTC_VCC

    470P_0402_50V7K

    470P_0402_50V7K
    HCB2012KF-121T50_0805
    GND3 5

    1000P_0402_50V7K

    1000P_0402_50V7K
    1 2 1
    GND4 6 JRTC1
    GND5 7

    1
    For EMI request

    PC101

    PC102

    PC103

    PC104
    D 1 1 PR102 2 BAT_D 2 2
    D
    GND6 1 2
    2 3 1K_0603_5% PC2

    2
    HIGHS_PJSS0026-8B01H G1 4 change to 1K SD01310018J BAT54CW_SOT323-3 1U_0402_10V6K
    G2 1
    ME@
    EMC@ EMC@ ACES_50273-0020N-001
    EMC@ EMC@
    ME@

    a
    hu
    C C

    g.
    an
    B

    Hu B
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/02/27 Deciphered Date 20140213 DCIN / RTC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CGx20
    Date: Wednesday, February 24, 2016 Sheet 42 of 50
    5 4 3 2 1
    5 4 3 2 1
    @
    PJ202
    2 1
    2 1
    VMB
    JUMP_43X79
    JBATT2 ME@
    SUYIN_125022HB008M200ZL PL201
    1 HCB2012KF-121T50_0805
    1 2 1 2
    2 3 EC_SMCA BATT+
    9 EMC_NS@
    10 GND1 3 4 EC_SMDA PL202
    11 GND2 4 5 HCB2012KF-121T50_0805
    12 GND3 5 6 1 2
    GND4 6 7

    1
    EMC_NS@
    7 8

    1
    100_0402_1%

    100_0402_1%
    PC201 PC202
    8 0.01U_0402_25V7K

    PR201

    PR202
    1000P_0402_50V7K

    2
    D D

    EC_SMB_CK1 {35,44}

    EC_SMB_DA1 {35,44}
    PR203
    1 2 +3VALW
    100K_0402_1%

    PR204
    BATT_TEMP_IN 1 2
    10K_0402_5%
    BATT_TEMP {35} A/D
    1

    PD206
    1

    a
    2
    2

    AZ5215-01F_DFN1006P2E2

    hu
    C C
    3

    EC_SMCA
    Reverse PD205 For EMI request

    g.
    EC_SMDA

    PD205
    AZC199-02S.R7G_SOT23-3
    @

    an
    1

    Hu B
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/02/27 Deciphered Date 20140213 BATTERY CONN/OTP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CGx20
    Date: Wednesday, February 24, 2016 Sheet 43 of 50
    5 4 3 2 1
    5 4 3 2 1

    V20B+
    P2 P3
    PQ309 For EMI request BATT+ PQ303 V20B+
    PQ301 PQ302 AON7408L_DFN8-5 PL302 PR316 AO4407AL_SO8
    AO4407AL_SO8 SI4483ADY-T1-GE3_SO8 PR301 0.01_1206_1% 8 1
    8 1 1 8 0.01_1206_1% PL301 1 6.8UH_PCMB063T-6R8MS_4.5A_20% 7 2
    7 2 2 7 HCB2012KF-121T50_0805 2 LX_CHG 1 2 CHG 1 4 6 3
    VIN 6
    5
    3 3 6
    5
    1 4 1 2 5 3
    2 3
    5

    2
    0.1U_0603_25V7-M

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    0.1U_0402_25V6
    2 3 EMC@ PQ311

    4
    2200P_0402_50V7K
    @

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    4

    4
    2

    2
    PC330

    PC304

    PC331
    AON7408L_DFN8-5 4.7_0805_5%

    2
    PR317

    PC305

    PC306

    PC307

    PC319

    PC340

    PC341

    PC320
    PC301 PC302 PC303
    D D
    PQ304 1 2 10U_0805_25V6K 10U_0805_25V6K

    16251_SN 1

    1
    1

    0.1U_0603_25V7-M
    @ @ 4

    1
    1
    PR302 LTA044EUBFS8TL_UMT3F-3 100P_0402_50V8J

    2
    200K_0402_5% PR303 @ PR304
    @ @ VIN

    PC308
    200K_0402_1% @ PC317 1 2
    PU301 2 1
    2

    3
    2
    1

    2ACOFF-1
    2 OZ8682LN_QFN16_3X3 PC321 47K_0402_1%

    2
    1P2_G2

    1SS355_SOD323-2
    DH_CHG 13 14 0.47U_0603_25V6-K 680P_0402_50V7K

    DISCHG_G-1
    HDR LX @ PR305

    2
    ICHP 5 16 DL_CHG PR312 10K_0402_1%
    ICHP LDR

    2
    0_0603_5% PD301
    ICHN 4 12 BST_CHG 1 2 PR306
    1

    1
    ICHM BST 200K_0402_1%
    P2-1 PR315 1 2 0_0402_5% 737_SDA 11 1 VCC PD303
    {35,43} EC_SMB_DA1 SDA VAC
    2 RB751V-40_SOD323-2

    1
    PQ305 PR313 1 2 0_0402_5% 737_SCL 10 15 VDDP 2 1 PQ308B
    {35,43} EC_SMB_CK1 SCL VDDP

    4
    S
    LTC015EUBFS8TL_UMT3F-3 L2N7002KDW1T1G_SOT363-6
    {35} ADP_I
    P2_G1

    ADP_I PR340 1 2 0_0402_5% IAC 7 3 IACM PC315 PD302


    IACM PR341 IAC IACM G
    5PACIN_N 1 2 PACIN_P
    CHARGER_GND 4.7U_0603_10V6-K
    3

    2
    2
    1 2 1 2 8 2 IACP
    COMP IACP D

    BASE
    IACP PC318 PC334 0_0402_5%
    1SS355_SOD323-2

    3
    100P_0402_50V8J 0.47U_0402_25V6K VDDP 1 2 6 9 PACIN 1 2 ACIN {35}

    1
    VDDA ACAV
    6

    PQ307A D PR327

    1
    2 PR307 PR342 10K_0402_1%

    17

    6
    1M_0402_5%
    G 68K_0402_1% 100_0402_5% PC333 D

    1
    PR347
    L2N7002KDW1T1G_SOT363-6 CHARGER_GND 1U_0603_25V6M PR343 PC313 2 PACIN

    2
    S 100K_0402_5% PC332 PC324 0.1U_0603_25V7-M G
    1

    CHARGER_GND 1000P_0402_25V7-K 0.1U_0603_25V7-M

    2
    ICHP @ S PQ308A

    1
    L2N7002KDW1T1G_SOT363-6
    P2-2

    ICHN
    3

    PR309 D PQ307B PJ301


    PACIN 1 2 5 1 2
    PACIN_G

    G
    47K_0402_1% L2N7002KDW1T1G_SOT363-6 JUMPER

    a
    C S @ C
    4

    CHARGER_GND

    hu
    1

    PQ315 D
    PR314 2
    1 2ACOFF-1 G
    {35} ACOFF
    0_0402_5% S L2N7002KWT1G_SOT323-3 VIN
    3
    1

    PR349
    1M_0402_5%

    g.
    PD309
    2

    1SS355_SOD323-2

    2 1
    PR308
    20_0603_5%

    1
    VCC

    an 1
    PC314
    0.47U_0603_25V6-K

    2
    B B

    Hu
    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2015/02/27 Deciphered Date 20140213 CHARGER
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CGx20
    Date: Wednesday, February 24, 2016 Sheet 44 of 50
    5 4 3 2 1
    5 4 3 2 1

    V20B+
    @

    2
    PJ401
    1
    1.5A +3VIN
    2 1

    1M_0402_5%
    0.1U_0402_25V6
    1

    1
    D D

    PR401
    10U_0805_25V6K
    PC403

    PC401

    PC402
    JUMP_43X79 +3VBS 1 2

    2
    0.1U_0603_25V7-M

    1
    @ 21 +3VALW

    BS
    IN5

    IN3

    IN2

    IN1
    EMC_NS@ GND4
    +3VLX 6
    LX LX3
    20
    PL401
    @
    PJ402
    5A
    7 19 +3VLX 1 2 +3VALW_P 2 1
    GND1 LX2 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    8 18
    100mA +3VLP
    GND2 GND3

    1
    JUMP_43X79
    +3V_PWRGD

    PC404

    PC405

    PC406

    PC407
    9 17 PR403
    PG LDO 4.7_0805_5%

    2
    10 16 EMC_NS@
    NC1 NC3

    1
    OUT

    NC2

    1 2
    EN2

    EN1
    PC409

    FF
    4.7U_0603_6.3V6K @

    2
    SY8286BRAC_QFN20_3X3 PC410

    +3VIN 11

    12

    13

    14

    15
    PTP401 680P_0402_50V7K
    PU401

    2
    PAD EMC_NS@

    +3VALW_P
    PR402 PR414
    EC_ON_R

    +3VFB
    1 2 1 2
    {35} EC_ON
    0_0402_5% 0_0402_5%

    a
    @

    0.1U_0402_25V6
    @
    PC411
    1

    1M_0402_5%
    PC408
    PR405
    {30} EC_ON_R

    PR404
    1 2 1 2

    hu
    2

    PR417 1000P_0402_25V7-K 1K_0402_1%


    2 1

    2
    {35} MAINPWON 0_0402_5%
    2

    C @ C
    PR429
    330_0603_5%
    @
    +3VL
    1

    +3VLP
    1

    g.
    PQ405 @
    1

    2 PJ404
    PR427 G PC425 2 1
    100K_0402_5% 2.2U_0603_10V7K 2 1
    2

    @ S @
    3

    2N7002KW_SOT323-3 JUMP_43X39
    2

    @ +3VALW

    2
    an
    PR406
    100K_0402_5%

    PR407 @

    1
    +3V_PWRGD 1 2
    ALW_PWRGD {47}
    V20B+ 0_0402_5% @
    @
    PU402
    2
    PJ405
    1
    2.5A 5V_VIN 5 9 +5V_PWRGD 1
    PR408
    2

    Hu
    2 1 4 IN1 PG 1 +5VBS 1 2
    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    IN2 BS
    1

    +5VALW
    PC413

    PC414

    3 PC415 0_0402_5% @
    IN3
    PC412

    JUMP_43X79 2 0.1U_0603_25V7-M
    IN4 6
    5A
    2

    7 LX1 19 PL402 PJ406


    8 GND1 LX2 20 +5VLX 1 2 +5VALW_P 2 1
    18 GND2 LX3 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    GND3

    1
    EMC_NS@ 21 PR413
    GND4

    1
    PR409 14 +5VALW_OUT1 2+5VALW_P PR410 JUMP_43X79
    EC_ON_R +5VALW_EN OUT 4.7_0805_5%

    PC417

    PC418

    PC419

    PC420
    1 2 12
    5V_VIN 11 EN1 13 +5VFB 0_0402_5% EMC_NS@ @

    2
    B EN2 FF B
    0_0402_5% 100mA

    2
    15
    10 LDO +5VLP
    NC1

    1
    1M_0402_5%

    16 17 +5V_VCC
    4.7U_0603_6.3V6K
    r
    NC2 VCC
    1

    PC423
    1

    680P_0402_50V7K
    PR411

    PC422
    1U_0603_25V6M

    SY8286CRAC_QFN20_3X3 2
    1

    @ PC421 EMC_NS@
    2

    0.1U_0402_25V6
    PC430
    2

    Fo
    2

    PC424
    PR412
    1 2 1 2

    1000P_0402_25V7-K 1K_0402_1%

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/08 Deciphered Date 2013/08/05 PWR_3VALW/5VALW


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CGx20
    Date: Wednesday, February 24, 2016 Sheet 45 of 50
    5 4 3 2 1
    A B C D

    V20B+ @ 2A
    PJ501
    2 1 1.35V_B+
    2 1

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    1

    1
    EMC@
    PC503

    PC504

    PC505
    @
    JUMP_43X79 PJ502
    2 1

    2
    1

    PR506 0.1U_0603_25V7-M 2 1 1

    PU501 0_0603_5% PC506 JUMP_43X118


    1 10 BST_1.35V 1 2 2 1 0.68UH_PCMB063T-R68MN_16A_20%
    VIN BST PL501 PJ503
    9 LX_1.35V 1 2 1.35V_L 2 1
    SW 2 1
    +1.35V

    NB685GQ-Z_QFN16_3X3
    S3_1.35V 16
    PR503 EN1

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    JUMP_43X118
    {35} SYSON 2 1 S5_1.35V 15 13 1.35V_FB @ 220P_0402_50V7K @
    PR511 EN2 FB

    1
    EMC_NS@

    PC515

    PC516

    PC517

    PC518

    PC519
    2.2_0805_5%
    2 1 2 1
    1A DIS ------10A

    PR508
    {35,37,47} SUSP# 2 1 0_0402_5% 1M_0402_5% PC510
    +3VALW 1.35V_L

    0.1U_0402_10V7K

    0.1U_0402_10V7K
    2 1 12 6
    @
    +0.675VSP PR513 @

    2
    0_0402_5% PR502 100K_0402_1% PG VDDQ

    2
    PC501 @

    PC502
    DDR_3V3 3 @

    2
    3V3

    41.2K_0402_1%
    1U_0402_6.3V6K
    @ 5

    1.35V_SN
    VTT

    PR509
    PR512

    2
    1200P_0402_50V7-K
    PC509
    4.7_0402_5%
    4 1K_0402_1%
    AGND

    PR507 2
    8
    VTTS

    EMC_NS@
    2

    1
    PGND

    PC512
    7 VTTREF
    VTTREF @
    @

    1
    1
    Mode 14 11 PJ504

    1
    MODE OTW#

    1U_0402_6.3V6K
    PC508 +0.675VSP 2 1 +0.675VS
    10U_0603_6.3V6M 1.35V_FB 2 1

    2
    2

    PC511
    1.35V_GND

    a
    +3VALW PR504 JUMP_43X79

    1
    0_0402_5%

    2
    PR510
    32.4K_0402_1%

    hu
    1
    1.35V_GND

    2
    1.35V_GND
    2 2

    1.35V_GND

    g.
    PJ505
    1 2

    an
    JUMPER
    @

    1.35V_GND

    Hu 3
    r
    Fo

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2015/02/27 Deciphered Date 2013/08/05 1.35VS/+0.675VS


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG510
    Date: Wednesday, February 24, 2016 Sheet 46 of 50
    A B C D
    A B C D

    PL601
    PJ601 PU601 1UH_PH041H-1R0MS_3.8A_20% PJ609
    2 1 1_8VS_PVIN 3 6 1.8VS_LX 1 2 2 1
    +3VALW 2 1 IN LX
    +1.8VSP
    2 1 +1.8VALW

    22U_0805_6.3V6M
    .1U_0402_10V6-K
    JUMP_43X79 5 1 JUMP_43X79
    NC FB

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    PC601

    0.1U_0402_25V6
    @ @
    +1.8VALW

    1
    PC602
    7 PR602 PR606 PC611
    EN

    PC604

    PC605

    PC606

    PC607
    4.7_0603_5% 200K_0402_1% 22P_0402_50V8-J

    2
    4 2 EMC_NS@
    TDC :2.3A

    2
    9 PGND1 PG

    1 2

    1
    EMC@ PGND2 8
    PR603 SGND OCP :3.8A
    0_0402_5% SY8003DFC_DFN8_2X2 PC609
    ALW_PWRGD 1 2 EN_1.8VSP 680P_0402_50V7K

    2
    @ EMC_NS@ EMC@

    2
    PR604
    PR605

    1
    1 1M_0402_5% PC608 1

    1
    EC_APU_ALWEN 2 1 .1U_0402_10V6-K
    @ PR607

    2
    0_0402_5% 100K_0402_1%

    a
    +1.5VS
    TDC :50mA

    hu
    change to G918T12U
    SA000078700
    2 2

    +1.5VSP +1.5VS
    50mA
    50mA

    g.
    PJ603 PU602 PJ604
    2 1 3 4 2 1
    +3VALW 2 1 VIN VOUT 2 1
    4.7U_0603_6.3V6K

    1
    2
    JUMP_43X39 GND JUMP_43X39 @
    PC612

    5
    SET

    1
    1 PR608
    2

    @ SHDN 21.5K_0402_1% PC613 PC614


    220P_0402_50V7K 10U_0603_6.3V6M
    G918T12U SOT-23 5P

    2
    PR609
    @
    2 1EN_1_5VSP
    {35,37,46} SUSP#

    an
    0_0402_5%
    VFB=0.8V
    1

    1
    PC615 PR610
    .1U_0402_10V6-K 24K_0402_1%
    2

    Hu
    +3VALW
    1

    PR624
    10K_0402_5%
    2

    3 3

    {35,50} APUALW_PWRGD
    V20B+
    PJ605 PU603
    r
    2 1 VIN_+0.95VALW 2 9
    2 1 IN1 PG
    0.1U_0603_25V7-M
    +0.95VALW
    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6

    3 PC619 @
    IN2
    1

    JUMP_43X79 4 1 +0.95VALW_BS 1 2 0.68UH_PCMB063T-R68MN_16A_20%


    IN3 BS PJ607
    1
    PC634

    PC638

    PC610

    @ EMC@ 5 PL602
    IN4 +0.95VALW_LX +0.95VALW_L
    SY8288RAC_QFN20_3X3

    6 1 2 2 1
    2

    LX1 2 1
    Fo
    7 19
    2

    8 GND1 LX2 20
    GDN2 LX3 JUMP_43X118
    1

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M

    22U_0805_6.3V6M
    100K_0402_5% 18
    GND3

    1
    330P_0402_50V8J
    @ PR623

    PC635

    PC639

    PC636

    PC637
    PR614 14 2.2_0805_5%
    FB
    PC618
    1 2 +0.95VALW_ILNT 13
    +3VALW EMC_NS@

    2
    ILMT
    1
    1 2
    1

    PR616 +0.95VALW_EN
    11 17 +0.95VALW_LDO
    2 2
    +1.0VALW
    EN VCC

    1
    1M_0402_5% PC640
    1

    @ 10 1200P_0402_50V7-K PR613
    TDC :7.68A
    2

    15 NC1 12 20K_0402_1%
    +3VALW EMC_NS@ PR618
    2

    BYP NC2 16 PC632 1K_0402_1%


    OCP :14A
    2

    NC3 21 4.7U_0603_6.3V6K
    2
    TP
    1

    PC627 +0.95VALW_FB
    4.7U_0603_6.3V6K
    2

    PR620
    33K_0402_1%
    2

    PR611
    0_0402_5%
    ALW_PWRGD 1 2
    {45} ALW_PWRGD
    @
    PR612
    EC_APU_ALWEN 2 1
    {35,50} EC_APU_ALWEN
    1

    0_0402_5%
    PC645
    .1U_0402_10V6-K
    2

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2013/08/15 Deciphered Date 2013/08/15 +1.35VS_VGA/+1.5VS


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GAMDFP4
    Date: Wednesday, February 24, 2016 Sheet 47 of 50
    A B C D
    5 4 3 2 1

    +VGA_B+
    PJ901
    2 1
    +5VALW 2 1
    V20B+
    JUMP_43X79
    @

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    PR901

    1
    PC901

    PC902

    PC903
    4.7_0603_5%

    5
    PX@
    +5VALW

    2
    +VGA_CORE

    AON6372_DFN
    D
    PU901
    +VDDIO_GPU D

    PQ901
    PC904 2.2U_0402_6.3V6M PC908 2.2U_0402_6.3V6M
    VGA_UGATE1 4 TDC :20A

    1
    PX@ VGA_VCC
    14 19 2 1 EMC_PX@ PX@ PX@
    VCC VDDIO OCP :35A

    1
    PR902 PR906 4.7_0402_5%
    0_0603_5% PX@ PX@
    PC909 PX@
    +VGA_B+

    3
    2
    1
    PR903 4.7_0402_5% PL901
    PX@

    2
    1 2 27 1 2 1 VGA_PHASE1 1 2
    PVCC VIN 1
    +VGA_CORE

    1.21K_0402_1%
    PX@

    1
    PX@ PC910 PX@ PR907 PX@ 0.22UH_SPS-06CZ-R22M-V1_23A_20%
    2.2U_0402_6.3V6M

    PR909

    330U_2.0V_M

    330U_2.0V_M

    330U_2.0V_M
    1U_0402_25V6-K 2.2_0603_5% PX@ 1 1 1

    2 PR911 1
    2

    4.7_0805_5%
    PR908 24.9K_0402_1% PR910 0_0402_5% 21 VGA_BOOT1
    1 2 VGA_BOOT1_R
    1 2
    VSEN

    EMC_PX@
    + + +

    PC906

    PC912

    PC913
    2 1 2 1 11

    AON6764_DFN

    AON6764_DFN
    SET1 PC907 56P_0402_50V8-J PC905 220P_0402_50V7K PC911 PX@ PX@

    2
    PQ902

    PQ903
    PX@ PR905
    PX@ 2 1 2 1 0.22U_0603_25V7K PC915 0.47U_0402_25V6K
    PH901 VGA_LGATE1 PX@ 2 2 2
    1PR904 21 2 4 4 2 1
    0_0402_5% 18.7K_0402_1% 2 1 PX@ PX@
    PX@ PX@ 3 2 1 2 1 2 1 @ PX@ PX@
    COMP

    2
    PX@
    PR915 100K_0402_1%_TSM0B104F4251RZ

    1
    PR916 0_0402_5% 4 PR912 60.4K_0402_1% PR913 10K_0402_1% PC917 300_0402_5% PC918

    VGA_ISEN1P

    +VGA_CORE
    3
    2
    1

    3
    2
    1
    2 1 2 1 2 PX@ 1 10 FB PC916 680P_0402_50V7K PR914
    PX@ PX@ @ PX@ 0.1U_0402_25V6

    1
    TSEN 2 EMC_PX@ PX@
    100P_0402_50V8J

    2
    66.5K_0402_1% PR917 60.4K_0402_1% RGND
    PX@ PX@
    PX@ PX@

    1
    PR919 PC931 @
    1PR918 21 2 0.1U_0402_25V6 PC930
    0_0402_5% 33.2K_0402_1% 22 0.1U_0402_25V6 2 1 PR920 10_0402_5%

    2
    NC VGA_BOOT1
    VREF PX@ PX@ 13 23 @ 1 2
    VREF_PINSET BOOT1
    1

    24 VGA_UGATE1 1 PX@ 2
    PR922 UGATE1

    a
    3.9_0402_1% 100K_0402_1%_TSM0B104F4251RZ 25 VGA_PHASE1 PR921 10_0402_5%
    PH902 PHASE1
    PX@
    PX@ 1 2 1 2 2 1 12 26 VGA_LGATE1 VGA_CORE_SEN {16}
    2

    IMON LGATE1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PR923
    PX@ 10.7K_0402_1% PR924
    1

    11K_0402_1% VGA_VSS_SEN {16}

    hu
    C PX@ C

    1
    PC932

    PC935

    PC936

    PC937

    PC925

    PC926

    PC927

    PC928
    PC919 PX@
    0.47U_0402_25V6K 7 VGA_ISEN1P
    2

    1 2 ISEN1P
    PX@

    2
    PR925 15.8K_0402_1% 8 +VGA_CORE
    ISEN1N
    PX@
    9 PX@ PX@ @ PX@ @ PX@ @ @
    {16} GPU_VR_HOT# VRHOT_L
    15
    {15} VGA_PWROK PWROK
    20 31
    {7,15} VR_VGA_PWRGD PGOOD BOOT2

    g.
    30
    UGATE2

    PR926 2 1 0_0402_5% 16 29
    {16} GPU_SVC SVC PHASE2

    28
    PR927 2 1 0_0402_5% 17 LGATE2
    {16} GPU_SVD SVD

    an
    PR928 2 1 0_0402_5% 18
    {16} GPU_SVT SVT

    2 PX@ 1 32 5 VGA_VCC
    {7,19} PXS_PWREN EN ISEN2P
    PR929
    150K_0402_5%
    2

    @ 33
    1 2 GND 6
    ISEN2N
    1

    PD901 PC923

    Hu
    RB751V-40_SOD323-2 .1U_0402_10V6-K
    PX@

    RT3662EBGQW_WQFN32_4X4
    B B
    PX@
    r
    Fo

    +3VGS
    2
    10K_0402_5%

    2
    10K_0402_5%

    10K_0402_5%
    PR938

    PR939

    PR940

    PX@
    VR_VGA_PWRGD 1

    PX@ PX@
    GPU_VR_HOT#

    A A
    VGA_PWROK

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG412
    Date: Wednesday, February 24, 2016 Sheet 48 of 50
    5 4 3 2 1
    5 4 3 2 1

    PR1144
    0_0402_5% CPU_B+
    PR1002 2 1 APU_VDDCORE_SEN_H {6}
    PR1160
    1.91K_0402_1% 51_0402_1%
    APU_RSP_LLA 1 2 APU_RSPA 1 2 1 PR1146 2 +APU_CORE
    10_0402_1%

    10U_0805_25V6K

    10U_0805_25V6K
    1

    1
    APU_VDD_SEN_L {6}

    0.1U_0402_25V6
    PC1147 PC1157 2 1

    1
    EMC@
    PC1001

    PC1003

    PC1002
    470P_0402_50V7K 1000P_0402_50V7K PR1143

    5
    PR1161 0_0402_5%
    2

    2
    51_0402_1%

    2
    APU_RSN 1 2 1 2

    AON6372_DFN
    1

    PQ1001
    PC1148 PR1148
    470P_0402_50V7K PC1158 10_0402_1% APU_GND APU_UGATE1 4
    1000P_0402_50V7K PR1162 PR1147
    PR1022
    2

    2
    51_0402_1% 10_0402_1%
    D APU_RSP_LLB 1 APU_RSPB +APU_CORE_NB D
    2 1 2 1 2 PC1004

    1
    22P_0402_50V8-J PR1001 PC1005

    3
    2
    1
    2.2_0603_5% 0.22U_0603_25V7K
    2.61K_0402_1% PR1145 APU_BOOT1 1 2 1 2

    2
    2 1
    APU_VDDNB_SEN_H {6} APU_CSPA 0.36UH 20% PDME064T-R36MS1R405_24A_20%
    APU_PHASE1 1 2
    0_0402_5% PL1001 +APU_CORE

    5
    1

    AON6764_DFN

    2
    PC1006

    AON6764_DFN
    PQ1002
    6800P_0402_25V7-K PR1005

    1
    PQ1003
    PR1004 APU_LGATE1 4 4.7_0805_5%

    330U_2.0V_M

    330U_2.0V_M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    4 PR1006

    330U_D2_2V_Y
    1 1 1

    2
    1.5K_0402_1% 43.2K_0402_1%

    1 1

    1
    + + +

    PC1008

    PC1009

    PC1010
    1 2 APU_CSNA PR1010
    EMC@

    PC1016

    PC1011

    PC1012

    PC1013
    51_0402_1%

    3
    2
    1

    2
    APU_GND PC1015
    @

    3
    2
    1

    2
    APU_UGATE1
    2 2 2

    APU_PHASE1
    1000P_0402_25V7-K
    680P_0402_50V7K
    +5VALW CPU_B+

    APU_TEMPA

    APU_RSP_LLA

    1
    APU_RSPA

    PGOOD_APU
    APU_RSN
    EMC@ PR1003 PH1003 @

    2
    PC1014
    1 2 2 1
    51K_0402_5%
    1
    22_0603_5%

    1
    82.5K_0402_1% 100K_0402_1%_TSM0B104F4251RZ
    2
    PR1008

    PR1007

    40

    39

    38

    37

    36

    35

    34

    33

    32

    31
    PU1001
    2

    COMPA

    TEMPA

    RSP_LLA

    RSN

    RSPA

    CSNA

    CSPA

    PGA

    LXA1

    HDRA1
    APU_GND
    1

    1U_0603_10V6-K PC1017
    2 1 1 APU_CSPA APU_CSNA
    VIN

    a
    PC1018
    1000P_0402_50V7K 30 APU_BOOT1
    2 1 APU_VDDA 2 BSTA1
    APU_GND VDDA

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    29 PC1007
    BSTA2

    1
    3

    hu
    C 1000P_0402_25V7-K C
    {35} EC_VR_ON

    1
    EN
    1M_0402_5%

    PC1026

    PC1027

    PC1028

    PC1029

    PC1030

    PC1031

    PC1032

    PC1033
    +1.8VS
    1

    28

    2
    HDRA2
    PR839

    PC1022 4
    1U_0603_10V6-K VDDIO APU_GND
    2

    27
    41 LXA2 +5VALW
    2

    APU_GND APU_GND AGND


    PR1012 2 1 0_0402_5% 5 BH5321LN_QFN40_5X5 26
    {35} EC_SMB_CK3 SCL LDRA2

    PR1013 2 1 0_0402_5% 6 25
    CPU_B+

    g.
    {35} EC_SMB_DA3 SDA VDDP

    PR1016 2 1 0_0402_5% 7 24 APU_LGATE1 PJ1001


    {6} APU_SVD SVD LDRA1

    1
    2 1
    PC1024
    1U_0603_25V6M 2 1 V20B+
    PR1017 2 1 0_0402_5% 8 23 LGATE_NB JUMP_43X79 1
    {6} APU_SVC

    2
    SVC LDRB

    68U_25V_M
    10U_0805_25V6K

    10U_0805_25V6K
    @
    +

    PC1035
    0.1U_0402_25V6

    1
    PC1036

    PC1037

    PC1038
    PR1018 2 1 0_0402_5% 9 22
    {6} APU_SVT SVT GNDP

    5
    2

    an

    2
    10 21 BOOT_NB
    +3VS

    AON6372_DFN
    @
    RSP_LLB

    VR_TTB BSTB
    1

    PWROK

    PC1146
    COMPB

    TEMPB

    HDRB
    CSNB

    PQ1006
    RSPB

    CSPB

    1000P_0402_25V7-K
    PGB

    LXB

    UGATE_NB 4 EMC@
    2

    2
    PR1142
    11

    12

    13

    14

    15

    16

    17

    18

    19

    20

    10K_0402_5% PR1024 PC1042


    APU_GND PR1140 2.2_0603_5% 0.22U_0603_25V7K

    3
    2
    1
    UGATE_NB
    PHASE_NB

    PR1020 2 1 0_0402_5% 0_0402_5% BOOT_NB 1 2 1 2


    APU_RSP_LLB

    {35} VR_HOT#

    1
    1

    PC1034 PGOOD_APU 1 2
    APU_TEMPB

    VR_APU_PWRGD {35}

    Hu
    APU_RSPB

    1000P_0402_25V7-K
    PR1141 0.36UH +-20% PCMB063T-R36MS 20A
    2

    PHASE_NB 1 2
    PGOOD_NB 1
    0_0402_5%
    2 PL1003 +APU_CORE_NB

    5
    B B
    APU_GND

    AON6372_DFN

    330U_2.0V_M

    330U_2.0V_M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    {6} APU_PWROK PR1021 1@ 1

    PQ1007
    PR1029

    1
    + +

    PC1044

    PC1045
    1 2 APU_CSNB LGATE_NB 4 PR1028 43.2K_0402_1%

    PC1046

    PC1047

    PC1048

    PC1049

    PC1050

    PC1051
    4.7_0805_5%

    1 1

    2
    2.05K_0402_1%

    2
    2 2
    EMC@
    PR1030

    APU_CSPB
    3
    2
    1
    PC1052
    1

    680P_0402_50V7K 51_0402_1%

    2
    PC1041
    r
    EMC@ PR1023 PH1004

    1
    +1.8VS 3300P_0402_50V7-K
    2

    2 1 1 2

    1000P_0402_25V7-K
    APU_CSNB
    APU_CSPB 80.6K_0402_1%
    100K_0402_1%_TSM0B104F4251RZ
    Fo

    2
    PC1040
    1

    PR1025 PR1026 PR1027 PC1043

    1
    1

    @ 1K_0402_1% @ 1K_0402_1% 22P_0402_50V8-J


    1K_0402_1%

    2
    2

    APU_GND

    APU_SVC APU_VDDA APU_GND


    APU_VDDA PRE-PWROK METAL VID CODES
    APU_TEMPA

    APU_TEMPB

    @
    APU_SVD
    SVC SVD Boot Voltage
    1

    APU_SVT
    PJ1002
    PR1031 PR1032 0 0 1.1V
    1 2
    0 1 1.0V
    1

    PR1034 4.87K_0402_1% 4.87K_0402_1%


    2

    PR1033 220_0402_5% PR1035 JUMPER


    1 0 0.9V
    1000P_0402_50V7K

    1000P_0402_50V7K

    A 220_0402_5% @ 220_0402_5% A
    @ @ @ 1 1 0.8V(Default)
    2

    APU_GND
    2

    1
    PC1053

    PC1054

    PH1001 PH1002
    100K_0402_1%_TSM0B104F4251RZ 100K_0402_1%_TSM0B104F4251RZ
    2

    APU_GNDAPU_GND APU_GND
    1

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
    APU_GND APU_GND Custom 1.0
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG412
    Date: Wednesday, February 24, 2016 Sheet 49 of 50
    5 4 3 2 1
    5 4 3 2 1

    +0.775VALWP +0.775VALW
    D
    200mA D

    50mA
    +1.8VALW PJ608 PU604 PJ1103
    2 1 3 4 2 1
    2 1 VIN VOUT 2 1

    4.7U_0603_6.3V6K

    1
    2
    JUMP_43X39 GND JUMP_43X39 @

    PC1161
    5 PR622
    SET

    1
    @ 1 5.9K_0402_1%

    2
    SHDN PC1160 PC631
    PR1165 220P_0402_50V7K 10U_0603_6.3V6M
    APL5701-ABI-TRG_SOT23-5

    2
    0_0402_5%
    STN@ STN@ STN@
    @
    EC_APU_ALWEN 1 2 EN_0_775VSP
    STN@
    {35,47} EC_APU_ALWEN
    STN@
    VFB=0.8V
    +1.5VS

    1
    APUALW_PWRGD 1 2
    PC633
    .1U_0402_10V6-K
    PR621
    20K_0402_1%
    TDC :200mA
    {35,47} APUALW_PWRGD

    2
    @
    PR1166

    a
    0_0402_5%
    STN@
    @
    C C

    hu
    g.
    an
    Hu
    B B

    r
    Fo

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2013/08/15 Deciphered Date 2013/08/15 +VGA_CORE
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 1.0
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Nano 110
    Date: Wednesday, February 24, 2016 Sheet 50 of 50
    5 4 3 2 1

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