Notes:

1. Power Quality: The power quality assessment is mainly based on total harmonic distortion (THD) in voltages and currents. For both wind turbines and photovoltaic
arrays connected to the utility grid, the maximum voltage and current THD allowed is 5%.

2. Point of Common Coupling (PCC): (As found on p75 of IEEE Std 519-1992) A point of metering, or any point as long as both the utility and the consumer can either
access the point for direct measurement of the harmonic indices meaningful to both or can estimate the harmonic indices at point of interference (POI). Within an
industrial plant, the PCC is the point between the nonlinear load and the other loads.[1] (As presently defined by IEEE 519 Working Group) The Point of Common
Coupling (PCC) with the consumer/utility interface is the closest point on the utility side of the customer's service where another utility customer is or could be
supplied. The ownership of any apparatus such as a transformer that the utility might provide in the customer’s system is immaterial to the definition of the PCC.[2]

3. Short Circuit Ratio (ISC/IL): The ratio of the short circuit current (ISC) available at the point of common coupling (PCC) to the maximum fundamental load current
(IL).[1]

4. Maximum Load Current (IL): Is recommended to be the average current of the maximum demand for the preceding 12 months.[1] (Unfortunately, this value is
inherently ambiguous making it difficult to derive at the design stage when measured load is not available).

5. Current TDD: Total Demand Distortion of the current waveform. The ratio of the root-sum-square value of the harmonic current to the maximum demand load
current.[1]

6. Compensator

7. PQ

8. Phase locked loop: When we connect renewable energy sources to the utility grid, there exists power quality and synchronization problem. The inverter output
parameters must be synchronized in phase and frequency of the utility network. For achieving this synchronism, we require a control technique called phase lock
loop. PLL is a closed-loop technique, and it produces an output signal which is synchronized in phase and frequency of the input reference signal. Every PLL has
three common blocks—phase detector, loop filter, and voltage-controlled oscillator.

9. Maximum Power Point Tracking (MPPT)

10. Synchronous PI Controller (yani DQ controller)

11. cross couplling compensation:

 12. Current-controlled inverters have the advantages of:
i. High accuracy control of an instantaneous current,
ii. peak-current protection,
iii. overload rejection,
iv. very good dynamics
13. Types of Controllers:
i. proportional–integral (PI),
ii. proportional–resonant (PR),
iii. predictive deadbeat (DB),
iv. hysteresis controllers have been proposed
14. The PI control scheme in the synchronously rotating (d,q) reference frame is commonly used and can work well with balanced systems, but it cannot cope with
unbalanced disturbance currents.
15. PR control scheme in the stationary (α,β) reference frame is popular due to the capability of eliminating the steady-state error, while regulating sinusoidal signals,
and the possible extension to compensate multiple harmonics. However, the resonant frequency in the controller has to be identical to the varying grid frequency
in order to maintain good performance
16. DB predictive control is widely used for current-error compensation and offers high performance for current-controlled VSIs. However, it is quite complicated and
sensitive to system parameters
17. Hysteresis control is simple and brings fast responses, but it results in high and variable sampling frequencies, which leads to high current ripples, poor current
quality, and difficulties in the output filter design. In order to obtain a fixed switching frequency, the complexity of the controller will be increased, if an adaptive
band hysteresis controller is used
18. Repetitive control theory [18], regarded as a simple learning control method, provides an alternative to reduce the THD in voltages or currents. It is able to
eliminate periodic errors in dynamic systems, according to the internal model principle [19], as it introduces high gains at the fundamental and all harmonic
frequencies of interest. The internal model is infinite dimensional and can be obtained by connecting a delay line into a feed back loop. Such a closed-loop system
can deal with a very large number of harmonics simultaneously. It has been successfully applied to constant-voltage constant-frequency pulse width modulation
(PWM) inverters [20], [21], grid-connected inverters [22],
[23], and active filters [24], [25]. However, these are
mainly used in the form of voltage controllers except the
one in [23].

19.
20.

Complexity Size of Filter Tolerant Control Switches

  Even though the 3LTI is generally implemented   By adding an additional
TNPC to apply in low-voltage applications, it has leg in parallel.  A 3L TNPC phase leg: consists of:
difficulties to apply in low-voltage and low-  1.) 4 IGBTs
power domestic appliances because the
increased efficiency is not sufficient due to its
complexity and cost problem.
 the 3-Level T-type inverter (3LTI) has been
proposed for the high efficiency and
performance in low-voltage applications
 The complexity of controlling the correct
switch-off sequence shall be maintained, i.e.
outer IGBT first (T1 or T4), inner IGBT
afterwards (T2 or T3) to avoid destruction due to
voltage breakdown.
 the T-Type topology must consequently use
semiconductors with higher voltage ratings for
its outer switches since they now have to block
the full DC link voltage, which means that its
semiconductor switching losses are generally
higher compared to a NPC converter at the same
switching frequency.
 The complexity of ANPC is even more than  There are different Fault-  A 3L TNPC phase leg: consists of:
ANPC NPC since controlling voltage balancing across Tolerant Control methods: 1.) 4 IGBTs
capacitors with proper selection of switching 1.) By adding an 2.) 2 switches (controlled IGBTs)
states and the classical DC offset injection for addition leg.
controlling neutral point voltage. 2.) Adding faulty
 The existing NP balancing control methods can phase to neutral.
be divided into two categories: 3.) Using two
1.) One is to add extra hardware circuit to additional fuses for
maintain the voltage balance between the open and short
series capacitors, which increases the cost circuit faults.
and complexity of the inverters. However the above
2.) The other is to apply different pulse width stated ones are
modulation (PWM) schemes. mostly for
SVPWM.
4.) For CBPWM there
is a proposed In-
Phase Disposition
Level Shifted
Disposition
Sinusoidal PWM
(IPD).