Designing with VHDL

Sandeepani is a training division of CoreEL Technologies (I) Pvt Ltd and Authorized Training
Provider for Xilinx in India for past 20 years

Course date: 3rd Dec – 5th Dec 2020

Course Description:

This course provides a thorough introduction to the VHDL language. The live, instructor-led program
comes with lectures and demos. The emphasis is on employing structural, register transfer level
(RTL), and behavioral coding styles in VHDL.

Who can attend?

 Undergraduate students in III or Final year of Engineering
 Post graduate students interested in brushing up their skills in VHDL
 Faculty members and working professionals interested in up-skilling

Pre-requisites:
 Knowledge of digital circuits

Course duration:
 3 days (9 hours – 3 hours per day)

What do I gain?
 Implement the VHDL portion of coding for synthesis
 Identify the differences between behavioral and structural coding styles
 Distinguish coding for synthesis versus coding for simulation
 Use concurrent and sequential control structure to regulate information flow
 Simulate a basic VHDL design
 Write a VHDL testbench and identify simulation-only constructs
 Modeling Memories
 Modeling FSMs – Mealy and Moore
 Using subprograms in the design

Course Contents:
Day 1
 Introduction to VHDL
 Discusses the history of the VHDL language and provides an overview of the different
features of VHDL.VHDL Design Units-Provides an overview of typical VHDL code, covering
design units such as libraries, packages, entities and architectures
 Lab 1: Modeling adders and multiplexers using concurrent assignment statements
 Introduction to Structural modeling – Components , Instantiation – positional and named
associations
 Lab 2: Modeling Ripple carry adder

Day 2:
 Introduction to Behavioral Modeling – Process blocks and Sequential assignment statements
 Lab 1: Modeling Latches and Flipflops

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  Introduction to Testbench – Components of Testbench- Simulation only constructs
Lab 2: Testbench for adders and flipflops
 Conditional Statements in VHDL: if/else, case Describes conditional statements such as
if/else and case statements.
Lab 3: Modeling synchronous counters and Shift registers
 Sequential Looping Statements Introduces the concept of looping in both the simulation and
synthesis environments
 Delays in VHDL: Wait Statements-Covers the wait statement and how it controls the
execution of the process statement.
 Lab 4: Testbench for counters and shift registers

Day 3:
 Finite State Machine Overview-Provides an overview of finite state machines, one of the
more commonly used circuits. Mealy and Moore FSM – Modeling memories
 Lab 1: Implementing Mealy and Moore FSM
 FSM Coding Guidelines - Describes the guidelines and recommendations for using one or
more procedural blocks when coding a finite state machine.
 Lab 2: Testbench for FSM
 Writing a good Testbench
 FSM coding guidelines
 VHDL Subprograms – Functions and Procedures
Lab 3: Modeling Mux using functions and procedures

Course Fee: 3 days (9 Hours) – INR 2,000/- (Exclusive till Lockdown Ends)

Last date for confirmation: 2-Dec-2020

Registration link: Click here to register

Payment Guidelines:
Participants of Sandeepani training modules can make the course fee payment through online
transfer via your Google Pay/PhonePe/Internet Banking Account to the following account and proof
of the same to be scanned & mailed to xtc@coreel.com.

Account details:
Sl.No Bank Account details for Domestic Transactions
1 Name of the Company CoreEL Technologies
2 Current Account No 0947000104207601
Karnataka Bank Ltd
3 Name of Bank & Address Koramangala Extension Branch,
Bangalore 560 034
4 NEFT/IFSC Code of Bank KARB0000094
5 MICR Code of Bank 560052014
6 Contact Tel/Mobile 080-41970400
7 Email ID, if any accounts@coreel.com

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