Professional Documents
Culture Documents
V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential
CONTENTS PAGE
Sections
1. Features 1-1
2. Specifications 2-1
8. Waveforms 8-1
Appendix
1. Main Board Circuit Diagram
Block Diagram
IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
9. On Screen Display: user can define display mode (i.e. color, brightness,
contrast, sharpness, backlight), sound setting, PIP, TV channel program,
aspect and gamma or reset all setting.
2. OPTICAL CHARACTERISTICS
Viewing Angle (CR>10)
Left: 89°typ.
Right: 89°typ.
Top: 89°typ.
Bottom: 89°typ.
4.Input Connectors
RJ11, D-SUB15PIN (MINI, 3rows), HDMIX2, RCAX2 (component), RCAX2 (AUDIO
in), RCAX2 (composite), RCAX2 (AUDIO in), S-Video, Tuner
Output Connectors
Analog audio out (Stereo RCA Jack) , Digital audio out (Optical)
6.Speaker
Output 10W (max) X2
7. ENVIRONMENT
7-1. Operating Temperature: 5c~35c (Ambient)
7-2. Operating Humidity: Ta= 35 °C, 90%RH (Non-condensing)
7-3. Operating Altitude: 0 - 14,000 feet (Non-Operating)
Please pay attention to the followings when you use this TFT LCD module.
9-1. MOUNTING PRECAUTIONS
(1) You must mount a module using holes arranged in four corners or four sides.
(2) You should consider the mounting structure so that uneven force (ex. Twisted
stress) is not applied to the module. And the case on which a module is mounted
should have sufficient strength so that external force is not transmitted directly to
the module.
(3) Please attach the surface transparent protective plate to the surface in order to
protect the polarizer.
Transparent protective plate should have sufficient strength in order to the resist
external force.
(4) You should adopt radiation structure to satisfy the temperature specification.
b. BACKLIGHT (0~100)
c. BRIGHTNESS (0~100)
d. CONTRAST (0~100)
e. COLOR (0~100)
f. TINT (-32~32)
g. SHARPNESS (0~100)
i. ADVANCED VIDEO
i-1. DNR(OFF/LOW/MEDIUM/STRONG)
i-4 CTI(OFF/LOW/MEDIUM/STRONG)
C. TV:
D. SETUP:
a. LANGUAGE (ENGLISH/FRENCH/SPANISH)
b. SLEEP TIMER (OFF/30/60/90/120)
c. ANALOG CC (OFF/CC1/CC2/CC3/CC4)
d. DIGITAL CC(OFF/SERVICE1/ SERVICE2/ SERVICE3/ SERVICE4/ SERVICE5/
SERVICE6)
e. DIGITAL CC STYLE
e-1. CAPTION STYLE
(AS BROADCASTER/CUSTOM)
e-2. FONT SIZE(SMALL/MEDIUM/LARGE)
e-3. FONT COLOR
(GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE)
e-4. FONT OPACITY
(SOLID/TRANSLUCENT/TRANSPARENT)
e-5. BACKGROUND COLOR
(GREEN/BLUE//RED/CYAN/YELLOW/MAGENTA/BLACK/WHITE)
e-6. BACKGROUND OPACITY
(SOLID/TRANSLUCENT/TRANSPARENT)
E. PARENTAL:
a. PASSWORD
a-1. CHANNEL BLOCK
a-2. TV RATING
a-3. MOVIE RATING
a-4. BLOCK TV UNRATED
a-5. ACCESS CODE EDIT
RGB Mode
A. PICTURE ADJUST:
B. AUDIO:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (-50~50)
e. SURROUND (ON/OFF)
f. SPEAKERS (ON/OFF)
a. LANGUAGE (ENGLISH/FRENCH/SPANISH)
AV COMPONENT MODE
AV-C、AV-S、COMPONENT
A. PICTURE:
b. BACKLIGHT (0~100)
c. BRIGHTNESS (0~100)
d. CONTRAST (0~100)
e. COLOR (0~100)
f. TINT (-32~32)
g. SHARPNESS (0~100)
i. ADVANCED VIDEO
i-1. DNR(OFF/LOW/MEDIUM/STRONG)
i-4 CTI(OFF/LOW/MEDIUM/STRONG)
D. SETUP:
a. LANGUAGE (ENGLISH/FRENCH/SPANISH)
E. PARENTAL:
a. PASSWORD
a-2. TV RATING
b. BACKLIGHT (0~100)
c. BRIGHTNESS (0~100)
d. CONTRAST (0~100)
e. COLOR (0~100)
f. TINT (-32~32)
g. SHARPNESS (0~100)
i. ADVANCED VIDEO
i-1. DNR(OFF/LOW/MEDIUM/STRONG)
i-4 CTI(OFF/LOW/MEDIUM/STRONG)
B. AUDIO:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (-50~50)
e. SURROUND (ON/OFF)
f. SPEAKERS (ON/OFF)
a. LANGUAGE (ENGLISH/FRENCH/SPANISH)
Pin Description
1 Red
2 Green
3 Blue
4 Ground
5 Ground
6 R-Ground
7 G-Ground
8 B-Ground
10 Ground
11 No Connection
12 (SDA)
14 V-Sync
15 (SCL)
1 5
6 10
11 15
J1 CONNECTION (TOP→BOTTOM)
Pin Description
1 “POWRSW”
2 “+12V”
3 “+12V”
4 “+12V”
5 “+12V”
6 “GND”
7 “GND”
8 “GND”
9 “+5V”
10 “+5V”
11 “+5V”
12 “PWM”
13 “BL ON/OFF”
2. Decoder
TVD
1.Single 2nd generation TV decoder
2.Automatic TV standard detection supporting NTSC, NTSC-4.43,
3.Enhanced 2nd generation NTSC Motion Adaptive 3D comb filter
4.Motion Adaptive 3D Noise Reduction
5.Embedded VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS
6.Supporting Macro vision detection
YPbPr
1.Supporting HDTV 480i/480p/576i/576p/720p/1080i input
2.Smart detection on Scart function for European region
VGA
1.Supporting various VGA input timings up to SXGA (1280x1024@75Hz).
2.Supporting Separate/Composite/SOG sync types
VBI
1.Dual VBI decoders for the application of V-Chip/Closed-Caption/XDS/ Teletext/WSS/VPS
2.Supporting external VBI decoder by YPrPb input
3.VBI decoder up to 1000 pages Teletext.
3. Support Formats:
Support NTSC, NTSC-4.43
Automatic Luma / Chroma gain control
Automatic TV standard detection
NTSC Motion Adaptive 3D comb filter
Motion adaptive 3D Noise Reduction
VBI decoder for closed-caption/XDS/Teletext/WSS/VPS
Macro vision detection
4. 2D-Graphic/OSD processor
Embedded two backend RGB domain OSD planes and one YUV domain OSD plane. to support
Main/PIP Teletext/Close-caption functions together with setup menu
1.Supporting alpha blending among these two planes and video
2.Supporting Text/Bitmap decoder
3.Supporting line/rectangle/gradient fill
4.Supporting bitblt
5.Supporting color Key function
6.Supporting Clip Mask
7.65535/256/16/4/2-color bitmap format OSD,
8.Automatic vertical scrolling of OSD image
9.Supporting OSD mirror and upside down
6. Video processor
1.Color Management
Fully 10-bit processing to enhance the video quality
Advanced flesh tone and multiple-color enhancement. (For skin, sky, and grass…)
Gamma/anti-Gamma correction
Advanced Color Transient Improvement (CTI)
Saturation/hue adjustment
2.Contrast/Brightness/Sharpness Management
Sharpness and DLTI/DCTI
Brightness and contrast adjustment
Black level extender
White peak level limiter
Adaptive Luma/Chroma management
3.De-interlacing
2nd generation advanced Motion adaptive de-interlacing
Automatic detect film or video source
3:2/2:2 pull down source detection
Main/PIP 2 independent de-interlacing processor
7. DRAM Usage
1.For features of 5372, Dual for enhance features support, and single 8x16 DDR for
simple function support Lists are the comparison chart between function support lists
of (2xDDR) and (1xDDR)
2.For single DDR,5372only support 1080i bob mode de-interlacing. (Non-3D de interlace)
3.With single DDR, it is suggested not to support PIP/POP features. Due to DDR Bandwidth
limitation on PIP when single DDR.
BLOCK DIAGRAM
3. HDCP Decryption
HDCP decryption contains all necessary logic to decrypt the incoming audio and video
data. The decryption process is entirely controlled by the host microprocessor through a
set sequence of register reads and wires through the DDC channel. Pre-programmed
HDCP keys and key Selection Vector are used in the decryption process. A resulting
calculated to an XOR mask during each clock cycle to decrypt the audio/video data in
sync with the host.
Block diagram
1. Input configuration
The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the
asymmetrical mode one input pin is connected via a capacitor to the signal source and the other
input is connected to the signal ground. The signal ground should be as close as possible to the
SVR (electrolytic) capacitor ground. Note that the DC level of the input pins is half of the supply
voltage VCC, so coupling capacitors for both pins are necessary
1 . Host CPU:
1. ARM 926EJ
2.16K I-Cache and 16K D-Cache
3. 8K Data TCM and 8K instruction
4. JTAG ICE interface
5. Watch Dog timers
3 . MPEG2 Decoder :
1. Support dual MPEG-2 HD decoder or up to 8 SD decoder.
2. Complaint to MP@ML , MP@HL and MPEG-1 video standards.
4 . JPEG Decoder :
1. Decode Base-line or progressive JPEG file.
5 . 2D Graphics :
1. Support multiple color modes.
2. Point , horizontal/vertical line primitive drawing.
3. Rectangle fill and gradient fill functions.
4. Bitblt with transparent , alpha blending , alpha composition and stretch.
5. Font rendering by color expansion.
6. Support clip masks.
7. YCrCb to RGB color space transfer.
6 . OSD Display :
1. 3 linking list OSDs with multiple color mode.
2. OSD scaling with arbitary ratio from 1/2x to 2x.
3. Square size , 32x32 or 64x64 pixel , hardware cursor.
7 . Video Processing :
1. Advanced Motion adaptive de-interlace on SDTV resolution.
2. Support clip
3. 3:2/2:2 pull down source detection.
4. Arbitrary ratio vertical/horizontal scaling of video , from 1/15X to 16X.
5. Support Edge preserve.
6. Support horizontal edge enhancement.
7. Support Quad-Picture.
9 . Auxiliary Display :
1. Mixing one video and one OSD.
2. 480i/576i output.
10 . TV Encoder :
1. Support NTSC M/N , PAL M/N/B/D/G/H/I
2. Macrovision Rev 7.1.L1
3. CGMS/WSS.
4. Closed Captioning.
5. Six 12-bit video DACs for CVBS , S-video or RGB/YPbPr output.
12 . DRAM Controller :
1. Support 64Mb to 1Gb DDR DRAM devices.
2. Configurable 32/64 bit data bus interface.
3. Support DDR266 , DDR333 , DDR400 , JEDEC specification compliant SDRAM.
15 . Peripherals :
1. Three UARTs with Tx and Rx FIFO , two of them have hardware flow control.
2. Two serial interfaces , one is master only the other can be set to master mode or slave mode.
3. Two PWMs.
4. IR blaster and receiver.
5. IEEE1394 link controller.
6. IDE bus : ATA/ATAPI7 UDMA mode 5 , 100MB/s.
7. Real-time clock and watchdog controller.
8. Memory card I/F : MS/MS-pro ,SD ,CF ,and MMC
9. PCMCIA/POD/CI interface
16 . IC Outline :
1. 471 Pin BGA Package.
2. 3.3V/1.2V dual Voltage.
The MX29LV320AT/B is a 32-mega bit Flash memory organized as 4M bytes of 8 bits and 2M words
of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile
random access memory.
The MX29LV320AT/B is packaged in 48-pin TSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard EPROM programmers. The standard
MX29LV320AT/B offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV320AT/B has
separate chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and
programming. The MX29LV320AT/B uses a command register to manage this functionality. MXIC
Flash technology reliably stores memory contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29LV320AT/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and
auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi
process. Latch-up protection is proved for stresses up to 100 milliamperes on address and
data pin from -1V to VCC + 1V.
Legend:
L=Logic LOW=VIL, H=Logic High=VIH, VID=12.0 0.5V, VHH=11.5-12.5V, X=Don't Care,
AIN=Address IN, DIN=Data IN,DOUT=Data OUT
Notes:
1. When the WP/ACC pin is at VHH, the device enters the accelerated program mode. See
"Accelerated Program Operations" for more information.
2.The sector group protect and chip unprotect functions may also be implemented via programming
equipment. See the "Sector Group Protection and Chip Unprotection" section.
3.If WP/ACC=VIL, the two outermost boot sectors remain protected. If WP/ACC=VIH, the two
outermost boot sector protection depends on whether they were last protected or unprotected
using the method described in "Sector/Sector Block Protection and Unprotection". If
WP/ACC=VHH, all sectors will be unprotected.
4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.
5.Address are A20:A0 in word mode (BYTE=VIH), A20:A-1 in byte mode (BYTE=VIL).
Notes:
1.Code=00h means unprotected, or code=01h protected.
2.Code=99 means factory locked, or code=19h not factory locked.
Legend:
X=Don't care
RA=Address of the memory location to be read.
RD=Data read from location RA during read operation.
PA=Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE or CE pulse.
PD=Data to be programmed at location PA. Data is latched on the rising edge of WE or CE pulse.
SA=Address of the sector to be erased or verified. Address bits A20-A12 uniquely select any sector.
ID=22A7h(Top), 22A8h(Bottom)
Notes:
1.All values are in hexadecimal.
2.Except when reading array or Automatic Select data, all bus cycles are write operation.
3.The Reset command is required to return to the read mode when the device is in the Automatic
Select mode or if Q5 goes high.
4.The fourth cycle of the Automatic Select command sequence is a read cycle.
5.The data is 99h for factory locked and 19h for not factory locked.
6.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
In the third cycle of the command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to
verify sectors 32~70 for Top Boot device.
7.Command is valid when device is ready to read array data or when device is in Automatic Select
mode.
8.The system may read and program functions in non-erasing sectors, or enter the Automatic Select
mode, when in the erase Suspend mode. The Erase Suspend command is valid only during a
sector erase operation.
9.The Erase Resume command is valid only during the Erase Suspend mode.
RESET OPERATION
01The RESET pin provides a hardware method of resetting the device to reading array data. When
the RESET pin is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all output pins, and ignores all read/write commands for the duration
of the RESET pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET pulse. When RESET is held at VSS 0.3V, the
device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS 0.3V, the
standby current will be greater.The RESET pin may be tied to system reset circuitry. A system reset
would that also reset the Flash memory, enabling the system to read the boot-up firm-ware from the
Flash memory.
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte/word address being programmed while in the erase-suspend program mode will
indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
CONFIDENTIAL – DO NOT COPY Page 7-27
File No. SG-0204
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12
to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register
Set command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the
desired values. A Mode Register Set command issued to reset the DLL should always be followed
by a Mode Register Set command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Auto Refresh
Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before
RAS (CBR) Refresh in previous DRAM types. This command is nonpersistent, so it must be issued
each time a refresh is required.The refresh addressing is generated by the internal refresh controller.
This makes the address bits “Don’t Care” during an Auto Refresh command. The 256Mb DDR
SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum).
Self Refresh
The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the
system is powered down.When in the self refresh mode, the DDR SDRAM retains data without
external clocking. The Self Refresh command is initiated as an Auto Refresh command coincident
with CKE transitioning low. The DLL is automatically disabled upon entering Self Refresh, and is
automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read
command can be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh
operation.
The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be
stable prior to CKE returning high. Once CKE is high, the SDRAM must have NOP commands
issued for tXSNR because time is required for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock
cycles before applying any other command.
Writes
Write bursts are initiated with a Write command, as shown in timing figure Write Command on
following: The starting column and bank addresses are provided with the Write command, and Auto
Precharge is either enabled or disabled for that access. If Auto Precharge is enabled, the row being
accessed is precharged at the completion of the burst. For the generic Write commands used in the
following illustrations, Auto Precharge is disabled.
During Write bursts, the first valid data-in element is registered on the first rising edge of DQS
following the write command, and subsequent data elements are registered on successive edges of
DQS. The Low state on DQS between the Write command and the first rising edge is known as the
write preamble; the Low state on DQS following the last data-in element is known as the write
postamble. The time between the Write command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle), so most of
the Write diagrams that follow are drawn for the two extreme cases (i.e. tDQSS(min) and
tDQSS(max)). Timing figure Write Burst (Burst Length = 4) on page 33 shows the two extremes of
tDQSS for a burst of four. Upon completion of a burst, assuming no other commands have been
initiated, the DQs and DQS enters High-Z and any additional input data is ignored.Data for any Write
burst may be concatenated with or truncated with a subsequent Write command. In either case, a
continuous flow of input data can be maintained.
Write Command
CH1 AV2
CH1 YPBPR2_Y
HDMI 2
CH1 RX1; CH2 RX1-B
Start
N0
1. Is Power board output
+5VSB &DV12?
LED is lighted
2. Is J1 connector good?
3. Is DC-DC OK?
4. Is U1 (+5V) working ok?
Yes
It is in power saving
N0 1. Check video cable
LED is lighting? 2. Is the timing supported?
3. Check sync input
4. Check VGASOG rout if analog
(SOG)
Yes
N0
Yes
Yes
N0 It means data to LVDS
1.Is J7 connecting OK?
U14 no data out? 2.Check J1 +5V&+12V
3.Is panel ok?
4. Check P3 D-sub Input correct
5. Check analog input route
Yes
END
Start
N0
Yes
N0
1.Check P11(VIDEO&S) signal
2.Check signal between P1 and
U14 (IF IN AV mode)
U14 input correct?
3.Check Tuner &U13 (IF TV mode)
4.Check P1 (IF S-Video)
Yes
N0
1. Check U14
DV33&DV12&AV15&AV12
U14 output correct?
2.Check X1 is OK?
Yes
N0
Yes
END
Start
N0
1.Check video
Input signal good? 2.Check host’s setting
Yes
N0
Yes
N0
1.Check signal between U14&P1
U14 input correct? 2.Check U14 Clock (27MHZ)
3. Check U14
DV33&DV12&AV15&AV12
Yes
N0
1.Check U14
LVDS output correct ? 2. Check LVDS 5V or 12V
Yes
END
Start
N0
N0
1.Check p10&p11 connect
U31 input correct?
2.Check signal between U31
and U19
Yes
N0
Yes
Yes
END
Start
N0
The voltage is about + 5V
1.Check power board
J7 PIN10,11,12 2.Check power cable
connection J7
Yes
N0
The voltage is about + 12V while
power switch on
J7 PIN 2,3,4 1.J7 connection good
2.Check J7 Pin1 is up to 3V?
3.Check power board
Yes
N0
The voltage is about +5V while
power switch on
U1 pin 5 6 7 8 1.J1 connection good
2. Check U11 GPIO_7 Pin
Yes
N0
The voltage is about +3.3V
1.J1 to connection good?
U4 pin2 2.Check U4
Yes
N0
The voltage is about +3.3V
1.J1 to connection good?
U6 pin 2 2.Check U6
Yes N0
The voltage is about +1.8V while
power switch on
U5 pin2 1.Check U5
Yes
N0
The voltage is about +3.3V
while power switch on
U8 pin2 1.Check J1 Connect
2.Check U8
END
Start
N0
Support DDC1/2B
1.Analog cable ok?
2.Check signal (U20 to P3)
Analog DDC OK? 3.Check U20 Voltage
4.Is compliant protocol?
Yes
N0
Support DDC1/2B
1.Analog cable ok?
HDMIDDC OK? 2.Check signal (U32 to P10)
3. Check signal (U34 to P11)
4.Is compliant protocol?
Yes
END
Digital
Video bus Power Board AC IN
Speakers
J2 J7 J1 J6
Main Board
J4
P6 P7 P8 P3 P4 P1 P2 P11 U12 P1 P9
□□□□□
Keypad/IR
Board RJ11 HDMIX2 RCA RGB earphone YPBPRX2RCAX2 AV1 Tuner SPDIF AudioRCA OUT
The TV system block diagram is powered by power board that transforms AC source
of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main
board receives different types of video signal into the MT5372 Ic. Afterward, the
MT5372 Ic process the signals control the various functions of the monitor and
outputs control signal, video signal and power to the 32” WXGA panel to be displayed.
The power send to the panel is first processed by the inverter. The function of the
inverter is to step up the voltage supplied by the main board to the power that is
needed to light up the lamps in the panel. Simultaneously, the digital video signals are
processed in the panel and the outcome determines the brightness, pixel on/off and
the color displayed on the panel. The analog video signals of S-video, YPbPr, TV, PC
and A/V all video signals are translated from analog signals into MT5372 generates
the vertical and horizontal timing signals for display device. The analog audio of
s-video, YpbPr, TV, PC and A/V is transmitting to the WM8776 processed. The
purpose is process the input audio signal to control volume, bass, treble, surround,
and balance. All functions are controllable by the main board. Plus, all functions in the
IC boards are programmable using I2C Bus.
U21
U28 R-
Audio U31
VGA TDA8946AJ
P3 DSUB EDID
EEPROM
Processor AUDIO AMP.
L+
WM8776 L-
DSUB
P4 AUDIO
U27
Y1
CD4052
P1 Pb1
U18 U19
16M x 16 DDR 16M x 16 DDR
Pr1
L1 R1
P2
L2 R2 U17 I2C
24C16
Y2 SYS
EEPROM
I2C
P1 Pb2
Pr2 U14
Panel
AV1
MT5372
J4 L1
R1
IR
J4 S-Video U11
74HC00
AV2 POWER ON
Detect Key Board
P11 L2
R2 P10
SPDIF
AUDIO
OUT
P9
I2C U30 ANALOGY
NTSC_CVBS WM8521 AUDIO
SIF OUT
U12 U16
Tuner FAT_IN- I2C
FLASH
MX29LV320
FAT_IN+ U13
IF_AGC MT5112