The History of ARM

Developed at Acorn Computers Limited, of Cambridge, England, between 1983 and 1985

Problems with CISC:

Slower then memory parts Clock cycles per instruction

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Features

Architectural simplicity which allows

Very small implementations which result in

Very low power consumption

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ARM Powered Products

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What Is ARM?

Advanced RISC Machine First RISC microprocessor for commercial use Market-leader for low-power

and cost-sensitive embedded applications

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Example ARM-based System

16 bit RAM 32 bit RAM Peripherals

Interru pt Control nIR nFI ler

Q Q

I/O

8 bit ROM

ARM Core

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ARM Processor Core

Current low-end ARM core for applications like digital mobile phones TDMI

T: Thumb, 16-bit instruction set D: on-chip Debug support, enabling the processor to halt in response to a debug request M: enhanced Multiplier, yield a full 64-bit result, high performance I: Fall 2008 2/18/13EmbeddedICE hardware ELEC8200-001: 66

ARM Core Diagram

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ELEC8200-001:

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An Example AMBA System

High Performance ARM processor High Bandwidt h External Memory Interface Highbandwidth on-chip RAM AP B APB Bridge UART Timer Keypad DMA Bus Master PIO

AH B

High Performance Pipelined Burst Support Multiple Bus Masters

Low Power Nonpipelined Simple Interface

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AHB Structure
Arbiter
HADD R HWDAT A HRDAT A HADD R HWDAT A HRDAT A

Mast er #1

Slav e #1

Address/Cont rol

Mast er #2
Write Data

Slav e #2

Mast er #3

Read Data

Slav e #3

Decoder

Slav e #4

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Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal)

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The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers

The current processor mode governs which of several banks is accessible. Each mode can access

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a particular set of r0-r12 registers ELEC8200-001:

1111

Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal)

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User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr

Register Organization Summary

FIQ IRQ SVC Undef Abort
User mode r0-r7, r15, and cpsr User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr User mode r0-r12, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

Thumb state Low register s Thumb state High register s

spsr

spsr

spsr

spsr

spsr

Note: System mode uses the User mode register set

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LSL : Logical Left Shift

C F

The Barrel Shifter

ASR: Arithmetic Right Shift
0

Destination

Destination

C F

Multiplication by a power of 2 LSR : Logical Shift Right

... 0

Division by a power of 2, preserving the sign ROR: Rotate Right bit

Destination
C F

Destination

C F

Division by a power of 2

Bit rotate with wrap around from LSB to MSB RRX: Rotate Right Extended
Destination
C F

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Single bit rotate with wrap around from CF to MSB

Operating Modes

Seven operating modes:

User Privileged:

System (version 4 and above) FIQ IRQ Abort Undefined Supervisor

Authors : Nemanja Perovic, 1515

exception modes