Migrating from the RX62N to the RX63N

Renesas Electronics America Inc.

Date 19-Jan-2012 Rev. 1.00

© 2012 Renesas Electronics America Inc. All rights reserved. 00000-A

 Agenda

 Why the RX63N?

 Overview of RX62N vs RX63N differences
 Additional features of the RX63N
 Tools for RX63N development
 Documentation, support, contacts
 2012 plans

 Main take away:

 Help you avoid most common mistakes!

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 Key Reasons to Look at RX63x Now

RX62x is good but I need… RX63x

• More than 512KB of Flash • Supports up to 2MB Flash

• More than 1 CAN • Up to 3 CAN Channels
• Lower Power in standby • Lowest mode is 2.5µA
• More than 8 ADC Ch. • Up to 21 ADC Channels
• More than 2 I2C Ports • Up to 4 I2C Ports
• More than 1 USB Port • Up to 2 USB Ports
• Separate RTC Power Domain • Supports VBAT pin

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 RX62N vs RX63N Differences

 Clock chain
 Option setting memory & mode pin(s)
 Register protection
 Multi-function Pin Controller (MPC)
 Interrupt request groups
 And many more!

 Good news for partners!

 USB & Ethernet and most other peripherals are unchanged!

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 Clock Chain

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 RX62N Clock Chain

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 RX63N Clock Chain

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 RX62N vs RX63N Differences: Clock Chain

 Differences:
 RX63N has on-chip HOCO (50 MHz), LOCO (125 kHz)
 Sub-clock Oscillator (32 kHz) has its own power domain
 RX63N has two PCLK’s
 RX63N has separate FCLK

 Gotcha’s:
 Chip starts up on LOCO = slow startup
 PLL: VCO osc. freq. must be between 104 MHz & 200 MHz
 Ethernet: PCLKA must match ICLK! (not documented)
 Be careful – you can make invalid settings easily!

 Tips:
 Save power: Set unused clocks (BCLK) to highest divisor
 Check app note on ICLK/PCLK latencies (R01AN0181EJ0100)

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 Option Setting & Mode Pins

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 RX62N vs RX63N Differences: Option Settings

RX62N RX63N

 MD0, MD1, MDE pins  One mode pin (MD)

 PC7: serial boot or
USB/user boot
 Flash settings
 WDT
 IWDT
 LVDT0
 HOCO
 Endian
 User boot/USB boot

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 RX63N Flash-Based Options (Chapter 7)

 Some located in the fixed vector table

 Some located in User Boot Flash
 All 0xFF’s (erased) means
 No watchdogs
 Little-endian
 HOCO off at boot
 Low-voltage monitor 0 reset disabled

 Gotcha’s
 Enable IWDT & break debugger connection!
– Serial boot mode to recover
 Different Endian modes for single-chip vs. user/USB boot
 Existing code may write these areas!

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 Register Protection

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 Register Protection

 Protect Register (PRCR)

 3 bits, each protects a group of registers:
 PRC0: Clock generation circuit
 PRC1: Operating modes, low power, module stop control
 PRC3: Low-voltage detect

 Upper byte is keyed to allow access to PRC0-PRC3

 0xA5xx to unlock

 Gotcha! Protected registers don’t reference PRCR!

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 Multi-Function Pin Controller

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 Multi-Function Pin Controller

 New feature on RX63N

 Replaces Port Function Control Registers on RX62N
 Much more flexible
 One register for each pin (P0nPFS…PJnPFS, n=0-7)
 One bit for Analog Input function (ASEL)
 One bit for Interrupt function (ISEL)
 Five bits for peripheral function select (PSEL)

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 Multi-Function Pin Controller

 Gotcha’s
 Remember to unlock with PWPR register
 The PSEL mappings may differ between packages
– Review before spinning a board!
 Additional registers for:
– External bus (chip selects, address & data buses)
– USB (pull-up configuration)
– Ethernet (MII or RMII mode)
 Follow “Usage Notes” for configuring
 For peripheral use, must also set Port Mode Register (PMR)

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 Pin Setup

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 Pin Setup Differences

 RX62N  RX63N
 PORTn.DDR  PORTn.PDR
 PORTn.DR  PORTn.PODR
 PORTn.PORT  PORTn.PIDR
 PORTn.ODR  PORTn.ODR0/1
 PORTn.PCR  PORTn.PCR
 PORTn.DSCR

 PORTn.ICR  PORTn.PMR
 PFnXXX  MPC.PnxPFS

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 Interrupts

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 RX63N Interrupt Control Unit Differences

 Vector numbers have changed

 Use your iodefine macros!
– VECT(TMR0, CMIA0)

 New features!
 Interrupt Request Groups
 Interrupt Unit Selection
 Digital Filter

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 RX63N Interrupt Request Groups

 Why? Out of vectors

 Aggregate multiple sources into one IR
 ISR must sort & service pending requests in the group
 8 groups: Group 0-6 and Group 12
 Groups 0-6:
 Edge sensitive
 Groups for CAN, MTU channels, TPU channels
 Group 12:
 Level sensitive
 SCI and RSPI errors all routed to single IR (IR114.IR)

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 RX63N ICU: Interrupt Unit Selection

 6 Units
 Select between TPU –or– MTU IRQ sources
 Check for conflicts! (i.e. can’t use MTU0 & TPU6)

TPU6
IR142

MTU0

IR147

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 RX63N IRQ Digital Filtering

 Hardware IRQ pins: Now offer digital filtering

 Four rates: PCLK, PCLK/8, PCLK/32, PCLK/64
 Filters out short pulses
– Shorter than 3 samples @ filter rate
 Even at slowest rates, still too fast for switch debouncing
 OK for filtering ringing/noise

 Gotcha’s (minor):
 Adds a bit of latency to IRQ’s

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 Wrap Up!

 Clock Chain

 Option Setting & Mode Pins

 Register Protection

 Multi-Function Pin Controller

 Pin setup

 Interrupts

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 Plans for 2012

 Launch of Renesas e2 Studio

 New Eclipse-based IDE from Renesas!
– Built on Eclipse v3.6 (Helios)
– e2 = eclipse embedded
 V1.0 MP scheduled to be released at the end of February
– Beta version for partners expected to become available
by the end of January – contact Axel
 Target MCU families: RL78, RX, V850 (SH coming later)
 Target debuggers / emulators:
– Renesas E1, E20, IECUBE, IECUBE2
– Third-party debuggers (bring your own plug-in!)
 Target Toolchains:
– Renesas toolchains for RX, RL78, V850 (licenses required)
– Third-party toolchains, e.g from IAR Systems, Green Hills
(via plug-ins; licenses required)
– GNU toolchains for RX, RL78, V850 (free of charge)
 Contact Axel for more information

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 Renesas Electronics America Inc.
© 2012 Renesas Electronics America Inc. All rights reserved.