FA16-BCE-093 M.

Afaq Khaliq

Question I: [7+2=9 Marks]

a). Apply HDL modelling technique using VHDL programming language to design 4-bit Arithmetic
Logic Unit (ALU) which can perform the functions enlisted in Table1. (PLO3-C3/CLO5)
b). Display the result using vector waveform (vwf) simulator. (PLO5-P4/CLO6
Main File
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.AllComponents.all;

entity Task1 is
port(
sel:in std_logic_vector(3 downto 0);
a,b:in std_logic_vector(7 downto 0);
cin:in std_logic;
y:out std_logic_vector(7 downto 0)
);
end Task1;

architecture archi of Task1 is

signal yArith:std_logic_vector(7 downto 0);
signal yLogic:std_logic_vector(7 downto 0);
begin
LevelArith: Arithematic port map(not sel(2 downto 0),a,b,cin,yArith);
LevelLogic: Logic port map(not sel(2 downto 0),a,b,yLogic);
process(sel,a,b,cin)
begin
if(not sel(3)='0') then
y<=yArith;
elsif(not sel(3)='1') then
y<=yLogic;
end if;
end process;
end archi;
FA16-BCE-093 M.Afaq Khaliq

Package File of All Component

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

package AllComponents is

component Arithematic is
port(
sel: in std_logic_vector(2 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
cin:in std_logic;
y: out std_logic_vector(7 downto 0)
);
end component;

component Logic is
port(
sel: in std_logic_vector(2 downto 0);
a: in std_logic_vector(7 downto 0);
b: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0)
);
end component;
end AllComponents;

Logic Function file

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Logic is

port(
FA16-BCE-093 M.Afaq Khaliq

sel: in std_logic_vector(2 downto 0);

a: in std_logic_vector(7 downto 0);

b: in std_logic_vector(7 downto 0);

y: out std_logic_vector(7 downto 0)

);

end Logic;

architecture archi of Logic is

begin

process(sel,a,b)

begin

if(sel="000") then

y<=not a;

elsif(sel="001") then

y<=not b;

elsif(sel="010") then

y<=a and b;

elsif(sel="011") then

y<=a or b;

elsif(sel="100") then

y<=a nand b;

elsif(sel="101") then

y<=a nor b;

elsif(sel="110") then

y<=a xor b;

elsif(sel="111") then
FA16-BCE-093 M.Afaq Khaliq

y<=a xnor b;

end if;

end process;

end archi;

Arithematic Function File

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity Arithematic is

port(

sel: in std_logic_vector(2 downto 0);

a: in std_logic_vector(7 downto 0);

b: in std_logic_vector(7 downto 0);

cin:in std_logic;

y: out std_logic_vector(7 downto 0)

);

end Arithematic;

architecture archi of Arithematic is

begin

process(sel,a,b)

begin

if(sel="000") then

y<=a;

elsif(sel="001") then
FA16-BCE-093 M.Afaq Khaliq

y<=a+"00000001";

elsif(sel="010") then

y<=a-"00000001";

elsif(sel="011") then

y<=b;

elsif(sel="100") then

y<=b+"00000001";

elsif(sel="101") then

y<=b-"00000001";

elsif(sel="110") then

y<=a+b;

elsif(sel="111") then

y<=a+b+cin;

end if;

end process;

end archi;

Waveform
FA16-BCE-093 M.Afaq Khaliq

Question II: Short Questions [3+3=6 Marks]

a) Write the syntax of package that must include package body with on example.
(PLO3-C3/CLO5)
FA16-BCE-093 M.Afaq Khaliq