DIGITAL ELECTRONICS

Number system conversions:

Decimal to Binary
Decimal numbers can be converted to binary by repeated division of the number by 2 while
recording the remainder. Let’s take an example to see how this happens.

The remainders are to be read from bottom to top to obtain the binary equivalent.
4310 = 1010112

Decimal to Octal
Decimal numbers can be converted to octal by repeated division of the number by 8 while
recording the remainder. Let’s take an example to see how this happens.

Reading the remainders from bottom to top,

47310 = 7318

Decimal to Hexadecimal
Decimal numbers can be converted to octal by repeated division of the number by 16 while
recording the remainder. Let’s take an example to see how this happens.

Reading the remainders from bottom to top we get,

42310 = 1A716

Binary to Octal and Vice Versa

To convert a binary number to octal number, these steps are followed −
 Starting from the least significant bit, make groups of three bits.
 If there are one or two bits less in making the groups, 0s can be added after the most
significant bit
 Convert each group into its equivalent octal number
Let’s take an example to understand this.

101100101012 = 26258
To convert an octal number to binary, each octal digit is converted to its 3-bit binary equivalent
according to this table.

Octal Digit 0 1 2 3 4 5 6 7

Binary Equivalent 000 001 010 011 100 101 110 111

546738 = 1011001101110112
Binary to Hexadecimal
To convert a binary number to hexadecimal number, these steps are followed −
 Starting from the least significant bit, make groups of four bits.
 If there are one or two bits less in making the groups, 0s can be added after the most
significant bit.
 Convert each group into its equivalent octal number.
Let’s take an example to understand this.

101101101012 = DB516
To convert an octal number to binary, each octal digit is converted to its 3-bit binary equivalent.
Logic gates are the basic building blocks of any digital system. It is an electronic circuit having
one or more than one input and only one output. The relationship between the input and the
output is based on a certain logic. Based on this, logic gates are named as AND gate, OR
gate, NOT gate etc.

AND Gate
A circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and one
output.

Logic diagram
Truth Table

OR Gate
A circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one
output.

Logic diagram

Truth Table

NOT Gate
NOT gate is also known as Inverter. It has one input A and one output Y.
Logic diagram

Truth Table

NAND and NOR gates(known as universal gates):

NAND Gate
A NOT-AND operation is known as NAND operation. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

NOR Gate
A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one output.
Logic diagram

Truth Table

XOR Gate
XOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full adder and
subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or sometime as X-OR gate. It
has n input (n >= 2) and one output.

Logic diagram
Truth Table

XNOR Gate
XNOR gate is a special type of gate. It can be used in the half adder, full adder and subtractor.
The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR gate. It has n
input (n >= 2) and one output.

Logic diagram

Truth Table

SR Flip-Flop with NAND gates:

The simplest way to make any basic single bit set-reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset
Bistable also known as an active LOW SR NAND Gate Latch, so that there is
feedback from each output to one of the other NAND gate inputs. This device
consists of two inputs, one called the Set, S and the other called the Reset, R with
two corresponding outputs Q and its inverse or complement Q (not-Q) as shown
below.

The Basic SR Flip-flop

The Set State

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and
input S is at logic level “1” (S = 1), the NAND gate Y  has at least one of its inputs at
logic “0” therefore, its output Q must be at a logic level “1” (NAND Gate principles).
Output Q is also fed back to input “A” and so both inputs to NAND gate X are at logic
level “1”, and therefore its output Q must be at logic level “0”.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to
logic “1” with S remaining HIGH also at logic level “1”, NAND gate Y inputs are
now R = “1” and B = “0”. Since one of its inputs is still at logic level “0” the output
at Q still remains HIGH at logic level “1” and there is no change of state. Therefore,
the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q = “0”.

Reset State
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output
at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has
one of its inputs at logic “0” its output Q must equal logic level “1” (again NAND gate
principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at
logic “1”, therefore, Q = “0”.
If the set input, S now changes state to logic “1” with input R remaining at logic “1”,
output Q still remains LOW at logic level “0” and there is no change of state.
Therefore, the flip-flop circuits “Reset” state has also been latched and we can
define this “set/reset” action in the following truth table.
Truth Table for this Set-Reset Function

State S R Q Q Description

1 0 0 1 Set Q » 1

Set

1 1 0 1 no change

0 1 1 0 Reset Q » 0

Reset

1 1 1 0 no change

Invalid 0 0 1 1 Invalid Condition

It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q can be
at either logic level “1” or “0”, depending upon the state of the
inputs S or R BEFORE this input condition existed. Therefore the condition
of S = R = “1” does not change the state of the outputs Q and Q.
However, the input state of S = “0” and R = “0” is an undesirable or invalid condition
and must be avoided. The condition of S = R = “0” causes both outputs Q and Q to
be HIGH together at logic level “1” when we would normally want Q to be the inverse
of Q. The result is that the flip-flop looses control of Q and Q, and if the two inputs
are now switched “HIGH” again after this condition to logic “1”, the flip-flop becomes
unstable and switches to an unknown data state based upon the unbalance as
shown in the following switching diagram.
S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting
in the flip-flop switching to one state or the other which may not be the required state
and data corruption will exist. This unstable condition is generally known as its Meta-
stable state.
Then, a simple NAND gate SR flip-flop or NAND gate SR latch can be set by
applying a logic “0”, (LOW) condition to its Set input and reset again by then
applying a logic “0” to its Reset input. The SR flip-flop is said to be in an “invalid”
condition (Meta-stable) if both the set and reset inputs are activated simultaneously.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both
inputs S and R are equal to logic level “1”. Due to this additional clocked input, a JK
flip-flop has four possible input combinations, “logic 1”, “logic 0”, “no change” and
“toggle”. The symbol for a JK flip flop is similar to that of an SR Bistable Latch as
seen in the previous tutorial except for the addition of a clock input.

JK Flip-flop:
Both the S and the R inputs of the previous SR bistable have now been replaced by
two inputs called the J and K inputs, respectively after its inventor Jack Kilby. Then
this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two
3-input NAND gates with the third input of each gate connected to the outputs
at Q and Q. This cross coupling of the SR flip-flop allows the previously invalid
condition of S = “1” and R = “1” state to be used to produce a “toggle action” as the
two inputs are now interlocked.
If the circuit is now “SET” the J input is inhibited by the “0” status of Q through the
lower NAND gate. If the circuit is “RESET” the K input is inhibited by the “0” status
of Q through the upper NAND gate. As Q and Q are always different we can use
them to control the input. When both inputs J and K are equal to logic “1”, the JK flip
flop toggles as shown in the following truth table.

The Truth Table for the JK Function

Clock Input Output

Description

Clk J K Q Q

X 0 0 1 0

Memory
no change

X 0 0 0 1
same as
for the
SR Latch
‾↓ ̲ 0 1 1 0

Reset Q » 0

X 0 1 0 1

‾↓ ̲ 1 0 0 1

Set Q » 1

X 1 0 1 0
 ‾↓ ̲ 1 1 0 1

toggle
Toggle
action

‾↓ ̲ 1 1 1 0

Then the JK flip-flop is basically an SR flip flop with feedback which enables only
one of its two input terminals, either SET or RESET to be active at any one time
thereby eliminating the invalid condition seen previously in the SR flip flop circuit.
Also when both the J and the K inputs are at logic level “1” at the same time, and the
clock input is pulsed “HIGH”, the circuit will “toggle” from its SET state to a RESET
state, or visa-versa. This results in the JK flip flop acting more like a T-type toggle
flip-flop when both terminals are “HIGH”.

Problems on Transformers
1) The core of a 100 KVA, 11000/550V, 50Hz single phase core type transformer has
a cross section of 20cm x 20cm Find:
i) The Number of H.V. & L.V. turns per phase and
ii) The emf per turn if the maximum core density is not to exceed 1.3 Tesla.
Assume a stacking factor of 0.9.
What will happen if the primary voltage is increased by 10% on no-load?
SOL: Given
Primary voltage, E1 = 11000 V
Secondary voltage, E2 = 550 V
Frequency, f = 50 Hz
Area of the cross section of the core, A = 20cm x 20cm
= 400 cm 2 = 0.04 m2
Maximum flux density, Bm = 1.3 T
Stacking factor = 0.9
∴ Maximum flux, Φmax = Bm × A × Stacking factor
= 1.3 × 0.04 × 0.9
= 46.8 × 10 -3 Wb = 46.8 mWb
i) We know, emf induced in primary winding, E 1 = 4.44 f N1 ϕm
11000 = 4.44 × 50 × N1 × 46.8 × 10-3
11000
−3
∴ HV turns per phase, N1 = 4 . 44×50×46 . 8×10
N1 = 1058.75 ≃ 1059
 emf induced in secondary winding E2 = 4.44 f N2 ϕm
550 = 4.44 × 50 × N2 × 46.8 × 10-3
550
−3
∴ LV turns per phase, N2 = 4. 44×50×46 . 8×10
N2 = 52.9 ≃ 53

E1 E2
ii) emf per turn = N 1 or N 2
11000
=10.38
= 1059 V
Keeping supply frequency constant, if primary voltage is increased by
10%, magnetizing current will increase by much more than 10%. However, due to
saturation, flux density will increase only marginally and so will the eddy current and
hysteresis losses.

2) The maximum flux density in the core of a 250/3000 V, 50 Hz single phase

transformer is 1.2 wb/m2. If the e.m.f per turn is 8 volts, Determine i)
Primary and secondary turns ii) Area of the core
SOL: Given
Primary voltage, E1 = 250 V
Secondary voltage, E2 = 3000 V
Frequency, f = 50 Hz
Maximum flux density, Bm = 1.2 Wb/m2
Emf/turn = 8 V
i) Number of primary turns, N1 = E1/8
250
=32
N1 = 8
Number of secondary turns, N2 = E2/8
3000
=375
N2 = 8
ii) emf induced in secondary winding E2 = 4.44 f N2 Bm A
3000 = 4.44 × 50 × 375 × 1.2 × A
3000
∴ Area of the core, A = 4.44×50×375×1.2
 A = 0.03 m2

(3) In a 25 KVA, 2000/200V, single phase transformer the iron and full load
copper losses are 350 W and 400W, respectively. Calculate the efficiency
at unity power factor on i) Full load ii) half full load.
SOL: Given
Primary voltage, V1 = 2000 V
Secondary voltage, V2 = 200 V
Rating of transformer = 25 KVA
Iron losses = 350 W
Cu losses = 400 W
(i) At full-load :
Total losses = Iron losses + Cu losses
= 350 + 400 = 750 W
Output at unity power factor = Rating of transformer × pf
= 25 × 1 = 25 KW
Output
×100
∴ Efficiency, η = Output +Losses
25×10 3
3
×100
= 25×10 +750 = 97 %
(ii) At half-load :
2
1
On half-load, Cu losses =
400× ()2 = 100 W
Iron losses are remain constant, i.e. 350 W
Total losses = 100 + 350 = 450 W
25
×1
On half-load, Output at unity power factor = 2 = 12.5 KW
Output
×100
∴ Efficiency, η = Output +Losses
12. 5×10 3
3
×100
= 12. 5×10 +450= 96.5 %
(4) A 15 KVA, 1000/400 Volts single phase transformer gave the following
test
 results
Open circuit test: 400 V, 0.8 A, 50 W
Short circuit test: 60V, 10A, 45 W
Calculate the efficiency and voltage regulation at full load 0.85 power factor lag.
SOL: Given
Rating of the transformer = 15 KVA
Primary voltage, V1 = 1000 V
Secondary voltage, V2 = 400 V
Power factor, cosΦ = 0.85 lagging
3
VA 15×10
= =15
Full-load or Rated current, I1 = V 1 1000 A
Core losses from OC test = 50 W
Cu losses from SC test = 45 W
SC test data have been given at 10A current.
15 2
∴ Cu losses at 15A = 10
( ) ×45
= 101.25 W
Total losses = 50 + 101.25 = 151.25 W
At 0.85 pf lagging, power output = 15KVA × 0.85
= 15 × 10 3 × 0.85 = 12.75 KW
Output
×100
∴ Efficiency, η = Output +Losses
12. 75×10 3
3
×100
= 12. 75×10 +151 .25 = 98.8 %

From SC test,
V SC 60
= =6
Impedance, Z = I SC 10 Ω
P SC 45
= =0 . 45
Resistance, R = I 2SC 102 Ω
Reactance, X = √ Z 2−R2=√ 62−0 . 452=5. 98 Ω
I 1 R cos φ+I 1 X sin φ
×100
% Regulation = V 1
15×0.45×0 . 85+15×5 . 98×0 .526
×100
= 1000
% Regulation = 5.29 %