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Acer Aspire 4741z 4741zg 5741 5741g 5741z 5741zg - Compal La-5891p - Rev 1.0 197 PDF
Acer Aspire 4741z 4741zg 5741 5741g 5741z 5741zg - Compal La-5891p - Rev 1.0 197 PDF
1 1
Compal Confidential
2 2
3 2010-01-07 3
REV:1.0
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Friday, January 08, 2010 Sheet 1 of 59
A B C D E
A B C D E
Clock Generator
Compal Confidential IDT: 9LVS3199AKLFT
Model Name : NEW50/70/80/90 Realtek: RTM890N-631-VB-GRT
133/120/100/96/14.318MHZ to PCH
File Name : LA5891P Fan Control
page 38 page 12
1 1
LVDS(DIS) Processor
rPGA988A
page 4,5,6,7,8,9
HDMI(DIS) CRT(DIS)
FDI x8 DMI x4 USB conn x3 Bluetooth CMOS Camera Card Reader
(UMA) USB port 1 Conn RTS5160
USB port 0, 2 on USB port 11 USB port 8 USB port 9
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 36 page 36 page 29 page 36
page 31 page 30 page 29 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
HDMI(UMA) LVDS(UMA)
CRT(UMA) Intel 3.3V 24MHz
HDMI HD Audio
Level Shift TMDS(UMA) Ibex Peak-M
page 31
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz PCH HDA Codec
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz page 13,14,15,16 ALC272X
port 2 port 1 17,18,19,20,21
SPI page 40
page 34
33MHz
Int. Speaker Phone Jack x 2
Sub-board ENE KB926 page 41 page 41
page 37
LS-5891P
USB/B 2Port
RTC CKT. USB Port0,2 page 36
page 15
Touch Pad Int.KBD
page 38 page 38
LS-5892P
Power On/Off CKT. Card Reader CPU XDP
page 34 USB Port9 page 36 page 5
BIOS ROM
page 38
DC/DC Interface CKT. LS-5893P LS-5894P PCH XDP
4
page 38 Power/B LID_SW/B 4
page 38 page 21
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
A B C D E
5 4 3 2 1
JCPU1E
DMI_PTX_HRX_N0
10mil PEG_ICOMPO A26
R493
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS 1 2 750_0402_1% AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
DMI_PTX_HRX_N3
B22 DMI_RX#[2] 15mil PEG_GTX_C_HRX_N15 C69 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N15
AL24 RSVD3 RSVD35 AK26
A21 DMI_RX#[3] PEG_RX#[0] K35 1 2 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 C72 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 C76 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 1 2 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 C84 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7
DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 C87 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 C96 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 1 2 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 C105 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N9 H17
DMI_HTX_PRX_N0 PEG_RX#[6] PEG_GTX_C_HRX_N8 C106 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N8 SB_DIMM_VREF (CFD Only)
D24 DMI_TX#[0] PEG_RX#[7] D35 1 2 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PEG_GTX_C_HRX_N7 C121 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N7 G17
DMI_HTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 C123 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N6 RSVD12
F23 DMI_TX#[2] PEG_RX#[9] C33 1 2 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PEG_GTX_C_HRX_N5 C129 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4 C141 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32 1 2
DMI_HTX_PRX_P0 D25 C31 PEG_GTX_C_HRX_N3 C149 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N3 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 C160 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N2 RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 1 2 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PEG_GTX_C_HRX_N1 C161 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N1
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0 C167 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_N0
G23 DMI_TX[3] PEG_RX#[15] A31 1 2
H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 C140 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P5 CFG9 AK31 AT34
RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 C142 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P4 CFG10 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 1 2 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PEG_GTX_C_HRX_P3 C151 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P3 WW41 Recommend not pull down CFG11 AJ28 AR35
H_FDI_TXP0 PEG_RX[12] PEG_GTX_C_HRX_P2 C153 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P2 CFG12 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 1 2 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
H_FDI_TXP1 C21 B29 PEG_GTX_C_HRX_P1 C165 1 2 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P1 CFG13 AN32
H_FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 C174 DIS@ 0.1U_0402_16V7K PEG_GTX_HRX_P0 CFG14 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 1 2 AJ32 CFG[14]
H_FDI_TXP3 C18 CFG15 AJ29 E15
C H_FDI_TXP4 FDI_TX[3] PEG_HTX_GRX_N15 C586 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 CFG16 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
H_FDI_TXP5 E20 M35 PEG_HTX_GRX_N14 C561 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 CFG17 AK30 A2
H_FDI_TXP6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C584 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 CFG18 CFG[17] KEY R146
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
H_FDI_TXP7 G19 M30 PEG_HTX_GRX_N12 C559 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C582 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
F17 K32 PEG_HTX_GRX_N10 C557 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
15 H_FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
E17 M29 PEG_HTX_GRX_N9 C580 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R147
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C555 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8 B19 0_0402_5%
PEG_TX#[7] PEG_HTX_GRX_N7 C578 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7 R497 RSVD15
15 H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C553 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6 0_0402_5%
PEG_TX#[9] PEG_HTX_GRX_N5 C576 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5 @ H_RSVD17_R
15 H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
D17 F29 PEG_HTX_GRX_N4 C551 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
15 H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C574 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C549 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2 R501 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C572 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C547 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C585 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C560 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C583 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P13 R9
PEG_TX[2] DMI_PTX_HRX_N[0..3] 15 RSVD_TP_73
L30 PEG_HTX_GRX_P12 C558 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P12 AG7
PEG_TX[3] DMI_PTX_HRX_P[0..3] 15 RSVD_TP_74
M31 PEG_HTX_GRX_P11 C581 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P10 C556 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P10 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[5] K31 1 2 DMI_HTX_PRX_N[0..3] 15 A3 RSVD_NCTF_24
M28 PEG_HTX_GRX_P9 C579 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_TX[6] DMI_HTX_PRX_P[0..3] 15
H31 PEG_HTX_GRX_P8 C554 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P8 V4
PEG_TX[7] PEG_HTX_GRX_P7 C577 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P7 RSVD_TP_76
PEG_TX[8] K28 1 2 H_FDI_TXN[0..7] 15 RSVD_TP_77 V5
G30 PEG_HTX_GRX_P6 C552 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6 N2
PEG_TX[9] H_FDI_TXP[0..7] 15 RSVD_TP_78
G29 PEG_HTX_GRX_P5 C575 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5 J29 AD5
PEG_TX[10] PEG_HTX_GRX_P4 C550 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4 RSVD26 RSVD_TP_79
PEG_TX[11] F28 1 2 J28 RSVD27 RSVD_TP_80 AD7
B PEG_HTX_GRX_P3 C573 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3 B
PEG_TX[12] E27 1 2 PEG_GTX_HRX_N[0..15] 22 RSVD_TP_81 W3
D28 PEG_HTX_GRX_P2 C548 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2 A34 W2
PEG_TX[13] PEG_GTX_HRX_P[0..15] 22 RSVD_NCTF_28 RSVD_TP_82
C27 PEG_HTX_GRX_P1 C571 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1 A33 N3
PEG_TX[14] PEG_HTX_GRX_P0 C546 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0 RSVD_NCTF_29 RSVD_TP_83
PEG_TX[15] C25 1 2 PEG_HTX_C_GRX_N[0..15] 22 RSVD_TP_84 AE5
PEG_HTX_C_GRX_P[0..15] 22 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS
IC,AUB_CFD_rPGA,R1P0
CONN@
eDP Signals Mapping CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence
H_FDI_FSYNC0 R519 1 DISO@ 2 1K_0402_5%
H_FDI_FSYNC1 R517 1 DISO@ 2 1K_0402_5%
eDP Singal PEG Singals Lane Reversal *1:Single PEG *1:Disabled; No Physical Display Port
H_FDI_INT R513 1 DISO@ 2 1K_0402_5%
eDP_TX0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P0 0:Bifurcation enabled attached to Embedded Display Port
H_FDI_LSYNC0 R520 1 DISO@ 2 1K_0402_5% 0:Enabled; An external Display Port
eDP_TX#0 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N0 H_FDI_LSYNC1 R515 1 DISO@ 2 1K_0402_5% device is connected to the Embedded
eDP_TX1 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P1 CheckList0.8 1.22 Display Port
Auburndale Graphics Disable CFG3 - PCI-Express Static Lane Reversal
eDP_TX#1 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N1 *:Default
A eDP_TX2 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P2 *1 :Normal Operation A
0 :Lane Numbers Reversed
eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N2 15 -> 0, 14 -> 1, ...
eDP_TX3 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P3
eDP_TX#3 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N3 Security Classification Compal Secret Data Compal Electronics, Inc.
eDP_AUX PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P2 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
eDP_AUX# PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
eDP_HPD# PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 4 of 59
5 4 3 2 1
5 4 3 2 1
JCPU1B
R512 2 1 20_0402_1% H_COMP3 AT23 COMP3
BCLK A16 CLK_CPU_BCLK 18
MISC
R507 2 1 20_0402_1% H_COMP2 AT24 B16
COMP2 BCLK# CLK_CPU_BCLK# 18
R521 2 1 49.9_0402_1% H_COMP1 CLK_CPU_XDP 2009/08/14
CLOCKS
G16 COMP1 BCLK_ITP AR30
AT30 CLK_CPU_XDP#
R503 2 BCLK_ITP# remove DP REF SSCLK
1 49.9_0402_1% H_COMP0 AT26 COMP0
PEG_CLK E16 CLK_CPU_DMI 14
PEG_CLK# D16 CLK_CPU_DMI# 14
PAD @ SKTOCC#_R AH24 CLK_CPU_DP_R R504 1 2 0_0402_5%
T7 SKTOCC#
A18 CLK_CPU_DP_R CLK_CPU_DP#_R R510 1 2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP#_R
D
DPLL_REF_SSCLK# A17 D
H_CATERR# AK14 CATERR# +1.05VS_VTT
THERMAL
2009/08/14 #425302
CP_S3PowerReduction
SM_DRAMRST# F6 SM_DRAMRST# 10
R547 1 2 H_PECI_R AT15 WhitePaper_Rev1.0 XDP_PRDY# R89 1 @ 2 51_0402_5%
18 H_PECI PECI
0_0402_5% AL1 SM_RCOMP_0 1 2 XDP_TMS R496 1 @ 2 51_0402_5%
SM_RCOMP[0] SM_RCOMP_1 R567 100K_0402_5% +1.05VS_VTT XDP_TDI_R R495 @ 51_0402_5%
SM_RCOMP[1] AM1 1 2
AN1 SM_RCOMP_2 XDP_PREQ# R90 1 @ 2 51_0402_5%
H_PROCHOT# SM_RCOMP[2] R539 1
54 H_PROCHOT# AN26 PROCHOT# 2 10K_0402_5% XDP_TCLK R62 1 @ 2 51_0402_5%
AN15 PM_EXTTS#0 R538 1 2 10K_0402_5%
PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1_R R548 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 10,11
R124 1 2 H_THERMTRIP#_R AK15
18 H_THERMTRIP# THERMTRIP#
0_0402_5%
XDP_TRST# R499 1 2 51_0402_5%
AT28 XDP_PRDY#
PRDY# XDP_PREQ# SM_RCOMP_0 R578 1
PREQ# AP27 2 100_0402_1%
SM_RCOMP_1 R576 1 2 24.9_0402_1%
AN28 XDP_TCLK SM_RCOMP_2 R573 1 2 130_0402_1%
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28
PWR MANAGEMENT
AT27 XDP_TRST#
TRST# XDP_TDI_R R488 1 2 0_0402_5% XDP_TDI
1
AR29 XDP_TDI_M
R122 1 H_CPUPW RGD_1 TDI_M XDP_TDO_M R480
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% 0_0402_5%
AN25 XDP_DBR#_R R87 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21
C R121 1 H_CPUPW RGD_0 DBR# C
18 H_CPUPW RGD 2 AN27
2
0_0402_5% VCCPWRGOOD_0 XDP_TDI_M @
1 2
AJ22 XDP_OBS0 XDP_TDO_R R481 1 2 0_0402_5%
R150 1 PM_DRAM_PW RGD_R BPM#[0] XDP_OBS1 R476 0_0402_5%
15 PM_DRAM_PW RGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22
0_0402_5% AK24 XDP_OBS2
BPM#[2] XDP_OBS3
BPM#[3] AJ24
H_VTTPW RGD 1 @ 2 H_VTTPW RGD_R AM15 AJ25 XDP_OBS4
R540 0_0402_5% VTTPWRGOOD BPM#[4] XDP_OBS5
BPM#[5] AH22
XDP_OBS6
JTAG MAPPING 2009/09/16 update
BPM#[6] AK23
H_PW RGD_XDP R489 1 2 H_PW RGD_XDP_R AM26 AH23 XDP_OBS7
0_0402_5% TAPPWRGOOD BPM#[7]
Scan Chain STUFF -> R488 , R480 , R476
(Default) NO STUFF -> R475 , R481
R126 1 2 PLT_RST#_R AL14 2009/2/4
17,21,33,37 PLT_RST# RSTIN#
1.5K_0402_1% Delete dampling resistor for
power noise and Layout space CPU Only STUFF -> R488 ,R475
1
+1.05VS_VTT
19 GND6 GND7 20
MC74VHC1G08DFT2G_SC70-5 R542 21 22
3
OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
1K_0402_1% 25 26 R83
XDP_OBS4 GND8 GND9 1K_0402_5%
27 28
2
C211 49 50 1K_0402_5%
GND14 GND15
1
A GND16 GND17 A
R149
R148
@ 750_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
3.01K_0402_1% 2009/04/23 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
2
JCPU1D
11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
JCPU1C
10 DDR_A_D[0..63] 11 DDR_B_DQS#[0..7]
10 DDR_A_DM[0..7] 11 DDR_B_DQS[0..7]
10 DDR_A_DQS#[0..7] 11 DDR_B_MA[0..15]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 11
SB_CK#[0] W9 DDR_B_CLK0# 11
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 10 SB_DQ[0] SB_CKE[0] DDR_B_CKE0 11
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# 10 SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 10 SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 11
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# 11
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 11
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 10 SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# 10 SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 10 SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# 11
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# 11
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# 10 SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# 10 SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 11
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 11
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 10 SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 10 SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A
IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
A
CONN@ A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 6 of 59
5 4 3 2 1
5 4 3 2 1
JCPU1F
WW15 MOW
+CPU_CORE
Peak 21A +1.05VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +CPU_CORE
VCC3 VTT0_3
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1
D C258 C274 C286 C282 C288 C284 C281 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 VCC5 VTT0_5 J14
AG30 VCC6 VTT0_6 J13
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
AG28 H12 2 2 2 2 2 2 2 C676 C677 C669 C674 C657 C652 C679 C262 C232
VCC8 VTT0_8
AG27 G14
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 VCC10 VTT0_10 G13
AF35 G12 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
VCC11 VTT0_11
AF34 VCC12 VTT0_12 G11
AF33 F14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC13 VTT0_13
AF32
VCC14 VTT0_14
F13 (Place these capacitors between inductor and socket on Bottom)
AF31 VCC15 VTT0_15 F12
AF30 F11 +1.05VS_VTT
VCC16 VTT0_16 +CPU_CORE
AF29 VCC17 VTT0_17 E14
AF28 E12
VCC18 VTT0_18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF27 D14 1 1
VCC19 VTT0_19
AF26 D13
VCC20 VTT0_20 + +
VCC62
V33 VCC63
V32 AK35 CPU_VID0 54 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC64 VID[0]
V31
VCC65 VID[1]
AK33 CPU_VID1 54 (Place these capacitors on CPU cavity, Bottom Layer)
V30 AK34 CPU_VID2 54
VCC66 VID[2]
V29 AL35 CPU_VID3 54
VCC67 VID[3]
CPU VIDS
16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16
+VGFX_CORE
JCPU1G
10U_0805_6.3V6M
22U_0805_6.3V6M AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 53
SENSE
LINES
1 1 1 1 1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 53
1
0.1U_0402_16V4Z
C610
C250 C272 C673 C672 AT16
R514 C675 + VAXG4
D AR21 VAXG5 D
0_0402_5% UMA@ UMA@ UMA@ UMA@ UMA@ AR19
2 2 2 2 2 VAXG6
DISO@ AR18 VAXG7
2 GFXVR_EN
AR16 AM22 GFXVR_VID_0 53 1 2
2
GRAPHICS VIDs
330U_X_2VM_R6M 22U_0805_6.3V6M AP19 AN22
VAXG10 GFX_VID[2] GFXVR_VID_2 53
10U_0805_6.3V6M AP18 AP23
VAXG11 GFX_VID[3] GFXVR_VID_3 53
AP16 VAXG12 15A GFX_VID[4] AM23 GFXVR_VID_4 53
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 53
GRAPHICS
AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 53
- 1.5V RAILS
VAXG27 VDDQ3 C307 C308 C309 C306 C310 C303 C315 + C326
AK16 VAXG28 VDDQ4 AE4
AJ21 AC1 330U_D2_2V_Y
VAXG29 VDDQ5 J2
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4 2 2 1 1 +1.5VS
AJ16 VAXG32 3A VDDQ8 Y1
@ JUMP_43X118
AH21 VAXG33 VDDQ9 W7
POWER
C AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18
AH16
VAXG35 VDDQ11 U1
T7
Short for +1.5VS to +1.5V_1
VAXG36 VDDQ12
VDDQ13 T4
VDDQ14 P1
+1.05VS_VTT N7
VDDQ15
VDDQ16 N4 11/03 add four 0.1u 0402
DDR3
VDDQ17 L1 Intel suggest for S3 reduse
J24 VTT1_45 VDDQ18 H1
FDI
J23 VTT1_46
H25 +1.5V_1 +1.5V
1 1 VTT1_47
C253 C260 +1.05VS_VTT
C797
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1 2 0.1U_0402_16V4Z
2 2 VTT0_59
VTT0_60 N10
L10 1 C798
VTT0_61 C267 0.1U_0402_16V4Z
VTT0_62 K10 1 2
+1.05VS_VTT 10U_0805_6.3V6M C799
2 0.1U_0402_16V4Z
1 2
+1.05VS_VTT
1.1V
J22 C800
VTT1_63 0.1U_0402_16V4Z
K26 VTT1_48 VTT1_64 J20 1 2
J27 VTT1_49 VTT1_65 J18 1
1.8V
E25 0.6A L27 40mil 0_0805_5%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V4Z
VCCPLL3 M26 1 2
1 1 1 1 1
C230 C224 C235 C234 C233
1U_0402_6.3V4Z
2 2 2 2 2 22U_0805_6.3V6M
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 8 of 59
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 H_NCTF6 @
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 PAD T18
AJ23 T28 D3 A35 H_NCTF7 @ PAD T15
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
B B
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 9 of 59
5 4 3 2 1
5 4 3 2 1
+1.5V +1.5V
DIMMA VREFDQ M1 Circuit JDIMM1
6 DDR_A_DQS#[0..7]
+DIMM_VREFDQA 1 VREF_DQ VSS1 2
+1.5V 3 4 DDR_A_D4
6 DDR_A_D[0..63] VSS2 DQ4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
6 DDR_A_DM[0..7] 1 1 7 DQ1 VSS3 8
1
C401 C402 9 10 DDR_A_DQS#0
R222 +DIMM_VREFDQA DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
6 DDR_A_DQS[0..7] 11 DM0 DQS0 12
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 13 14
1K_0402_1% 2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
6 DDR_A_MA[0..15] 15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
20mil 17 18
2
DQ3 DQ7
19 20
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 DQ8 DQ12 22
1
DDR_A_D9 23 24 DDR_A_D13
R227 DQ9 DQ13
25 VSS9 VSS10 26
D DDR_A_DQS#1 DDR_A_DM1 D
27 DQS#1 DM1 28
1K_0402_1% DDR_A_DQS1 29 30 DIMM_DRAMRST#
DQS1 RESET#
31 32
2
DDR_A_D24 57 58 DDR_A_D29
R203 +DIMM_VREFCA DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
1K_0402_1% DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
20mil 65 66
2
71 72
WhitePaper_Rev1.0 VSS25 VSS26
1
R201 R254
0_0402_5% R274
1K_0402_1% 1 @ 2
1K_0402_1% DDR_A_CKE0 73 74 DDR_A_CKE1
6 DDR_A_CKE0 DDR_A_CKE1 6
2
CKE0 CKE1
75 76
2
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78
D
3 1 DIMM_DRAMRST# DDR_A_BS2 79 80 DDR_A_MA14
5 SM_DRAMRST# DIMM_DRAMRST# 11 6 DDR_A_BS2 BA2 A14
Q17 81 82
BSS138LT1G_SOT23-3 DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 84
C DDR_A_MA9 A12/BC# A11 DDR_A_MA7 C
85 86
G
C422
2
A9 A7
87 88
RST_GATE DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
18 RST_GATE 1 2 89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
0.047U_0402_16V7K DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 100
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
6 DDR_A_CLK0 101 CK0 CK1 102 DDR_A_CLK1 6
DDR_A_CLK0# 103 104 DDR_A_CLK1#
6 DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# 6
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
DDR_A_BS0 109 110 DDR_A_RAS#
6 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 6
111 112
DDR_A_WE# VDD13 VDD14 DDR_A_CS0#
113 114 DDR_A_CS0# 6
6 DDR_A_WE# DDR_A_CAS# WE# S0# DDR_A_ODT0
6 DDR_A_CAS# 115 116 DDR_A_ODT0 6
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16 DDR_A_ODT1 +DIMM_VREFCA
119 120 DDR_A_ODT1 6
DDR_A_CS1# A13 ODT1
6 DDR_A_CS1#
121
S1# NC2
122 20mil
123 VDD17 VDD18 124
125 126 DDR_VREF_CA_DIMMA R202 1 2 0_0402_5%
NCTEST VREF_CA
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36
129 130
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
Layout Note: DDR_A_DQS#4
133
VSS29 VSS30
134
DDR_A_DM4
135 136
Place near JDIMM1 DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138 1 1
139 140 DDR_A_D38 C358 C361
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 142
DDR_A_D35 DQ34 DQ39 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
Layout Note: Place these 4 Caps near Command 143
DQ35 VSS33
144
DDR_A_D44 2 2
145 146
and Control signals of DIMMA DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
B DDR_A_D41 DQ40 DQ45 B
149 DQ41 VSS35 150
+1.5V 151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
1
1 1 1 1 1 1 1 1 1 1 161 162
C354 C355 C356 C405 C404 C406 C362 C363 C399 C400 + C425 DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
330U_2.5V_M_R15 DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
@ DQ49 DQ53
167 168
2
1 1 1 1 1
C394
DDR3 SO-DIMM A
C391
2
C388
2
C397
2
C396
2 2
10U_0805_6.3V6M H=8mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
1U_0402_6.3V4Z 1U_0402_6.3V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 10 of 59
5 4 3 2 1
5 4 3 2 1
+1.5V
+1.5V
2008/9/8 #400755 JDIMM2
6 DDR_B_DQS#[0..7] Calpella Clarksfield +DIMM_VREFDQB 1 2
VREF_DQ VSS1 DDR_B_D4
3 4
DDR3 SO-DIMM DDR_B_D0 5
VSS2 DQ4
6 DDR_B_D5
6 DDR_B_D[0..63] 1 1 DQ0 DQ5
VREFDQ Platform C433 C431 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
6 DDR_B_DM[0..7] Design Guide Change Details 9 VSS4 DQS#0 10
2.2U_0603_6.3V4Z DDR_B_DM0 11 12 DDR_B_DQS0
2 2 DM0 DQS0
6 DDR_B_DQS[0..7] 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
6 DDR_B_MA[0..15] 17 DQ3 DQ7 18
0.1U_0402_16V4Z 19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 DQ8 DQ12 22
D DDR_B_D9 DDR_B_D13 D
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 30 DIMM_DRAMRST# 10
DQS1 RESET#
DIMMB VREFDQ M1 Circuit 31
VSS11 VSS12
32
DDR_B_D10 33 34 DDR_B_D14
+1.5V DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DQ16 DQ20
1
DDR_B_D17 41 42 DDR_B_D21
R282 +DIMM_VREFDQB DQ17 DQ21
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
1K_0402_1% DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
20mil 49 50 DDR_B_D22
2
55 56 DDR_B_D28
R281 DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
1K_0402_1% 61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 64
2
DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
71 72
VSS25 VSS26
DDR_B_CKE0 73 74 DDR_B_CKE1
6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 80
C BA2 A14 C
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
101 CK0 CK1 102 DDR_B_CLK1 6
6 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1#
103 104 DDR_B_CLK1# 6
6 DDR_B_CLK0# CK0# CK1#
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 6
6 DDR_B_BS0 109 110 DDR_B_RAS# 6
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_B_CS0#
113 114 DDR_B_CS0# 6
6 DDR_B_WE# DDR_B_CAS# WE# S0# DDR_B_ODT0
6 DDR_B_CAS# 115 116 DDR_B_ODT0 6
CAS# ODT0
Layout Note: DDR_B_MA13
117
VDD15 VDD16
118
DDR_B_ODT1
119 A13 ODT1 120 DDR_B_ODT1 6
Place near JDIMM2 DDR_B_CS1# 121 122 20mil +DIMM_VREFCA
6 DDR_B_CS1# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB R270 1
Layout Note: Place these 4 Caps near Command 125 126 2 0_0402_5%
NCTEST VREF_CA
127 128
and Control signals of DIMMB DDR_B_D32 129
VSS27 VSS28
130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
+1.5V DQ33 DQ37
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_B_D38 C414 C415
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142
DQ34 DQ39
1
B C437 C436 C420 C418 C416 C429 C430 C417 C419 + C395 145 146 DDR_B_D44 B
330U_2.5V_M_R15 DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
2
1U_0402_6.3V4Z 1U_0402_6.3V4Z
2.2U_0603_6.3V4Z
2 2
0.1U_0402_16V4Z FOX_AS0A626-U4RN-7F
CONN@
DDR3 SO-DIMM B
H=4mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 11 of 59
5 4 3 2 1
A B C D E F G H
L74 2 1
FBMA-L11-201209-221LMA30T_0805
SM010014520 3000ma 220ohm@100mhz DCR 0.04 @ +CLK_1.5VS
40mil
+1.5VS L75 2 1 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1
C768 C742 C771 C769
C781
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2
0.1U_0402_16V4Z
2 +CLK_3VS 2
+CLK_3VS
1 32 D_CK_SCLK
VDD_USB_48 SCL D_CK_SCLK 10,11
2 31 D_CK_SDATA
VSS_48M SDA D_CK_SDATA 10,11
CLK_BUF_DREF_96M 3 30 REF_0/CPU_SEL R682 1 2 33_0402_5%
14 CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M 14
CLK_BUF_DREF_96M# 4 29
14 CLK_BUF_DREF_96M# DOT_96# VDD_REF
5 28 CLK_XTAL_IN
R679 1 @ VDD_27 XTAL_IN
23 VGA_CLK_27M 2 33_0402_5% 27M_CLK 6 27MHZ XTAL_OUT 27 CLK_XTAL_OUT
R719 1 @ 2 33_0402_5% 27M_CLK_SS 7 26
27MHZ_SS VSS_REF CK505_PW RGD
8 USB_48 CKPWRGD/PD# 25
9 VSS_27M VDD_CPU 24
CLK_BUF_PCIE_SATA 10 23 CLK_BUF_CPU_BCLK
14 CLK_BUF_PCIE_SATA SATA CPU_0 CLK_BUF_CPU_BCLK 14
CLK_BUF_PCIE_SATA# 11 22 CLK_BUF_CPU_BCLK#
14 CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# 14
12 VSS_SRC VSS_CPU 21
CLK_BUF_CPU_DMI 13 20
14 CLK_BUF_CPU_DMI SRC_1 CPU_1
CLK_BUF_CPU_DMI# 14 19
14 CLK_BUF_CPU_DMI# SRC_1# CPU_1#
+CLK_1.05VS 15 VDD_SRC_IO VDD_CPU_IO 18 +CLK_1.05VS
H_STP_CPU# 16 17 +CLK_1.5VS
CPU_STOP# VDD_SRC
33 TGND
IDT SA00003HR00
SLG8SP587VTR_QFN32_5X5
2
+3VS
Silego Have Internal Pull-Up Realtek: RTM890N-631-VB-GRT, SA00003HQ10 R693
IDT 9LVS3199AKLFT NC 10K_0402_5%
R691
R690 1 2 10K_0402_5% H_STP_CPU# +3VS 0_0402_5%
1
R678 CK505_PW RGD 1 @ 2 VGATE 15,54
4.7K_0402_5%
D
2
1
G
1 2 +3VS
2 CLK_ENABLE# 54
IDT Have Internal Pull-Down 14,21,35 PCH_SMBDATA 1 3 D_CK_SDATA G
S Q48
D
3
FOR Realtek Q46 2N7002E-T1-GE3_SOT23-3
2N7002E-T1-GE3_SOT23-3
CLK_XTAL_IN
G
1 2 +3VS 2 1
1
PIN 30 CPU_0 CPU_1 14,21,35 PCH_SMBCLK 1 3 D_CK_SCLK 27P_0402_50V8J
Y4
D
2
4 4
Change to 5x3.2 CLK_XTAL_OUT 2 1
1 100MHz 100MHz
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 12 of 59
A B C D E F G H
5 4 3 2 1
+RTCBATT
+RTCVCC 1 2 PCH_RTCRST#
R215 C723
2
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1 R336
close to RAM door X2
20mil 1K_0402_5%
1
1 2 3 4
1
R671 @ NC OSC R615
10K_0603_5% 2 1
C366 NC OSC 10M_0402_5% U41A +RTCBATT_R
1U_0603_10V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0
1
1 2 C722 B13 D33 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 37
D 2 1 PCH_RTCX2 D13 B33 LPC_AD1 D
RTCX2 FWH1 / LAD1 LPC_AD1 37
C32 LPC_AD2 D8
FWH2 / LAD2 LPC_AD2 37
18P_0402_50V8J A32 LPC_AD3 BAS40-04_SOT23-3
FWH3 / LAD3 LPC_AD3 37
+RTCVCC 1 2 PCH_SRTCRST# PCH_RTCRST# C14 +RTCVCC
R214 RTCRST# LPC_FRAME#
C34 LPC_FRAME# 37 20mil
2
20K_0402_1% +RTCVCC PCH_SRTCRST# FWH4 / LFRAME#
RC Delay 18~25mS D17 SRTCRST# +CHGRTC
A34 1
RTC
LPC
R213 1 LDRQ0#
close to RAM door 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34 C724
1 2 modify to 330K 20mil
R675 @ R212 1 2 330K_0402_1% PCH_INTVRMEN A14 AB9 SERIRQ 0.1U_0402_16V4Z
INTVRMEN SERIRQ SERIRQ 37 2
10K_0603_5%
C365 INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs
1U_0603_10V6K HDA for AUDIO
1 2 40 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH A30
R330 33_0402_5% HDA_BCLK SATA_DTX_C_PRX_N0
SATA0RXN AK7 SATA_DTX_C_PRX_N0 32
(HDA_SYNC Have internal Pull-Down) 40 HDA_SYNC_AUDIO 1 2 HDA_SYNC_PCH D29 AK6 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_P0 32 SATA for HDD1
R327 33_0402_5% HDA_SYNC SATA0RXP SATA_PTX_DRX_N0
SATA0TXN AK11 SATA_PTX_DRX_N0 32
HDA_SYNC (SPKR Have internal Pull-Down) 40 PCH_SPKR PCH_SPKR P1 AK9 SATA_PTX_DRX_P0
SPKR SATA0TXP SATA_PTX_DRX_P0 32
On Die PLL VR is supplied by HDA_RST_PCH#
40 HDA_RST_AUDIO# 1 2 C30 HDA_RST#
1.5V when sampled High, R328 33_0402_5% AH6 SATA_DTX_C_PRX_N1
SATA1RXN SATA_DTX_C_PRX_N1 32
1.8V when sampled Low. AH5 SATA_DTX_C_PRX_P1 SATA_DTX_C_PRX_P1 32 SATA for ODD
SATA1RXP SATA_PTX_DRX_N1
40 HDA_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 32
AH8 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 32
F30 HDA_SDIN1
+3VS R650 AF11
1K_0402_5% SATA2RXN
E32 AF9 2/10 SATA2, SATA3 not support on HM55
IHDA
@ PCH_SPKR HDA_SDIN2 SATA2RXP
1 2 HDA_SDO ,This signal has a weak internal pull-down SATA2TXN AF7
Have internal PD resistor. Should not be Pull High F32 HDA_SDIN3 SATA2TXP AF6
C C
1 2 SERIRQ AH3
R237 HDA_SDOUT_PCH SATA3RXN
40 HDA_SDOUT_AUDIO 1 2 B29 HDA_SDO SATA3RXP AH1
10K_0402_5% R324 33_0402_5% AF3
SATA3TXN
If GPIO33 pull down, ME will not working. SATA3TXP AF1
GPIO33 can not pull down PCH_GPIO33# H32
For factory update ME, pull down resistor pull
SATA
HDA_DOCK_EN# / GPIO33
(manufacturing environments) SATA4RXN AD9
under door.
PCH_GPIO33#
J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 GPIO21
SATA4TXN AD6
AD5
Project ID PCH_GPIO21
SATA4TXP
D
1
PCH_JTAG_TCK
2
21 PCH_JTAG_TCK M3 JTAG_TCK SATA5RXN AD3
AD1
* NEW50/70/80/90 0
37 ME_OVERRIDE SATA5RXP
G Q39 21 PCH_JTAG_TMS K3 JTAG_TMS SATA5TXN AB3 NEW71/91 1
1
S AB1
3
JTAG
21 PCH_JTAG_TDO J2 JTAG_TDO SATAICOMPO AF16
2
SPI
1 2 33_0402_5% PCH_SPI_MISO AV1 SPI_MISO SATA1GP / GPIO19 V1 R260 1 SG@ 2 10K_0402_5%
unpop TDO,TDI,TMS resister
+1.05VS_PCH +3V
1
IBEXPEAK-M_FCBGA107
PCH_GPIO21 21
R259 R268
2008 Intel MOW36/MOW50 PCH_GPIO19 21
51_0402_5% 2 @ 1 R646 DISO@
200_0402_5% 2 1 R726 TDO: 10K_0402_5% 10K_0402_5%
100_0402_5% 2 1 R725 PCH_JTAG_TMS Reserved on ES1 Sample
2
Mount R724, R722 on ES2 Sample
51_0402_5% 2 @ 1 R644
200_0402_5% 2 1 R724
100_0402_5% 2 1 R722 PCH_JTAG_TDO MP mount R646, R644, +3VS
R645, R643 and remove U18
51_0402_5% 2 @ 1 R645 others PCH_SPI_CS0# 1 8
200_0402_5% 2 CS# VCC
1 R728 +3VS R301 1 2 3.3K_0402_5% SPI_W P1# 3 WP# SCLK 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 @ 1 2
100_0402_5% 2 1 R727 PCH_JTAG_TDI R271 1 2 3.3K_0402_5% SPI_HOLD1# 7 5 PCH_SPI_MOSI_1 C729 10P_0402_50V8J
HOLD# SI PCH_SPI_MISO_1
4 GND SO 2
51_0402_5% 2 @ 1 R643
20K_0402_5% 2 1 R721 MX25L3205DM2I-12G SOP 8P
10K_0402_5% 2 1 R723 PCH_JTAG_RST# SA000021A00
GPIO19 GPIO37
SPI ROM Footprint 200mil PCH_GPIO19 VGA_PRSNT_L#
dGPU 0 0
A
4.7K_0402_5% 2 1 R647 PCH_JTAG_TCK
iGPU 0 1 A
* SG 1 X
S3 CRB 1.1 Change to 4.7K
+3VS
U41B
1. Connect Directly
REV1.0 EXPRESS CARD, MINI1, MINI2
PCIE_DTX_C_PRX_N1 BG30 B9 EC_LID_OUT# 2. Level Shift1, Pull-Up to +3VS
33 PCIE_DTX_C_PRX_N1 PERN1 SMBALERT# / GPIO11 EC_LID_OUT# 37
PCIE_DTX_C_PRX_P1 BJ30
33 PCIE_DTX_C_PRX_P1 PERP1 CLOCK GEN, DIMM1, DIMM2
For PCIE LAN 33 PCIE_PTX_C_DRX_N1 C335 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 H14 PCH_SMBCLK PCH_SMBCLK 12,21,35
C339 0.1U_0402_16V7K PCIE_PTX_DRX_P1 PETN1 SMBCLK
33 PCIE_PTX_C_DRX_P1 2 1 BH29 PETP1 PCH_SMBDATA
3. Level Shift2, Pull-Up to +3VS
SMBDATA C8 PCH_SMBDATA 12,21,35
35 PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_N2 AW30 LAN
PCIE_DTX_C_PRX_P2 BA30 PERN2
35 PCIE_DTX_C_PRX_P2
C332 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 PERP2 PCH_GPIO60
4. Level Shift3, Pull-Up to +3VS
For Wireless LAN 35 PCIE_PTX_C_DRX_N2
C334 2
1
0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PETN2 SML0ALERT# / GPIO60 J14
CPU & PCH XDP
35 PCIE_PTX_C_DRX_P2 1 PETP2
D
SML0CLK C6 D
AU30
SMBus
PERN3
AT30 PERP3 SML0DATA G8
AU32 PETN3
AV32 PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 PCH_SML1CLK
PERP4 SML1CLK / GPIO58
BD32 PETN4 DGPU_PW R_EN 18,21,39,43
BE32 G12 PCH_SML1DAT +3V
PETP4 SML1DATA / GPIO75
PCI-E*
1
BF33 PERN5
1
2009/08/25: remove PCIE5 R275 +3VSDGPU
For Mini2 BH33 PERP5 CL_CLK1 T13
Controller
BG32 R636 SG@
PETN5 UMA@ 10K_0402_5%
BJ32 PETP5 CL_DATA1 T11
1
10K_0402_5%
Link
2
BA34 T9 R277
2
PERN6 CL_RST1# @
AW34 PERP6
2
10K_0402_5%
G
BC34 PETN6
BD34
2
PETP6 PEG_CLKREQ#_R
PEG_A_CLKRQ# / GPIO47 H1 1 3 PEG_CLKREQ# 23
AT34
S
PERN7
1
2/10 PCIE7, PCIE8 not support on HM55 AU34 Q18
PERP7 R247 SG@ R276
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PEG_VGA# 22
AV36 AD45 CLK_PEG_VGA 22 DISO@ SG@
PETP7 CLKOUT_PEG_A_P 2.2K_0402_5% 2.2K_0402_5%
BG34 AN4 CLK_CPU_DMI# 5
2
PERN8 CLKOUT_DMI_N
PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI 5
BG36 PETN8
C BJ36 2N7002E-T1-GE3_SOT23-3 C
PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
33 CLK_PCIE_LAN# AK48 CLKOUT_PCIE0N
For PCIE LAN 33 CLK_PCIE_LAN AK47 CLKOUT_PCIE0P
1
B B
R241 MINI2_CLKREQ#_1 M9 AF38 XCLK_RCOMP R170 1 2 90.9_0402_1% +1.05VS_PCH R564 Y2
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20PF_7A25000012
10K_0402_5% Project Structure ID UMA@ UMA@
2
AJ50 T45 +3VS Change to 5x3.2
2
2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P 1 2
MINI2_CLKREQ#_1 R156 1 2 10K_0402_5%
PCH_GPIO44 H6 P43 PROJECT_ID1 C694
Clock Flex
2
+3VS IBEXPEAK-M_FCBGA107
1222 GPIO66 Project Structure PCH_SML1CLK 6 1 EC_SMB_CK2
MINI1_CLKREQ# R265 1
PULL HIGH:8L EC_SMB_CK2 23,37
2 10K_0402_5% GPIO21 GPIO65 GPIO66
PCH_GPIO20 R649 1 2 10K_0402_5% PULL DOWN:6L Q19A
+3V Structure
ID2 ID1 ID0 DMN66D0LDW -7_SOT363-6
+3VS
EC_LID_OUT# R623 1
0 0 0 DVT Pull high +3VS at KB926 side
2 10K_0402_5%
PCH_SMBCLK R602 1 2 2.2K_0402_5% 0 0 1
5
PCH_SMBDATA R626 1 2 2.2K_0402_5%
DMI_HTX_PRX_N[0..3]
4 DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
4 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
4 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
4 DMI_PTX_HRX_P[0..3]
H_FDI_TXN[0..7]
4 H_FDI_TXN[0..7]
D U41C D
H_FDI_TXP[0..7] H_FDI_TXN0
4 H_FDI_TXP[0..7]
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 H_FDI_TXN1
DMI_HTX_PRX_N1 BJ22 DMI0RXN FDI_RXN1 H_FDI_TXN2
DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
DMI_HTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 H_FDI_TXN4
DMI3RXN FDI_RXN4 BA16
+3VS BE14 H_FDI_TXN5
DMI_HTX_PRX_P0 FDI_RXN5 H_FDI_TXN6
BD24 DMI0RXP FDI_RXN6 BA14
DMI_HTX_PRX_P1 BG22 BC12 H_FDI_TXN7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 H_FDI_TXP0
R657 8.2K_0402_5% DMI3RXP FDI_RXP0 H_FDI_TXP1
FDI_RXP1 BF17
DMI_PTX_HRX_N0 BE22 BC16 H_FDI_TXP2
DMI_PTX_HRX_N1 DMI0TXN FDI_RXP2 H_FDI_TXP3
BF21 DMI1TXN FDI_RXP3 BG16
DMI_PTX_HRX_N2 BD20 AW16 H_FDI_TXP4
DMI_PTX_HRX_N3 DMI2TXN FDI_RXP4 H_FDI_TXP5
BE18 DMI3TXN FDI_RXP5 BD14
BB14 H_FDI_TXP6
DMI_PTX_HRX_P0 FDI_RXP6 H_FDI_TXP7
BD22 DMI0TXP FDI_RXP7 BD12
DMI_PTX_HRX_P1 BH21
+3V DMI_PTX_HRX_P2 DMI1TXP
BC20 DMI2TXP
DMI_PTX_HRX_P3 BD18 BJ14 H_FDI_INT 4
+1.05VS_PCH DMI3TXP FDI_INT
DMI
FDI
1 2 SUS_PW R_DN_ACK BF13 H_FDI_FSYNC0 4
R648 10K_0402_5% R600 FDI_FSYNC0
BH25 DMI_ZCOMP
1 2 PCH_GPIO72 49.9_0402_1% BH13 H_FDI_FSYNC1 4
R628 8.2K_0402_5% DMI_COMP FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
1 2 EC_SW I# BJ12 H_FDI_LSYNC0 4
R198 10K_0402_5% FDI_LSYNC0
1 2 PCH_PCIE_W AKE# 09/09/14 WW37 PCH WAKE# PU 10K BG14 H_FDI_LSYNC1 4
C R641 10K_0402_5% FDI_LSYNC1 C
1 @ 2 PM_SLP_LAN#
R248 10K_0402_5%
K5 P8 PCH_GPIO61 @ PAD
MEPWROK SUS_STAT# / GPIO61 T10
C
EC_RSMRST# 37
CH751H-40PT_SOD323-2
E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
B
2
R604 1 2 +3V
EC_SW I# F14 F6 PM_SLP_LAN# 10K_0402_5% R598 4.7K_0402_5%
37 EC_SW I# RI# SLP_LAN# / GPIO29
D20A
2
IBEXPEAK-M_FCBGA107 1
6
2
+3VS BAV99DW -7_SOT363
D20B
5
U44 4
2 EC_PW ROK 3
P
1
1 VGATE
A VGATE 12,54
G
2
A A
SYS_PW ROK 1 2
R606 10K_0402_5%
EC_PW ROK 1
R632
2
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
LAN_RST# 1
R617
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, FDI, PM
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 15 of 59
5 4 3 2 1
5 4 3 2 1
U41D
IGPU_BKLT_EN T48 BJ46
L_BKLTEN SDVO_TVCLKINN
29 PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46
LVDS
PCH_TXCLK- AV53
29 PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C313 2 1 UMAHD@ 0.1U_0402_16V7K PCH_TMDS_D2# 31
+3VS 29 PCH_TXCLK+ LVDSA_CLK DDPB_0N
BC42 PCH_DPB_P0 C305 2 1 UMAHD@ 0.1U_0402_16V7K PCH_TMDS_D2 31 HDMI D2
PCH_TXOUT0- DDPB_0P PCH_DPB_N1 C320 UMAHD@ 0.1U_0402_16V7K
11/21 intel JIM suggest Pull high at LVDS Conn 29 PCH_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42 2 1 PCH_TMDS_D1# 31
PCH_TXOUT1- BA52 BG42 PCH_DPB_P1 C323 2 1 UMAHD@ 0.1U_0402_16V7K PCH_TMDS_D1 31 HDMI D1
DDPD_0N BJ40
30 PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
30 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38
CRT
DDPD_2N BF37
CRT_IREF AD48 BH37
B ENBKL R135 1 UMAO@ 2 0_0402_5% IGPU_BKLT_EN DAC_IREF DDPD_2P B
AB51 CRT_IRTN DDPD_3N BE36
UMA Only
REV1.0 DDPD_3P BD36
1
IBEXPEAK-M_FCBGA107
R134
1
100K_0402_5%
R143
1K_0402_0.5%
2
SN74CBTD3306CPW R_TSSOP8
SG@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS, CRT, DPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 16 of 59
5 4 3 2 1
5 4 3 2 1
U41E
+3VS +3VS
H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
AD1 NV_CE#1 MC74VHC1G08DFT2G_SC70-5
C44 AD2 NV_CE#2 AP15
5
R160 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8 U42
R588 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3 PLT_RST#
1 2 C36 2
P
R585 8.2K_0402_5% PCI_PIRQC# AD4 B
1 2 J34 AD5 NV_DQS0 AV9 Y 4 PLT_RST_BUF# 35
R158 1 2 8.2K_0402_5% PCI_SERR# A40 BG8 1 1
AD6 NV_DQS1 A
1
D45 C443
AD7 @ R621
E36 AP7
3
AD8 NV_DQ0 / NV_IO0 0.1U_0402_16V7K 100K_0402_5%
H48 AD9 NV_DQ1 / NV_IO1 AP6
2
E40 AD10 NV_DQ2 / NV_IO2 AT6
D C40 AT9 D
2
R554 8.2K_0402_5% PCI_PLOCK# AD11 NV_DQ3 / NV_IO3 +3VS
1 2 M48 AD12 NV_DQ4 / NV_IO4 BB1
R555 1 2 8.2K_0402_5% PCI_PERR# M45 AV6
R581 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5 R742
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3
5
R579 1 2 8.2K_0402_5% PCI_STOP# M40 BA4 0_0402_5% U43
AD15 NV_DQ7 / NV_IO7 R741 @
NVRAM
M43 BE4 1 2 2
P
AD16 NV_DQ8 / NV_IO8 0_0402_5% B R619 1 DIS@
J36 AD17 NV_DQ9 / NV_IO9 BB6 Y 4 2 PLTRST_VGA# 22
K48 AD18 NV_DQ10 / NV_IO10 BD6 18,21 DGPU_HOLD_RST# 1 DIS@ 2 1 A
100_0402_5%
1
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 BC8 MC74VHC1G08DFT2G_SC70-5 R622
3
R556 8.2K_0402_5% PCI_REQ0# AD20 NV_DQ12 / NV_IO12 DIS@ 100K_0402_5%
1 2 K46 AD21 NV_DQ13 / NV_IO13 BJ8
R557 1 2 8.2K_0402_5% PCI_PIRQB# M51 BJ6 DIS@
R559 8.2K_0402_5% PCI_PIRQF# AD22 NV_DQ14 / NV_IO14
1 2 J52 BG6
2
R560 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15
1 2 K51 AD24
L34 BD3 NV_ALE NV_ALE,NV_CLE
AD25 NV_ALE NV_CLE
F42 AY6
J40
AD26 NV_CLE has a weak internal pull-down
AD27
G46 AD28
R577 1 2 8.2K_0402_5% PCI_IRDY# F44 AU2 NV_RCOMP R660 1 @ 2 32.4_0402_1% +1.8VS
R574 8.2K_0402_5% PCI_PIRQD# AD29 NV_RCOMP
1 2 M47 AD30
PCI
R572 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
R153 8.2K_0402_5% PCI_DEVSEL# AD31 NV_RB# NV_ALE R233 1 @
1 2 2 1K_0402_5%
J50 C/BE0# NV_WR#0_RE# AY8
G42 C/BE1# NV_WR#1_RE# AY5
H47 NV_CLE R225 1 @ 2 1K_0402_5%
C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
R568 1 2 8.2K_0402_5% PCI_FRAME# BF5
R570 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# NV_WE#_CK1 Intel Anti-Theft Techonlogy
1 2 G38 PIRQA#
R565 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# H51 PIRQB#
C R566 1 2 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# B37 PIRQC# USBP0N H18 USB20_N0
USB20_N0 36 High=Endabled C
PCI_PIRQD# A44 PIRQD# USBP0P J18 USB20_P0
USB20_P0 36 USB/B (Right Side) NV_ALE
PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# USB20_N1 Low=Disable(floating)
has a weak internal pull-up
PCI_REQ0# F51 REQ0#
USBP1N
USBP1P
A18
C18 USB20_P1
USB20_N1
USB20_P1
36
36 USB Port (Left Side) *
PCI_REQ1# A46 N20 USB20_N2
REQ1# / GPIO50 USBP2N USB20_N2 36
16,29,30 DGPU_SELECT#
DGPU_SELECT# B45 REQ2# / GPIO52 USBP2P P20 USB20_P2
USB20_P2 36 USB/B (Right Side) DMI Termination Voltage
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N
USBP3P L20 EHCI 1 Set to Vcc when HIGH
PCI_GNT0# F48 GNT0# USBP4N F20 NV_CLE
PCI_GNT1# K45 GNT1# / GPIO51 USBP4P G20 Set to Vss when LOW
DGPU_PW MSEL# F36 A20
29 DGPU_PW MSEL# GNT2# / GPIO53 USBP5N
PCI_GNT3# H53 C20
GNT3# / GPIO55 USBP5P
PCI_GNT2# ESI Strap (Server Only) USBP6N M22
PCI_PIRQE# B41 N22 2/10 USB6, USB7 not NV_ALE
:
this signal should not be pulled low PCI_PIRQF# K53
PIRQE# / GPIO2 USBP6P
B21 Enable Intel Anti-Theft
PCI_PIRQG# PIRQF# / GPIO3 USBP7N support on HM55
A36 PIRQG# / GPIO4 USBP7P D21 Technology 8.2K PU to +3VS
PCI_PIRQH# A48 H22 USB20_N8
:
PIRQH# / GPIO5 USBP8N USB20_N8 29
J22 USB20_P8
USB20_P8 29 CMOS Camera (LVDS) Disable Intel Anti-Theft
USBP8P
USB
@ TP_PCI_RST# K6 E22 USB20_N9 Technology floating(internal PD)
T12 PAD PCIRST# USBP9N USB20_N9 36
F22 USB20_P9 Card Reader
USBP9P USB20_P9 36
PCI_SERR# E44 A22 USB20_N10
USB20_N10 35
NV_CLE
PCI_PERR# SERR# USBP10N USB20_P10
E50 PERR# USBP10P C22 USB20_P10 35 Mini Card(SIM Card)
USBP11N G24 USB20_N11
USB20_N11 36
DMI termination voltage.
H24 USB20_P11 Bluetooth EHCI 2 weak internal PU, don't PD
USBP11P USB20_P11 36
PCI_IRDY# A42 L24 USB20_N12
IRDY# USBP12N USB20_N12 35
H44 M24 USB20_P12 Mini Card(WLAN)
PAR USBP12P USB20_P12 35
PCI_DEVSEL# F46 A24 USB20_N13
DEVSEL# USBP13N USB20_N13 35
PCI_FRAME# C46 C24 USB20_P13 Mini Card(WWAN)
FRAME# USBP13P USB20_P13 35
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R191
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1% USB_OC#0_R
TRDY# USBRBIAS USB_OC#0_R 21
M7 USB_OC#2_R
PME# USB_OC#2_R 21
N16 USB_OC#0_R R216 1 2 0_0402_5% (For USB Port0, 2)
OC0# / GPIO59 USB_OC#0 36
PLT_RST# D5 J16 USB_OC#1_R
5,21,33,37 PLT_RST# PLTRST# OC1# / GPIO40 USB_OC#1_R 21
F16 USB_OC#2_R R210 1 2 0_0402_5% (For USB Port1)
OC2# / GPIO41 USB_OC#2 36
N52 L16 USB_OC#3_R
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#3_R 21
2008/1/6 2009MOW01 change to 22 ohm P53 E14 USB_OC#4_R
CLKOUT_PCI1 OC4# / GPIO43 USB_OC#4_R 21
P46 G16 USB_OC#5_R
CLKOUT_PCI2 OC5# / GPIO9 USB_OC#5_R 21
37 CLK_PCI_LPC R561 1 2 22_0402_5% CLK_PCI_LPC_R P51 F12 USB_OC#6_R RP1
CLKOUT_PCI3 OC6# / GPIO10 USB_OC#6_R 21
R142 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R USB_OC#3_R 1 8 +3V
14 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 USB_OC#7_R 21
USB_OC#5_R 2 7
USB_OC#6_R 3 6
IBEXPEAK-M_FCBGA107 USB_OC#7_R 4 5
OC[0..3] use for EHCI 1
Boot BIOS Strap 10K_1206_8P4R_5%
OC[4..7] use for EHCI 2
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location
0 0 LPC PCI_GNT0# R137 1 @ 2 1K_0402_5%
Have internal PU USB_OC#1_R R601 1 2 10K_0402_5%
0 1 Reserved (NAND)
PCI_GNT1# R159 1 @ 2 1K_0402_5% USB_OC#4_R R603 1 2 10K_0402_5%
1 0 PCI Have internal PU
1 1 SPI PCI_GNT3# R558 1 @ 2 1K_0402_5%
A * Have internal PU
A
+3VS +3VS
MISC
R651 1 2 10K_0402_5% PCH_GPIO39 EC_SCI# J32 AF47
37 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
DGPU_PWR_EN Pull Low at Page 43 EC_SMI# F10
37 EC_SMI# GPIO8
R264 1 @ 2 10K_0402_5% DGPU_PW R_EN
PCH_GPIO12 K9
(GPIO8 Have Internal Pull High,Should not be Pull-Low) U2 EC_GA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE EC_GA20 37
(GPIO15 Have Internal Pull Down) PCH_GPIO15 T7 GPIO15
R236 1 2 10K_0402_5% PCH_GPIO48
R658 1 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3
R155 1 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
2 10K_0402_5% VGA_PW ROK
R161 1 2 DGPU_PW ROK_1 F38 AM1
51 VGA_PW ROK TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 5
0_0402_5%
R243 1 2 10K_0402_5% PCH_GPIO34 PCH_GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI 5
GPIO
R178 1 2 10K_0402_5% EC_SCI#
2009/09/07 GPIO24 pull high +3V PCH_GPIO24 H10 T1 EC_KBRST#
GPIO24 RCIN# EC_KBRST# 37
+3V (GPIO27 Have Internal Pull High) PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPW RGD 5
CPU
R245 1 2 10K_0402_5% PCH_GPIO12 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
21 PCH_GPIO28 GPIO28 THRMTRIP# H_THERMTRIP# 5
R246 1 2 10K_0402_5% EC_SMI# R221 56_0402_5%
PCH_GPIO34 M11 2 1 +1.05VS_PCH
R239 1 STP_PCI# / GPIO34
2 1K_0402_5% PCH_GPIO15 R220 56_0402_5%
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO35 V6 2009/08/23
R242 1 @ SATACLKREQ# / GPIO35
2 10K_0402_5% PCH_GPIO24 Series resistor of 56±5%
14,21,39,43 DGPU_PW R_EN DGPU_PW R_EN AB7 BA22
R642 10K_0402_5% PCH_GPIO28 SATA2GP / GPIO36 TP1 Pull-up of 56±5% to VTT
1 2
R640 1 2 10K_0402_5% PCH_GPIO57
21 VGA_PRSNT_L#
VGA_PRSNT_L# AB13 AW22 (both these should be close to PCH)
R633 10K_0402_5% PCH_GPIO45 SATA3GP / GPIO37 TP2
1 2
C R630 1 2 10K_0402_5% RST_GATE VGA_PRSNT_R# V3 BB22 C
SLOAD / GPIO38 TP3
PCH_GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
R262 1 DIS@ 2 10K_0402_5% VGA_PRSNT_L# PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 MAINPW ON 45,46,48
R659 1 2 10K_0402_5% DGPU_HOLD_RST# 10 RST_GATE RST_GATE F1 AV43
PCIECLKRQ7# / GPIO46 TP6 R224
1
PCH_GPIO48 AB6 AV45 @ 330_0402_5% C
R154 1 @ SDATAOUT1 / GPIO48 TP7
2 10K_0402_5% DGPU_PW ROK_1 +1.05VS_PCH 1 2 2 Q14
PCH_TEMP_ALERT# AA4 AF13 B 2SC2411K_SOT23-3
21,37 PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
R229 1 2 10K_0402_5% PCH_GPIO35 E
@
3
PCH_GPIO57 F8 M18
R263 1 @ GPIO57 TP9
2 10K_0402_5% PCH_GPIO27
GPIO27 (Have internal Pull-High) N18 H_THERMTRIP#
TP10
High: VCCVRM VR Enable A4 AJ24
VSS_NCTF_1 TP11
Low: VCCVRM VR Disable GPIO19 GPIO37 A49
NCTF
VSS_NCTF_2
RSVD
A5 VSS_NCTF_3 TP12 AK41
+3VS PCH_GPIO19 VGA_PRSNT_L# A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
dGPU 0 0 A53 VSS_NCTF_6
2
B B
BF53 VSS_NCTF_14
2 Q20 BH1 H12
30 CRT_DET# VSS_NCTF_15 TP18
G @ BH2
2N7002E-T1-GE3_SOT23-3 VSS_NCTF_16
S BH52 AA23
3
VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
GPIO8 BJ4 AB38
VSS_NCTF_21 NC_2
This signal has a weak internal pull up BJ49 VSS_NCTF_22
can't Pull low BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
GPIO27 BJ53 VSS_NCTF_26
On-Die PLL Voltage Regulator D1 VSS_NCTF_27 NC_5 T39
This signal has a weak internal pull up D2 INIT3_3V
::On-Die
VSS_NCTF_28
D53 VSS_NCTF_29 2009/08/23
H voltage regulator enable This signal has weak internal
* L On-Die PLL Voltage Regulator disable
E1
E53
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V# P6 (Have internal PH,Do not pull down)
PH, can't pull low
TP24_SST @
REV1.0 TP24 C10 PAD T21
Note: the internal pull-up is disabled IBEXPEAK-M_FCBGA107
after RSMRST# de-asserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the
On-Die PLL Voltage Regulator is disabled.
:
A A
GPIO15
L Intel ME Crypto Transport
* Layer Security(TLS) chiper suite
:
with no confidentiality
H Intel ME Crypto Transport
Layer Security(TLS) chiper suite
Security Classification Compal Secret Data Compal Electronics, Inc.
with confidentiality Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
CRB has a 1-k pull-up on this signal AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
to +3.3VA rail. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 18 of 59
5 4 3 2 1
5 4 3 2 1
Need Modify
180 ohm @
100MHz Bead
+1.05VS_VTT
+1.05VS_PCH +3VS
60mA
J1
10U_0805_10V4Z 1U_0402_6.3V4Z
U41G POWER +VCCADAC
15mil 0.01U_0402_16V7K
2 2 1 1 AB24 VCCCORE[1] VCCADAC[1] AE50 1 2
1 1 AB26 1 1 1 L19
VCCCORE[2]
1
D @ JUMP_43X118 AB28 69mA AE52 C296 C298 MBK1608221YZF_2P D
C718 C344 VCCCORE[3] VCCADAC[2] R136 C291
AD26 VCCCORE[4]1524mA 220 ohm bead,350mA
CRT
AD28 AF53 0_0402_5% 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 VCCCORE[5] VSSA_DAC[1] @ 2 2 2
AF26 VCCCORE[6]
VCC CORE
Short J4 for PCH VCCCORE AF28 AF51 Near AE50
2
VCCCORE[7] VSSA_DAC[2] +3VS
Near AB24 Near AB24 AF30 VCCCORE[8] CRB 0.9 is 180 ohm @ 100MHz
AF31 VCCCORE[9] DG0.8 is 600 ohm FB (Page 290)
Top Side AH26 20mil
VCCCORE[10] +VCCA_LVDS R138 1 UMA@ 2 0_0805_5%
AH28 VCCCORE[11]
AH30 VCCCORE[12] 300mA
1
Intel suggest follow CRB 8/21 AH31 VCCCORE[13] VCCALVDS AH38
AJ30 R172
VCCCORE[14] 0_0402_5%
AJ31 VCCCORE[15] VSSA_LVDS AH39
All Ibex Peak-M Power rails with netnames +1.1VS and DISO@
59mA
2
+1.1V rails are actually +1.05VS and +1.05V rails +1.05VS_PCH AP43 +1.8VS
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45 15mil L20 UMA@
AT46 Near AP43
LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C300
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C316 1 1 UMA@ 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
10mil @ +VCCAPLL_EXP BJ24 C304
T20 PAD VCCAPLLEXP
AB34 UMA@ 0.01U_0402_16V7K 1 DISO@ 2
VCC3_3[2] 2 UMA@ 2 2 R145
DG 1.6 (Page 329)
Have Internal VRM AN20 AB35 0_0402_5%
VCCIO[25] VCC3_3[3]
AN22
HVCMOS
VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C331 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 0.1U_0402_16V4Z Near AB34
VCCIO[32] 2
AT26 VCCIO[33]
AT28 R186 1 @ 2 0_0805_5% +1.05VS_PCH
VCCIO[34]
AU26 VCCIO[35]
+1.05VS_PCH +VCCVRM
AU28 VCCIO[36] 40mil
AV26 VCCIO[37] 35mA R192 1
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 2 0_0805_5% +1.8VS
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.05VS_PCH
DMI
C719 C321 C342 C345 C348
BA26 VCCIO[41] VCCDMI[1] AT16 10mil
BA28 VCCIO[42]
BB26 AU16 +VCC_DMI R204 1 2 0_0805_5%
2 2 2 2 2 VCCIO[43] VCCDMI[2]
BB28 VCCIO[44] 1
Top Side BC26 VCCIO[45]
PCI E*
1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C368
VCCIO[46] 1U_0402_6.3V4Z
BD26 VCCIO[47] 2
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
BH27 VCCIO[53] VCCPNAND[5] AK15
AK13 +1.8VS
+3VS VCCPNAND[6]
Follow Intel suggestion 8/21 AN30 VCCIO[54] VCCPNAND[7] AM12
Near AN35
NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
VCCPNAND[9] AM15
0.1U_0402_16V4Z 1
B C329 2 C372 B
1 AN35 VCC3_3[1]
0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
@ +VCCAPLL_FDI
85mA Near AK13
10mil DG 1.6 (Page 329) T9 PAD BJ18 VCCFDIPLL 6mA VCCME3_3[1] AM8
Have Internal VRM AM9 +3VS
VCCME3_3[2]
FDI
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 19 of 59
5 4 3 2 1
5 4 3 2 1
U41J POWER
@ +1.1VS_VCCACLK
10mil
AP51
52mA REV1.0 V24
T17 PAD VCCACLK[1] VCCIO[5] +1.05VS_PCH
VCCIO[6] V26 1 09/09/14 WW37 remove
DG 1.6 (Page 329) AP53 Y24 +1.05VS_PCH +VCCADPLLA
VCCACLK[2] VCCIO[7] C340
+VCCADPLLA,+VCCADPLLB external 1U
Have Internal VRM VCCIO[8] Y26
344mA 1U_0402_6.3V4Z
+1.05VS_PCH 2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3V L60
Near BB51
R187 1 @
15mil +VCCLAN VCCSUS3_3[2] U28 Near V24 1 2
10UH_LB2012T100MR_20%
2 AF24 VCCLAN[2] VCCSUS3_3[3] U26
0_0603_5% 1 U24 10uH inductor, 120mA 1 1
VCCSUS3_3[4]
1
P28 1 1 R562
VCCSUS3_3[5]
1
R199 C352 +PCH_VCCD6W C350 C347 + C691 0_0402_5%
D
0_0402_5% 1U_0402_6.3V4Z
10mil Y20 DCPSUSBYP VCCSUS3_3[6] P26
C688 @ @
D
1 VCCSUS3_3[7] N28
@ 2 C367 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
1998mA VCCSUS3_3[8] N26
2 2 2 1U_0402_6.3V4Z
Near AF23 AD38 M28
2
0.1U_0402_16V4Z VCCME[1] VCCSUS3_3[9]
M26 Near A26 Near U23
2
2 VCCSUS3_3[10] +VCCADPLLB
AD39 L28
USB
VCCME[2] VCCSUS3_3[11]
Near Y20 VCCSUS3_3[12] L26
DG2.0 Table162 Note2 (C295 unpop) AD41 VCCME[3] VCCSUS3_3[13] J28
J26 L61 1 2
+1.05VS_PCH VCCSUS3_3[14] 10UH_LB2012T100MR_20%
Follow Intel suggestion AF43 VCCME[4] VCCSUS3_3[15] H28
VCCSUS3_3[16] H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M AF41 163mA G28 C692
VCCME[5] VCCSUS3_3[17] + 1U_0402_6.3V4Z
1 1 1 1 1 VCCSUS3_3[18] G26
@ AF42 F28 C689 @
C293 C294 C341 C295 C324 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26
22U_0805_6.3V6M 1U_0402_6.3V4Z +3V 2
2 2 2 2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
E26
2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 C26 CH751H-40PT_SOD323-2
VCCSUS3_3[24]
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
+1.05VS_PCH
All Ibex Peak-M Power rails with netnames +1.1VS and
1
Y41 U23 2/12 Follow EDS1.11 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28]
Change to 100 ohm +5V
Y42 VCCME[12] VCCIO[56] V23 10mil
2
10mil R189 D4
Near V9 C390 10mil >1mA F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z V5REF_SUS
C 1 2 +VCCRTCEXT V9 2 1 C349 2/12 Follow EDS1.11 C
DCPRTC 1U_0402_6.3V6K R141
10mil Change to 100 ohm
1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 VCCVRM[3] Change to 1U for power
PCI/GPIO/LPC
357mA 2 1 C299
sequence issue on ICH9 1U_0402_6.3V6K
20mil 72mA VCC3_3[8] J38
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
20mil 73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS_PCH BD53 N36
VCCADPLLB[2] VCC3_3[11]
Near AH23 C337
1
AH23 VCCIO[21] VCC3_3[12] P36 Near J38
AJ35 VCCIO[22]
1 1 Near AF32 AH35 U35 0.1U_0402_16V4Z
C351 VCCIO[23] VCC3_3[13] 2 +3VS
C330 1 2 +PCH_VCCIO AF34
1U_0402_6.3V4Z 1U_0402_6.3V4Z R139 0_0603_5% VCCIO[2]
2 2 VCC3_3[14] AD13 Near AD13
2 1 AH34 VCCIO[3]
Near AH35 C336 1 2 C376
1U_0402_6.3V4Z AF32 32mA 10mil 0.1U_0402_16V4Z
VCCIO[4]
VCCSATAPLL[1] AK3
10mil 1 2 +VCCSST V12 AK1 +VCCSATAPLL @ PAD T23
C375 DCPSST VCCSATAPLL[2]
0.1U_0402_16V4Z
Near V12
DG 1.6 (Page 329)
+1.05VS_PCH Have Internal VRM
10mil 1 2 +VCCSUS Y22
B C353 DCPSUS B
+3V 0.1U_0402_16V4Z
Near Y22 VCCIO[9] AH22
VCCSUS3_3[30] +1.05VS_PCH
PCI/GPIO/LPC
VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32] +5VALW
VCCIO[12] AF22 1
+3VS
AD19 C371
VCCIO[13] 1U_0402_6.3V4Z R176
V15 VCC3_3[5] VCCIO[14] AF20
1
2 0_0402_5% S Q8
1 VCCIO[15] AF19
C370 V16 AH20 Near AB19 43 SBPW R_EN# 2 @ 1 2 R169
VCC3_3[6] VCCIO[16] G @ 0_0402_5%
0.1U_0402_16V4Z Y16 AB19 1 D
1
2 VCC3_3[7] VCCIO[17] C343 AO3413L_SOT23-3
AB20
2
+1.05VS_PCH VCCIO[18] +1.05VS_PCH @
Near V15 VCCIO[19] AB22
0.1U_0402_16V4Z
> 1mA VCCIO[20] AD22 15mil 2
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R179 1 2 0_0603_5% +5V
CPU
C357 1 2 1U_0402_6.3V4Z
20mil IBEXPEAK-M_FCBGA107
+RTCVCC Near L30
1 1 1
C386 C377
C373 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/08/01 2010/08/01 Title
1U_0402_6.3V4Z 2 2 2 Issued Date Deciphered Date
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 20 of 59
5 4 3 2 1
5 4 3 2 1
U41I U41H
AY7
B11
VSS[159] VSS[259] H49
H5
AB16 VSS[0] PCH XDP Port
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 K47 AM19 AK34 R314 1 @ 2 33_0402_5% XDP_FN0
VSS[164] VSS[264] VSS[4] VSS[83] 17 USB_OC#0_R
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 L14 AA26 AK38 R311 1 @ 2 33_0402_5% XDP_FN2
VSS[166] VSS[266] VSS[6] VSS[85] 17 USB_OC#2_R
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 L2 AA30 AK46 R306 1 @ 2 33_0402_5% XDP_FN4
VSS[168] VSS[268] VSS[8] VSS[87] 17 USB_OC#4_R
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 L40 AB15 AL2 R312 1 @ 2 33_0402_5% XDP_FN8
VSS[172] VSS[272] VSS[12] VSS[91] 14 PCH_GPIO20
BB20 L52 AB23 AL52 R310 1 @ 2 33_0402_5% XDP_FN9
VSS[173] VSS[273] VSS[13] VSS[92] 14 PCH_GPIO18
BB24 M12 AB30 AM11 R309 1 @ 2 33_0402_5% XDP_FN10
VSS[174] VSS[274] VSS[14] VSS[93] 13 PCH_GPIO21
BB30 M16 AB31 BB44 R307 1 @ 2 33_0402_5% XDP_FN11
VSS[175] VSS[275] VSS[15] VSS[94] 13 PCH_GPIO19
BB34 M20 AB32 AD24 R305 1 @ 2 33_0402_5% XDP_FN12
VSS[176] VSS[276] VSS[16] VSS[95] 14,18,39,43 DGPU_PW R_EN
BB38 N38 AB39 AM20 R304 1 @ 2 33_0402_5% XDP_FN13
VSS[177] VSS[277] VSS[17] VSS[96] 18 VGA_PRSNT_L#
BB42 M34 AB43 AM22 R300 1 @ 2 33_0402_5% XDP_FN14
VSS[178] VSS[278] VSS[18] VSS[97] 17,18 DGPU_HOLD_RST#
BB49 M38 AB47 AM24 R297 1 @ 2 33_0402_5% XDP_FN15
VSS[179] VSS[279] VSS[19] VSS[98] 18,37 PCH_TEMP_ALERT#
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 M46 AB8 AM28 R313 1 @ 2 33_0402_5% XDP_FN17
VSS[181] VSS[281] VSS[21] VSS[100] 18 CRT_DET
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 M8 AD11 AM31 R287 1 2 0_0402_5% PCH_JTAG_TCK_R
VSS[184] VSS[284] VSS[24] VSS[103] 13 PCH_JTAG_TCK
BC22 N24 AD12 AM32 R284 1 2 0_0402_5% PCH_JTAG_TMS_R
VSS[185] VSS[285] VSS[25] VSS[104] 13 PCH_JTAG_TMS
BC32 P11 AD16 AM34 R286 1 2 0_0402_5% PCH_JTAG_TDI_R
VSS[186] VSS[286] VSS[26] VSS[105] 13 PCH_JTAG_TDI
BC36 AD15 AD23 AM35 13 PCH_JTAG_TDO R293 1 2 PCH_JTAG_TDO_R
VSS[187] VSS[287] VSS[27] VSS[106] 0_0402_5%
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 P30 AD31 AM39 R289 1 @ 2 0_0402_5% PCH_JTAG_RST#_R
VSS[189] VSS[289] VSS[29] VSS[108] 13 PCH_JTAG_RST#
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 P47 AD46 AM49 JP3
VSS[194] VSS[294] VSS[34] VSS[113]
BE12 R2 AD49 AM7 1 2 (XDP_FN16)
VSS[195] VSS[295] VSS[35] VSS[114] GND0 GND1
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50 3 OBSFN_A0 OBSFN_C0 4 PCH_GPIO28 18
BE20 T12 AE2 BB10 5 6 XDP_FN17
VSS[197] VSS[297] VSS[37] VSS[116] OBSFN_A1 OBSFN_C1
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32 7 GND2 GND3 8
C BE30 T46 AF12 AN50 XDP_FN0 9 10 XDP_FN8 C
VSS[199] VSS[299] VSS[39] VSS[118] (XDP_FN1) 17 USB_OC#1_R OBSDATA_A0 OBSDATA_C0 XDP_FN9
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52 11 OBSDATA_A1 OBSDATA_C1 12
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12 13 GND4 GND5 14
BE42 T8 AU4 AP42 XDP_FN2 15 16 XDP_FN10
VSS[202] VSS[302] VSS[42] VSS[121] (XDP_FN3) 17 USB_OC#3_R OBSDATA_A2 OBSDATA_C2 XDP_FN11
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46 17 OBSDATA_A3 OBSDATA_C3 18
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49 19 GND6 GND7 20
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5 21 OBSFN_B0 OBSFN_D0 22
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8 23 OBSFN_B1 OBSFN_D1 24
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2 25 GND8 GND9 26
BF3 V11 AF49 AR52 XDP_FN4 27 28 XDP_FN12
VSS[208] VSS[308] VSS[48] VSS[127] (XDP_FN5) 17 USB_OC#5_R OBSDATA_B0 OBSDATA_D0 XDP_FN13
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11 29 OBSDATA_B1 OBSDATA_D1 30
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12 31 GND10 GND11 32
BG18 V20 AG2 AH48 (XDP_FN6) 17 USB_OC#6_R 33 34 XDP_FN14
VSS[211] VSS[311] VSS[51] VSS[130] (XDP_FN7) 17 USB_OC#7_R OBSDATA_B2 OBSDATA_D2 XDP_FN15
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32 35 OBSDATA_B3 OBSDATA_D3 36
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36 37 GND12 GND13 38
BG50 V31 AH15 AT41 39 40 +3VS
VSS[214] VSS[314] VSS[54] VSS[133] 15 SYS_PW ROK PWRGOOD/HOOK0 ITPCLK/HOOK4
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47 5,15,37 PBTN_OUT# 1 2 41 HOOK1 ITPCLK#/HOOK5 42
BH15 V34 AH24 AT7 +3VS R296 0_0402_5% 43 44
VSS[216] VSS[316] VSS[56] VSS[135] VCC_OBS_AB VCC_OBS_CD
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12 45 HOOK2 RESET#/HOOK6 46 2 1 PLT_RST# 5,17,33,37
BH23 V38 AV18 AV16 47 48 R295 XDP_DBRESET# 5,15
VSS[218] VSS[318] VSS[58] VSS[137] HOOK3 DBR#/HOOK7 1K_0402_5%
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20 49 GND14 GND15 50
BH35 V45 AH47 AV24 51 52 PCH_JTAG_TDO_R
VSS[220] VSS[320] VSS[60] VSS[139] 5 SMB_DATA_S3 SDA TD0
BH39 V46 AH7 AV30 53 54 PCH_JTAG_RST#_R
VSS[221] VSS[321] VSS[61] VSS[140] 5 SMB_CLK_S3 SCL TRST#
BH43 V47 AJ19 AV34 55 56 PCH_JTAG_TDI_R
VSS[222] VSS[322] VSS[62] VSS[141] PCH_JTAG_TCK_R TCK1 TDI PCH_JTAG_TMS_R
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38 57 TCK0 TMS 58
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42 59 GND16 GND17 60
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 V8 AJ23 AV49 CONN@ SAMTE_BSH-030-01-L-D-A
VSS[226] VSS[326] VSS[66] VSS[145]
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 Y28 AM41 AW36 +3VS R294
VSS[234] VSS[334] VSS[74] VSS[153] @
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 Y31 AK26 AW52 4.7K_0402_5%
VSS[236] VSS[336] VSS[76] VSS[155]
2
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11 1 2 +3VS
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
SMB_DATA_S3
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47 12,14,35 PCH_SMBDATA 6 1
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107 Q21A
F5 VSS[241] VSS[341] P49
G10 Y5 DMN66D0LDW -7_SOT363-6
VSS[242] VSS[342] @
G14 VSS[243] VSS[343] Y6
G18 Y8 +3VS R290
VSS[244] VSS[344] @
G2 VSS[245] VSS[345] P24
G22 T43 4.7K_0402_5%
VSS[246] VSS[346]
5
G32 VSS[247] VSS[347] AD51 1 2 +3VS
G36 VSS[248] VSS[348] AT8
G40 AD47 12,14,35 PCH_SMBCLK 3 4 SMB_CLK_S3
VSS[249] VSS[349]
G44 VSS[250] VSS[350] Y47
G52 AT12 Q21B
VSS[251] VSS[351] DMN66D0LDW -7_SOT363-6
AF39 VSS[252] VSS[352] AM6
H16 AT13 @
VSS[253] VSS[353]
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS & PCH XDP Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Thursday, January 07, 2010 Sheet 21 of 59
5 4 3 2 1
5 4 3 2 1
4 PEG_GTX_HRX_N[0..15]
4 PEG_GTX_HRX_P[0..15]
4 PEG_HTX_C_GRX_N[0..15]
4 PEG_HTX_C_GRX_P[0..15]
1 VGA@ 2
10K_0402_5%
U34A
TXCLK_UP_DPF3P AK35
AL36
TXCLK_UN_DPF3N
TXOUT_U0P_DPF2P AJ38
AK37
TXOUT_U0N_DPF2N
PEG_HTX_C_GRX_P0 AA38 Y33 PEG_GTX_HRX_P0 AH35
PEG_HTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PEG_GTX_HRX_N0 TXOUT_U1P_DPF1P
Y37 PCIE_RX0N PCIE_TX0N Y32 TXOUT_U1N_DPF1N AJ36
AG38
PEG_HTX_C_GRX_P1 PEG_GTX_HRX_P1 TXOUT_U2P_DPF0P
Y35 W33 AH37
PEG_HTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PEG_GTX_HRX_N1 TXOUT_U2N_DPF0N
W36 PCIE_RX1N PCIE_TX1N W32
AF35
TXOUT_U3P
TXOUT_U3N AG36
PEG_HTX_C_GRX_P2 W38 U33 PEG_GTX_HRX_P2
PEG_HTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PEG_GTX_HRX_N2
V37 U32
PCIE_RX2N PCIE_TX2N LVTMDP
CLOCK
14 CLK_PEG_VGA AB35
PCIE_REFCLKP
14 CLK_PEG_VGA# AA36 PCIE_REFCLKN
CALIBRATION
For M96, AH16 is NC AJ21 Y30 R55 1 VGA@ 2 1.27K_0402_1%
NC#1 PCIE_CALRP
AK21
NC#2
2 VGA@ 1 AH16 Y29 R52 1 VGA@ 2 2K_0402_1% +1.0VSDGPU
R498 10K_0402_5% NC_PWRGOOD PCIE_CALRN
AA30 PERSTB
17 PLTRST_VGA#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M96_ PCIE / LVDS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 22 of 59
5 4 3 2 1
5 4 3 2 1
U34B
Strap Name Pin Straps description <all internal PD> Setting External VGA Thermal Sensor
VIP Device Strap Enable indicates to the software driver +3VSDGPU
VIP_DEVICE_EN V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset 0 TXCAP_DPA3P
AU24 VGA_HDMI_TXC+ 31
1: VHAD_0 to determine whether or not a VIP slave device TXCAM_DPA3N
AV23 VGA_HDMI_TXC- 31
1
0.1U_0402_16V4Z
C263
VGA Disable determines TX0P_DPA2P
AT25 VGA_HDMI_TXD0+ 31
VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24
DPA TX0M_DPA2N VGA_HDMI_TXD0- 31
1: The device will not be recognized as the system’s VGA controller VGA@
AU26 2
TX1P_DPA1P VGA_HDMI_TXD1+ 31
Transmitter Power Saving Enable AV25 U9
TX1M_DPA1N VGA_HDMI_TXD1- 31
TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode 1 1 8 VGA_SMB_CK2
VDD SCLK
1: full Tx output swing (Default setting for Desktop) AR8
DVPCNTL_MVP_0 TX2P_DPA0P
AT27 VGA_HDMI_TXD2+ 31
AU8 AR26 GPU_THERM_D+ 2 7 VGA_SMB_DA2
DVPCNTL_MVP_1 TX2M_DPA0N VGA_HDMI_TXD2- 31 D+ SDATA
PCI Express Transmitter De-emphasis Enable AP8 2200P_0402_50V7K
DVPCNTL_0 VGA@ THM_ALERT#
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode 1 NC on Park AW8
DVPCNTL_1 TXCBP_DPB3P
AR30 1 2 3
D- ALERT#
6
1: Tx de-emphasis enabled (Defailt setting for desktop) AR3 AT29 C247
D DVPCNTL_2 TXCBM_DPB3N GPU_THERM_D- D
AR1 4 5
VRAM_ID0 DVPCLK THERM# GND
GPIO13,12,11 (config 2,1,0) : memory apertures AU1 AV31 1 VGA@ 2 +3VSDGPU
VRAM_ID1 DVPDATA_0 TX3P_DPB2P R102 4.7K_0402_5%
CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0] AU3
DVPDATA_1 TX3M_DPB2N
AU30
CONFIG[1] GPIO12 VRAM_ID2 AW3 DPB ADM1032ARMZ-2REEL_MSOP8
the ROM type. 128 MB 000 DVPDATA_2
CONFIG[0] GPIO11 001 VRAM_ID3 AP6 AR32 VGA@
256 MB 001 * DVPDATA_3 TX4P_DPB1P
b) If BIOS_ROM_EN = 0, then Config[2:0] defines AW5
DVPDATA_4 TX4M_DPB1N
AT31
the primary memory aperture size. 64 MB 010 AU5
DVPDATA_5 +3VSDGPU
AR6 AT33
DVPDATA_6 TX5P_DPB0P
BIOS_ROM_EN GPIO22 Enable external BIOS ROM device AW6
DVPDATA_7 TX5M_DPB0N
AU32
0: Diable, 1: Enable 0 AU6 +3VSDGPU
DVPDATA_8
AT7 AU14
DVPDATA_9 TXCCP_DPC3P
2
00: No audio function; 10: Audio for DisplayPort only; AV7
DVPDATA_10 TXCCM_DPC3N
AV13
AUD[1] HSYNC 11 AN7 R108 R115
01: Audio for DisplayPort and HDMI if adapter is detected; DVPDATA_11
AUD(0) VSYNC AV9 AT15 4.7K_0402_5% 4.7K_0402_5%
11: Audio for both DisplayPort and HDMI DVPDATA_12 TX0P_DPC2P
5
AT9 AR14 VGA@ VGA@
DVPDATA_13 TX0M_DPC2N
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AR10
1
DVPDATA_14 DPC VGA_SMB_CK2 EC_SMB_CK2
BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0 AW10
DVPDATA_15 TX1P_DPC1P
AU16 4 3 EC_SMB_CK2 14,37
5.0 GT/s capability will be controlled by software AU10
DVPDATA_16 TX1M_DPC1N
AV15
AP10 Q5B DMN66D0LDW-7_SOT363-6
DVPDATA_17
2
H2SYNC Internal use only. THIS PAD HAS AN INTERNAL PULL-DOWN AND MUST AV11 AT17 VGA@
DVPDATA_18 TX2P_DPC0P
RESERVED GPIO8 BE 0 V AT RESET. The pad may be left unconnected AT11
DVPDATA_19 TX2M_DPC0N
AR16
GPIO21 AR12 VGA_SMB_DA2 1 6 EC_SMB_DA2
DVPDATA_20 EC_SMB_DA2 14,37
NC on Park AW12
DVPDATA_21 TXCDP_DPD3P
AU20
Q5A DMN66D0LDW-7_SOT363-6
AU12 AT19
+3VSDGPU DVPDATA_22 TXCDM_DPD3N VGA@
AP12
DVPDATA_23
AT21
R74 1 VGA@ VGA_GPIO0 TX3P_DPD2P
2 10K_0402_5% AR20
R111 1 VGA@ 2 10K_0402_5% VGA_GPIO1
+3VSDGPU
TX3M_DPD2N +3VSDGPU R120
R487 1 @ 2 10K_0402_5% VGA_GPIO2 DPD AU22 NC on Park @
TX4P_DPD1P 0_0603_5%
AV21
R71 @ VGA_AC_DET TX4M_DPD1N +3VS
1 2 10K_0402_5% R117 1 VGA@ 2 4.7K_0402_5%
R116 1 VGA@ 2 4.7K_0402_5% I2C AT23 AO3413L_SOT23-3 +3VSDGPU
R95 @ TX5P_DPD0P
1 2 10K_0402_5% SOUT_GPIO8 AR22 Q6 100mA
VGA_LCD_CLK TX5M_DPD0N
AK26 3 1
D
29 VGA_LCD_CLK SCL
R93 1 @ 2 10K_0402_5% SIN_GPIO9 VGA_LCD_DATA AJ26 Not share via for other GND
29 VGA_LCD_DATA SDA
2
1 VGA@ 1
G
2
R113 1 VGA@ 2 10K_0402_5% VGA_GPIO11 AD39 C609 C279 R106
VGA_CRT_R 30
2
R112 @ 10K_0402_5% VGA_GPIO12 GENERAL PURPOSE I/O R R128 VGA@ VGA@ 470_0603_5%
C 1 2 AD37 C
R110 @ 10K_0402_5% VGA_GPIO13 VGA_GPIO0 RB 100K_0402_5% 0.1U_0402_16V7K 10U_0805_6.3V6M VGA@
1 2 AH20
R96 @ 3K_0402_5% ROMSE_GPIO22 VGA_GPIO1 GPIO_0 VGA@ 2 2
1 2 AH18 AE36 VGA_CRT_G 30
1 1
R109 @ 10K_0402_5% GENERICC VGA_GPIO2 GPIO_1 G R739
1 2 AN16 AD35
1
@ GPIO_2 GB D
AH23 1 VGA@ 2
CH751H-40PT_SOD323-2 GPIO_3_SMBDATA 24K_0402_1% Q4
AJ23 AF37 VGA_CRT_B 30 2VGA_ON#
DGPU_BKL_EN VGA_AC_DET GPIO_4_SMBCLK B
16,37 ENBKL 1 DISO@ 2 15,37 EC_ACIN 1 2 AH17 AE38 VGA@ G
R103 0_0402_5% DISCRETE D3 GPIO_5_AC_BATT DAC1 BB
ONLY AJ17 S
3
GPIO_6
1
DGPU_BKL_EN R129 D 2N7002E-T1-GE3_SOT23-3
16 DGPU_BKL_EN AK17 AC36 VGA_CRT_HSYNC 30
SOUT_GPIO8 GPIO_7_BLON HSYNC Q7
Park(XT) AJ13
GPIO_8_ROMSO VSYNC
AC38 VGA_CRT_VSYNC 30 39,43,51,52 VGA_ON 2 1 2
2 VGA@ 1 SIN_GPIO9 AH15 0_0402_5% 1 G VGA@
CLK_GPIO10 GPIO_9_ROMSI VGA@
Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 AJ16 S
3
R104 10K_0402_5% VGA_GPIO11 GPIO_10_ROMSCK R53 VGA@ 499_0402_1% L3 C289 2N7002E-T1-GE3_SOT23-3
VRAM 64Mx16 64Mx16 AK16
GPIO_11 RSET
AB34 1 2
VGA_GPIO12 AL16 10mil BLM18AG121SN1D_0603 0.1U_0402_16V4Z
GPIO_12 2 43,51,52 VGA_ON#
Samsung 0 1 0 0 VGA_GPIO13 AM16 70mA AD34 +AVDD 2 1 +1.8VSDGPU VGA@
GPIO_13 AVDD VGA@
<4PCS> AM14
GPIO_14_HPD2 AVSSQ
AE34
HYNIX 1 1 0 0 GPU_VID0 AM13 10mil 1 VGA@ 1 VGA@ 1 VGA@
51 GPU_VID0 GPIO_15_PWRCNTL_0
1U_0402_6.3V4Z
C181
0.1U_0402_16V4Z
C182
22U_0805_6.3V6M
C188
<4PCS> T1 @ AK14 45mA AC33 +VDD1DI
THM_ALERT# GPIO_16_SSIN VDD1DI
AMD 1 1 1 0 AG30
GPIO_17_THERMAL_INT VSS1DI
AC34
<4PCS> AN14
GPIO_18_HPD3 2 2 2
Madison(Pro) GPU_VID1
AM17
GPIO_19_CTF L8
51 GPU_VID1 AL13 AC30
GPIO_20_PWRCNTL_1 R2 BLM18AG121SN1D_0603
Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0 2009/08/27 AJ14
GPIO_21_BB_EN R2B
AC31
VRAM ROMSE_GPIO22 AK13 2 1
64Mx16 64Mx16 remove BB_EN AN13
GPIO_22_ROMCSB
AD30 VGA@
+1.8VSDGPU
14 PEG_CLKREQ# GPIO_23_CLKREQB G2
Samsung 0 0 0 0 JTAG_TRSTB AM23 AD31 1 VGA@ 1 VGA@ 1 VGA@
JTAG_TRSTB G2B
1U_0402_6.3V4Z
C156
0.1U_0402_16V4Z
C154
10U_0603_6.3V6M
C219
<8PCS> T6 @ AN23
VGA_CLK_27M_R JTAG_TDI
HYNIX 1 0 0 0 AK23
JTAG_TCK B2
AF30 SM010030010
<8PCS> JTAG_TMS AL24 AF31
JTAG_TMS B2B 2 2 2 200ma 120ohm@100mhz DCR 0.2
AMD 1 0 1 0 T5 @ AM24
JTAG_TDO
<8PCS> 2009/09/18 For AMD roger AJ19
GENERICA
ID3: VRAM Vender ID2: VRAM Size ID1: VRAM Vender Ass Option Circuit for Solve Intermittent System AK19
GENERICB C
AC32
GENERICC AJ20 AD32
X76@ X76@ X76@ X76@ Boot-up Hangs,R717,R718,VGA_CLK_27M_R GENERICC Y
+1.8VSDGPU AK20 AF32
GENERICD COMP
AJ24
GENERICE_HPD4
1
1
10K_0402_5%
R491
10K_0402_5%
R482
10K_0402_5%
R473
10K_0402_5%
R477
AH26 DAC2
GENERICF H2SYNC
Park NC pins AH24
GENERICG H2SYNC
AD29
V2SYNC
AC29
B V2SYNC B
VGA_HDMI_DET +3VSDGPU
31 VGA_HDMI_DET AK24 10mil
2
1
10K_0402_5%
R492
10K_0402_5%
R483
10K_0402_5%
R474
10K_0402_5%
R478
1U_0402_6.3V4Z
C599
0.1U_0402_16V4Z
C172
10U_0603_6.3V6M
C600
R101 1 VGA@ 2 249_0402_1% 10mil 1 1 1 Strap VGA_CRT_VSYNC R447 1 VGA@ 2 10K_0402_5%
20mA AD33 +A2VDDQ VGA_CRT_HSYNC R460 1 VGA@ 2 10K_0402_5%
A2VDDQ
PD-Reset 1 2 C244 +VGA_VREF AH13
VGA@ 0.1U_0402_16V4Z VREFG
AF33
A2VSSQ R56 2 2 2 VGA_HDMI_SCLK R506 VGA@ 10K_0402_5%
1 2
2
1U_0402_6.3V4Z
C236
1U_0402_6.3V4Z
C215
0.1U_0402_16V4Z
C216
10U_0603_6.3V6M
C218
+3VSDGPU 1 @ 2 JTAG_TMS 2 1 +DPLL_VDDC AN31 150mA AM19
R718 10K_0402_5% VGA@ DPLL_VDDC DDC2CLK
1 1 1 AL19
VGA@ VGA@ VGA@ DDC2DATA 2 2 2
10U_0603_6.3V6M
C243
0.1U_0402_16V4Z
C196
1U_0402_6.3V4Z
C197
XTALOUT
2 1 AJ32
TSVDD 20mA DDC6CLK
AJ30 2 1 3
W
2 1 27MCLK VGA@ 1 1 1 AJ33 AJ31 R94 0_0402_5%
R500 1M_0402_5% VGA@ VGA@ VGA@ TSVSS DDC6DATA @
2 1 8 4
VCC VSS
10U_0603_6.3V6M
C220
1U_0402_6.3V4Z
C221
0.1U_0402_16V4Z
C180
MAA[0..12] MAB[0..12]
MDA[0..63] MAA[0..12] 27 MDB[0..63] MAB[0..12] 28
D 27 MDA[0..63] MDA0 MAA0 28 MDB[0..63] MDB0 MAB0 D
C37 DQA_0 MAA_0 G24 C5 DQB_0 MAB_0 P8
MDA1 C35 J23 MAA1 MDB1 C3 T9 MAB1
MEMORY INTERFACE A
MEMORY INTERFACE B
MDA2 DQA_1 MAA_1 MAA2 MDB2 DQB_1 MAB_1 MAB2
A35 DQA_2 MAA_2 H24 E3 DQB_2 MAB_2 P9
MDA3 E34 J24 MAA3 MDB3 E1 N7 MAB3
MDA4 DQA_3 MAA_3 MAA4 MDB4 DQB_3 MAB_3 MAB4
G32 H26 F1 N8
MDA5 DQA_4 MAA_4 MAA5 MDB5 DQB_4 MAB_4 MAB5
D33 DQA_5 MAA_5 J26 F3 DQB_5 MAB_5 N9
MDA6 F32 H21 MAA6 MDB6 F5 U9 MAB6
MDA7 DQA_6 MAA_6 MAA7 MDB7 DQB_6 MAB_6 MAB7
E32 DQA_7 MAA_7 G21 G4 DQB_7 MAB_7 U8
MDA8 D31 H19 MAA8 MDB8 H5 Y9 MAB8
MDA9 DQA_8 MAA_8 MAA9 MDB9 DQB_8 MAB_8 MAB9
F30 H20 H6 W9
MDA10 DQA_9 MAA_9 MAA10 MDB10 DQB_9 MAB_9 MAB10
C30 DQA_10 MAA_10 L13 J4 DQB_10 MAB_10 AC8
MDA11 A30 G16 MAA11 MDB11 K6 AC9 MAB11
MDA12 DQA_11 MAA_11 MAA12 A_BA[0..2] MDB12 DQB_11 MAB_11 MAB12 B_BA[0..2]
F28 DQA_12 MAA_12 J16 A_BA[0..2] 27 K5 DQB_12 MAB_12 AA7 B_BA[0..2] 28
MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
MDA14 DQA_13 MAA_13/BA2 A_BA0 MDB14 DQB_13 MAB_13/BA2 B_BA0
A28 J17 M6 Y8
MDA15 DQA_14 MAA_14/BA0 A_BA1 MDB15 DQB_14 MAB_14/BA0 B_BA1
E28 H17 M1 AA9
MDA16 DQA_15 MAA_15/BA1 DQMA#[0..7] MDB16 DQB_15 MAB_15/BA1 DQMB#[0..7]
D27 DQA_16 DQMA#[0..7] 27 M3 DQB_16 DQMB#[0..7] 28
MDA17 F26 A32 DQMA#0 MDB17 M5 H3 DQMB#0
MDA18 DQA_17 DQMA_0 DQMA#1 MDB18 DQB_17 DQMB_0 DQMB#1
C26 DQA_18 DQMA_1 C32 N4 DQB_18 DQMB_1 H1
MDA19 A26 D23 DQMA#2 MDB19 P6 T3 DQMB#2
MDA20 DQA_19 DQMA_2 DQMA#3 MDB20 DQB_19 DQMB_2 DQMB#3
F24 E22 P5 T5
MDA21 DQA_20 DQMA_3 DQMA#4 MDB21 DQB_20 DQMB_3 DQMB#4
C24 C14 R4 AE4
MDA22 DQA_21 DQMA_4 DQMA#5 MDB22 DQB_21 DQMB_4 DQMB#5
A24 DQA_22 DQMA_5 A14 T6 DQB_22 DQMB_5 AF5
MDA23 E24 E10 DQMA#6 MDB23 T1 AK6 DQMB#6
MDA24 DQA_23 DQMA_6 DQMA#7 MDB24 DQB_23 DQMB_6 DQMB#7
C22 D9 U4 AK5
MDA25 DQA_24 DQMA_7 QSA[0..7] MDB25 DQB_24 DQMB_7 QSB[0..7]
A22 DQA_25 QSA[0..7] 27 V6 DQB_25 QSB[0..7] 28
MDA26 F22 C34 QSA0 MDB26 V1 F6 QSB0
MDA27 DQA_26 QSA_0/RDQSA_0 QSA1 MDB27 DQB_26 QSB_0/RDQSB_0 QSB1
D21 D29 V3 K3
MDA28 DQA_27 QSA_1/RDQSA_1 QSA2 MDB28 DQB_27 QSB_1/RDQSB_1 QSB2
A20 DQA_28 QSA_2/RDQSA_2 D25 Y6 DQB_28 QSB_2/RDQSB_2 P3
MDA29 F20 E20 QSA3 MDB29 Y1 V5 QSB3
MDA30 DQA_29 QSA_3/RDQSA_3 QSA4 MDB30 DQB_29 QSB_3/RDQSB_3 QSB4
D19 E16 Y3 AB5
MDA31 DQA_30 QSA_4/RDQSA_4 QSA5 MDB31 DQB_30 QSB_4/RDQSB_4 QSB5
E18 E12 Y5 AH1
C MDA32 DQA_31 QSA_5/RDQSA_5 QSA6 MDB32 DQB_31 QSB_5/RDQSB_5 QSB6 C
C18 DQA_32 QSA_6/RDQSA_6 J10 AA4 DQB_32 QSB_6/RDQSB_6 AJ9
MDA33 A18 D7 QSA7 MDB33 AB6 AM5 QSB7
MDA34 DQA_33 QSA_7/RDQSA_7 QSA#[0..7] MDB34 DQB_33 QSB_7/RDQSB_7 QSB#[0..7]
F18 QSA#[0..7] 27 AB1 QSB#[0..7] 28
MDA35 DQA_34 QSA#0 MDB35 DQB_34 QSB#0
D17 DQA_35 QSA_0B/WDQSA_0 A34 AB3 DQB_35 QSB_0B/WDQSB_0 G7
MDA36 A16 E30 QSA#1 MDB36 AD6 K1 QSB#1
MDA37 DQA_36 QSA_1B/WDQSA_1 QSA#2 MDB37 DQB_36 QSB_1B/WDQSB_1 QSB#2
F16 E26 AD1 P1
MDA38 DQA_37 QSA_2B/WDQSA_2 QSA#3 MDB38 DQB_37 QSB_2B/WDQSB_2 QSB#3
D15 DQA_38 QSA_3B/WDQSA_3 C20 AD3 DQB_38 QSB_3B/WDQSB_3 W4
MDA39 E14 C16 QSA#4 MDB39 AD5 AC4 QSB#4
MDA40 DQA_39 QSA_4B/WDQSA_4 QSA#5 MDB40 DQB_39 QSB_4B/WDQSB_4 QSB#5
F14 DQA_40 QSA_5B/WDQSA_5 C12 AF1 DQB_40 QSB_5B/WDQSB_5 AH3
MDA41 D13 J11 QSA#6 MDB41 AF3 AJ8 QSB#6
MDA42 DQA_41 QSA_6B/WDQSA_6 QSA#7 +1.5VSDGPU MDB42 DQB_41 QSB_6B/WDQSB_6 QSB#7
F12 DQA_42 QSA_7B/WDQSA_7 F8 AF6 DQB_42 QSB_7B/WDQSB_7 AM3
MDA43 A12 MDB43 AG4
+1.5VSDGPU MDA44 DQA_43 ODTA0 MDB44 DQB_43 ODTB0
D11 DQA_44 ODTA0 J21 ODTA0 27 AH5 DQB_44 ODTB0 T7 ODTB0 28
MDA45 F10 G19 ODTA1 MDB45 AH6 W7 ODTB1
DQA_45 ODTA1 ODTA1 27 DQB_45 ODTB1 ODTB1 28
1
MDA46 A10 MDB46 AJ4
MDA47 DQA_46 CLKA0 R47 MDB47 DQB_46 CLKB0
C10 H27 CLKA0 27 AK3 L9 CLKB0 28
DQA_47 CLKA0 DQB_47 CLKB0
1
2
40.2_0402_1% MDA51 DQA_50 CLKA1 CLKA1# MVREFDB MDB51 DQB_50 CLKB1 CLKB1#
20mil MDA52
H11 DQA_51 CLKA1B H14 CLKA1# 27 MDB52
AG7 DQB_51 CLKB1B AD7 CLKB1# 28
G10 AK9
2
DQA_52 DQB_52
1
MVREFDA MDA53 G8 K23 RASA0# MDB53 AL7 T10 RASB0#
MDA54 DQA_53 RASA0B RASA1# RASA0# 27 MDB54 DQB_53 RASB0B RASB1# RASB0# 28
K9 K19 RASA1# 27 1 AM8 Y10 RASB1# 28
DQA_54 RASA1B DQB_54 RASB1B
1
0.1U_0402_16V4Z
C112
1 MDA55 K10 R44 MDB55 AM7
DQA_55 DQB_55
0.1U_0402_16V4Z
C78
2
100_0402_1% MDA58 DQA_57 CASA1B 2 MDB58 DQB_57 CASB1B
C8 DQA_58 AM6 DQB_58
2 VGA@ MDA59 E8 K24 CSA0#_0 MDB59 AM1 P10 CSB0#_0
CSA0#_0 27 CSB0#_0 28
2
1
MVREFSB AA12
WEA0# MVREFSB WEB0#
1 VGA@ 2 L27 K26 WEA0# 27
R54 N10 WEB0# 28
NC_MEM_CALRN0 WEA0B WEB0B
1
R33 1 VGA@ 2 240_0402_1% N12 L15 WEA1# VGA@ 23 TESTEN AB11 WEB1#
NC_MEM_CALRN1 WEA1B WEA1# 27 WEB1B WEB1# 28
R34 R40 1 VGA@ 2 240_0402_1% AG12 40.2_0402_1% 20mil R64
R65 240_0402_1% NC_MEM_CALRN2 GCORE_SEN 10K_0402_5% R63
AF28 GCORE_SEN 51
2
40.2_0402_1% RSVD#1 MVREFSB TESTEN
20mil 1 VGA@ 2 M12 AG28 1 2 AD28 4.7K_0402_5%
VGA@ R38 MEM_CALRP1 RSVD#2 TESTEN
1 VGA@ 2 240_0402_1% M27 AL31 2009/08/20 del AG28 VDDCI_SEN VGA@ R66 1 @ 2 +1.5VSDGPU
2
0.1U_0402_16V4Z
C147
R70 240_0402_1% H23 R57 TEST_YCLK AL10 AH11 1 2
RSVD#5 MAA13 27 CLKTESTB DRAM_RST VRAM_RST# 27,28
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R35 100_0402_1% VGA@
2
VGA@ 2 R68
T8 MAB13 28 2 2 1 C168
2
RSVD#9
C184
C193
100_0402_1% W8
2 VGA@ RSVD#11 VGA@ VGA@
2
1
216-0729002 A12 M96_BGA962
1
MADI@ If use M96 upper resistor will
If use M96 upper resistor will In M97, Medison and Park, AF28 is change to 100ohm for
change to 100ohm for FB_VDDC, AG28 is FB_VDDCI, AH29 is MVREFDA/B and MVREFSA/B VGA@ R72 R75
VGA@
2
MVREFDA/B and MVREFSA/B FB_GND. GCORE_SEN and FB_GND 51.1_0402_1% 51.1_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Memory
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 24 of 59
5 4 3 2 1
5 4 3 2 1
2009/09/14
U34E update P/N SM010005500 500ma 600ohm@100MHZ DCR 0.38
+1.5VSDGPU
MEM I/O
2900mA
1U_0402_6.3V4Z
C127
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 PCIE VGA@
TBD AC7 400mA 40mil
1U_0402_6.3V4Z
C192
1U_0402_6.3V4Z
C199
1U_0402_6.3V4Z
C138
1U_0402_6.3V4Z
C65
1U_0402_6.3V4Z
C179
1U_0402_6.3V4Z
C159
1U_0402_6.3V4Z
C158
C492 + AA31 +PCIE_VDDR 2 1
VDDR1#1 PCIE_VDDR#1 +1.8VSDGPU
VGA@ AD11 AA32 L42
VDDR1#2 PCIE_VDDR#2
AF7 AA33 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ BLM18AG601SN1D_2P
2
2 2 2 2 2 2 2 2 VDDR1#3 PCIE_VDDR#3
0.1U_0402_16V4Z
C150
0.1U_0402_16V4Z
C124
1U_0402_6.3V4Z
C108
1U_0402_6.3V4Z
C139
1U_0402_6.3V4Z
C109
1U_0402_6.3V4Z
C588
1U_0402_6.3V4Z
C587
10U_0805_6.3V6M
C589
330U_2.5V_M_R15 AG10 AA34
VDDR1#4 PCIE_VDDR#4
AJ7 VDDR1#5 PCIE_VDDR#5 V28
AK8 W29
VDDR1#6 PCIE_VDDR#6 2 2 2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
G11 Y31
VDDR1#8 PCIE_VDDR#8
1U_0402_6.3V4Z
C608
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 G14 VDDR1#9
1U_0402_6.3V4Z
C91
1U_0402_6.3V4Z
C79
1U_0402_6.3V4Z
C83
1U_0402_6.3V4Z
C68
1U_0402_6.3V4Z
C82
1U_0402_6.3V4Z
C531
1U_0402_6.3V4Z
C602
D D
G17 VDDR1#10 2A
G20 VDDR1#11 PCIE_VDDC#1 G30 +1.0VSDGPU
G23 VDDR1#12 PCIE_VDDC#2 G31
2 2 2 2 2 2 2 2 G26
VDDR1#13 PCIE_VDDC#3
H29 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
1U_0402_6.3V4Z
C122
1U_0402_6.3V4Z
C90
1U_0402_6.3V4Z
C85
1U_0402_6.3V4Z
C77
1U_0402_6.3V4Z
C74
1U_0402_6.3V4Z
C70
1U_0402_6.3V4Z
C55
10U_0805_6.3V6M
C56
G29 H30
VDDR1#14 PCIE_VDDC#4
H10 VDDR1#15 PCIE_VDDC#5 J29
J7 J30
VDDR1#16 PCIE_VDDC#6 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z
C64
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 J9 L28
VDDR1#17 PCIE_VDDC#7
10U_0805_6.3V6M
C501
10U_0805_6.3V6M
C498
10U_0805_6.3V6M
C484
10U_0805_6.3V6M
C483
10U_0805_6.3V6M
C482
1U_0402_6.3V4Z
C530
1U_0402_6.3V4Z
C201
1U_0402_6.3V4Z
C209
K11 VDDR1#18 PCIE_VDDC#8 M28
K13 N28
VDDR1#19 PCIE_VDDC#9
K8 VDDR1#20 PCIE_VDDC#10 R28
2 2 2 2 2 2 2 2 2 L12 T28
VDDR1#21 PCIE_VDDC#11
L16 VDDR1#22 PCIE_VDDC#12 U28
L21
VDDR1#23
L23
VDDR1#24 34.6A
L26 AA15 +VGA_CORE
VDDR1#25 CORE VDDC#1
+1.8VSDGPU 1 2 L7 VDDR1#26 VDDC#2 AA17 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V4Z
C152
1U_0402_6.3V4Z
C144
1U_0402_6.3V4Z
C177
1U_0402_6.3V4Z
C132
1U_0402_6.3V4Z
C133
1U_0402_6.3V4Z
C118
1U_0402_6.3V4Z
C114
1U_0402_6.3V4Z
C145
1U_0402_6.3V4Z
C104
1U_0402_6.3V4Z
C130
L43 1 1 1 M11 AA20
VDDR1#27 VDDC#3
0.1U_0402_16V4Z
C163
BLM18AG121SN1D_0603 VGA@ VGA@ VGA@ N11 AA22
VDDR1#28 VDDC#4
10U_0603_6.3V6M
C591
1U_0402_6.3V4Z
C175
VGA@ P7 AA24
VDDR1#29 VDDC#5 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2 VGA@ 2
R11 AA27
2 2 2 VDDR1#30 VDDC#6
SM010030010 U11
VDDR1#31 VDDC#7
AB13
200ma 120ohm@100mhz DCR 0.2 U7 VDDR1#32 VDDC#8 AB16
Y11 VDDR1#33 VDDC#9 AB18
Y7 AB21
VDDR1#34 VDDC#10
1U_0402_6.3V4Z
C135
1U_0402_6.3V4Z
C185
1U_0402_6.3V4Z
C89
1U_0402_6.3V4Z
C176
1U_0402_6.3V4Z
C146
1U_0402_6.3V4Z
C148
1U_0402_6.3V4Z
C131
1U_0402_6.3V4Z
C117
1U_0402_6.3V4Z
C116
1U_0402_6.3V4Z
C143
AB23 VGA@ 1 1 1 1 1 1 1 1 1 1
VDDC#11
+3VSDGPU 2 1 AB26
L5 VDDC#12 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 1 1 AB28
VDDC#13
0.1U_0402_16V4Z
C183
BLM18AG121SN1D_0603 VGA@ VGA@ VGA@ AC12
VDDC#14 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
C186
1U_0402_6.3V4Z
C166
VGA@ 20mil LEVEL AC15
TRANSLATION VDDC#15
2 2 2 136mA VDDC#16
AC17
POWER
+VDD_CT AF26 AC20
C 2009/09/14 VDD_CT#1 VDDC#17 C
AF27 VDD_CT#2 VDDC#18 AC22
10U_0805_6.3V6M
C5
10U_0805_6.3V6M
C4
10U_0805_6.3V6M
C3
10U_0805_6.3V6M
C9
10U_0805_6.3V6M
C8
10U_0805_6.3V6M
C7
10U_0805_6.3V6M
C6
update P/N SM010005500 500ma 600ohm@100MHZ DCR 0.38 AG26
VDD_CT#3 VDDC#19
AC24 1 1 1 1 1 1 1 1 1
AG27 AC27
VDD_CT#4 VDDC#20 VGA@ + C1 VGA@ + C2
VDDC#21 AD13
+1.8VSDGPU 2 1 AD16 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
L14 I/O VDDC#22 2 2 2 2 2 2 2 330U_D2_2V_Y 330U_D2_2V_Y
+VDDR3
60mA VDDC#23
AD18
2 2
BLM18AG601SN1D_2P 1 VGA@ 1 VGA@ 1 VGA@ AF23 AD21
VDDR3#1 VDDC#24
10U_0603_6.3V6M
C259
1U_0402_6.3V4Z
C169
0.1U_0402_16V4Z
C170
VGA@ 10mil AF24 AD23
VDDR3#2 VDDC#25
AG23 VDDR3#3 VDDC#26 AD26
AG24 AF17
2 2 2 VDDR3#4 VDDC#27
20mil VDDC#28 AF20
+VDDR4_5
170mA VDDC#29
AF22
AF13
AF15
VDDR5#1 VDDC#30 AG16
AG18
2009/08/27
VDDR5#2 VDDC#31
AG13
VDDR5#3 VDDC#32
AG21 RemoveBack Biasing
AG15 AH22
VDDR5#4 VDDC#33
M16
VDDC#34
170mA VDDC#35
M18
AD12 M23
VDDR4#1 VDDC#36
AF11 VDDR4#2 VDDC#37 M26
AF12 N15
VDDR4#3 VDDC#38
AG11
VDDR4#4 VDDC#39
N17 2009/09/17
N20
VDDC#40
N22
ADD BIF_VDDCI N27,T27
VDDC#41
N24
MEM CLK VDDC#42 R716 1 VGA@ 2 0_0603_5%
N27 +VGA_CORE
VDDC#43
SM010030010 L37 2009/08/27 M20 VDDRHA VDDC#44 R13
200ma 120ohm@100mhz DCR 0.2 +1.8VSDGPU 2 1 M21 R16
VGA@ remove VDDRHA,VDDRHB VSSRHA VDDC#45
R18
BLM18AG121SN1D_0603 1 VGA@ 1 VGA@ 1 VDDC#46
R21
VDDC#47
10U_0603_6.3V6M
C566
1U_0402_6.3V4Z
C565
0.1U_0402_16V4Z
C564
1U_0402_6.3V4Z
C518
0.1U_0402_16V4Z
C517
1U_0402_6.3V4Z
C521
0.1U_0402_16V4Z
C522
1U_0402_6.3V4Z
C206
0.1U_0402_16V4Z
C198
L58 V27
VDDC#66
+1.8VSDGPU 2 1 Y16
VDDC#67
1U_0402_6.3V4Z
C94
BLM18AG121SN1D_0603 VGA@ Y18 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1
2 2 2 VDDC#68
1U_0402_6.3V4Z
C92
1U_0402_6.3V4Z
C137
1U_0402_6.3V4Z
C101
1U_0402_6.3V4Z
C102
1U_0402_6.3V4Z
C100
1U_0402_6.3V4Z
C162
1U_0402_6.3V4Z
C93
1U_0402_6.3V4Z
C88
1U_0402_6.3V4Z
C103
VGA@ 1 VGA@ 1 VGA@ 1 Y21
VDDC#69
10U_0603_6.3V6M
C655
1U_0402_6.3V4Z
C646
0.1U_0402_16V4Z
C649
0.1U_0402_16V4Z
C107
10U_0805_6.3V6M
C514
R12 VGA@ 1 VGA@ 1 VGA@ 1 FBMA-L11-201209-221LMA30T_0805
VDDCI#3
10U_0805_6.3V6M
C513
10U_0805_6.3V6M
C515
T12
VDDCI#4
2 1
2 2 L34 VGA@
A 2 2 2 FBMA-L11-201209-221LMA30T_0805 A
216-0729002 A12 M96_BGA962
MADI@ 2009/08/27 SM010014520 3000ma 220ohm@100mhz DCR 0.04
short BBP
Back Bias is not supported on Security Classification Compal Secret Data Compal Electronics, Inc.
M97,Broadway,Madison and Park Issued Date 2009/08/01 2010/08/01 Title
Deciphered Date
Connect to VDDCI directly
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M96_Power/GND
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 25 of 59
5 4 3 2 1
5 4 3 2 1
U34F L18
BLM18AG121SN1D_0603
+1.8VSDGPU 2 1 +1.8VSDGPU
VGA@
AB39
PCIE_VSS#1 GND#1
A3 1 VGA@ 1 VGA@ 1 1 1 1 For M96 are NC pins
10U_0603_6.3V6M
C255
0.1U_0402_16V4Z
C246
1U_0402_6.3V4Z
C239
E39 A37 For M96 are NC pins VGA@ VGA@ VGA@
PCIE_VSS#2 GND#2
10U_0603_6.3V6M
C266
0.1U_0402_16V4Z
C264
1U_0402_6.3V4Z
C265
F34 PCIE_VSS#3 GND#3 AA16
VGA@
F39 PCIE_VSS#4 GND#4 AA18
2 2 2 2 2 2
SM010030010
G33 PCIE_VSS#5 GND#5 AA2 SM010030010 200ma 120ohm@100mhz DCR 0.2
G34 AA21 200ma 120ohm@100mhz DCR 0.2
PCIE_VSS#6 GND#6
H31 PCIE_VSS#7 GND#7 AA23
H34 AA26
PCIE_VSS#8 GND#8
H39 PCIE_VSS#9 GND#9 AA28
J31 AA6 L12
PCIE_VSS#10 GND#10 BLM18AG121SN1D_0603
J34 PCIE_VSS#11 GND#11 AB12 +1.0VSDGPU
D D
K31 PCIE_VSS#12 GND#12 AB15 2 1 +1.0VSDGPU
K34 AB17 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
PCIE_VSS#13 GND#13
10U_0603_6.3V6M
C640
0.1U_0402_16V4Z
C625
1U_0402_6.3V4Z
C633
K39 PCIE_VSS#14 GND#14 AB20
L31 AB22 VGA@ 1 VGA@ 1 VGA@ 1
PCIE_VSS#15 GND#15
0.1U_0402_16V4Z
C237
1U_0402_6.3V4Z
C207
10U_0603_6.3V6M
C248
L34 AB24 U34H
PCIE_VSS#16 GND#16 2 2 2
M34 PCIE_VSS#17 GND#17 AB27
DP C/D POWER DP A/B POWER
M39
PCIE_VSS#18 GND#18
AC11 130mA 130mA 2 2 2
N31 PCIE_VSS#19 GND#19 AC13 20mil 20mil
N34 PCIE_VSS#20 GND#20 AC16 AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24
P31 AC18 +DPC_VDD18 AP21 AP24 +DPA_VDD18
PCIE_VSS#21 GND#21 NC_DPC_VDD18#2 NC_DPA_VDD18#2
P34 PCIE_VSS#22 GND#22 AC2
P39
PCIE_VSS#23 GND#23
AC21 +1.8VSDGPU 200mA 200mA
R34 PCIE_VSS#24 GND#24 AC23 1 1 1 20mil 20mil +1.8VSDGPU
T31 AC26 For M96 are NC pins VGA@ VGA@ VGA@ AP13 AP31
PCIE_VSS#25 GND#25 DPC_VDD10#1 DPA_VDD10#1
10U_0603_6.3V6M
C254
0.1U_0402_16V4Z
C238
1U_0402_6.3V4Z
C245
T34 AC28 +DPC_VDD10 AT13 AP32 +DPA_VDD10 VGA@ VGA@ VGA@ For M96 are NC pins
PCIE_VSS#26 GND#26 DPC_VDD10#2 DPA_VDD10#2
T39 AC6 1 1 1
PCIE_VSS#27 GND#27 2 2 2
0.1U_0402_16V4Z
C205
1U_0402_6.3V4Z
C240
10U_0603_6.3V6M
C252
U31 PCIE_VSS#28 GND#28 AD15
U34 AD17 AN17 AN27
PCIE_VSS#29 GND#29 DPC_VSSR#1 DPA_VSSR#1
V34 PCIE_VSS#30 GND#30 AD20 AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
V39 AD22 AP17 AP28 2 2 2
PCIE_VSS#31 GND#31 DPC_VSSR#3 DPA_VSSR#3
W31 AD24 AW14 AW24
PCIE_VSS#32 GND#32 DPC_VSSR#4 DPA_VSSR#4
W34 AD27 +1.0VSDGPU AW16 AW26
PCIE_VSS#33 GND#33 DPC_VSSR#5 DPA_VSSR#5
Y34 PCIE_VSS#34 GND#34 AD9
Y39 AE2 VGA@ 1 VGA@ 1 VGA@ 1 130mA
PCIE_VSS#35 GND#35
10U_0603_6.3V6M
C641
0.1U_0402_16V4Z
C634
1U_0402_6.3V4Z
C626
GND#36
AE6 20mil 130mA 20mil +1.0VSDGPU
GND#37 AF10 SM010030010 AP22 NC_DPD_VDD18#1 NC_DPB_VDD18#1 AP25
AF16 +DPD_VDD18 AP23 AP26 +DPB_VDD18 VGA@ 1 VGA@ 1 VGA@ 1
GND#38 200ma 120ohm@100mhz DCR 0.2 2 2 2 NC_DPD_VDD18#2 NC_DPB_VDD18#2
0.1U_0402_16V4Z
C200
1U_0402_6.3V4Z
C629
10U_0603_6.3V6M
C632
GND#39
AF18 SM010030010
AF21 20mil 200mA 200mA
F15
GND#101
GND GND#40
GND#41
GND#42
AG17
AG2 2009/09/04 +DPD_VDD10 AP14
DPD_VDD10#1 DPB_VDD10#1
AN33
20mil 2 2 2
200ma 120ohm@100mhz DCR 0.2
10U_0603_6.3V6M
C597
0.1U_0402_16V4Z
C595
1U_0402_6.3V4Z
C596
F29 AJ10 AP19 AP30 VGA@ 1 VGA@ 1 VGA@ 1
GND#108 GND#49 DPD_VSSR#3 DPB_VSSR#3
1
0.1U_0402_16V4Z
C636
1U_0402_6.3V4Z
C627
10U_0603_6.3V6M
C645
F31 GND#109 GND#50 AJ11 AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
F33 AJ2 R69 AW22 AW32
GND#110 GND#51 2 2 2 DPD_VSSR#5 DPB_VSSR#5
F7 GND#111 GND#52 AJ28 0_0402_5%
F9 AJ6 @ R486 R494 2 2 2
GND#112 GND#53 150_0402_1% 150_0402_1%
G2 AK11
2
GND#113 GND#54
G6 AK31 2 1 AW18 AW28 1 2
GND#114 GND#55 DPCD_CALR DPAB_CALR
H9 GND#115 GND#56 AK7 PX_EN: VGA@ VGA@
J2
GND#116 GND#57
AL11 AL21should be leave NC since 20mil 200mA 20mA
J27
GND#117 GND#58
AL14
SBIOS will control VGA power on/off. +DPE_VDD18
DP E/F POWER DP PLL POWER
+DPA_PVDD
10mil +1.8VSDGPU
J6 AL17 AH34 AU28
GND#118 GND#59 DPE_VDD18#1 DPA_PVDD VGA@ 1 VGA@ 1 VGA@ 1
J8 AL2 AJ34 AV27
GND#119 GND#60 DPE_VDD18#2 DPA_PVSS
0.1U_0402_16V4Z
C628
1U_0402_6.3V4Z
C637
10U_0603_6.3V6M
C644
K14
GND#120 GND#61
AL20 SM010030010
PX_EN L9 +DPE_VDD10
K7
GND#121 GND#62
AL21 20mil 120mA 20mA 200ma 120ohm@100mhz DCR 0.2
L11 AL23 BLM18AG121SN1D_0603 10mil
GND#122 GND#63
1
0.1U_0402_16V4Z
C191
1U_0402_6.3V4Z
C226
L24 AL8 @ 20mA
GND#126 GND#67
L6 AM11 10mil
2
0.1U_0402_16V4Z
C630
1U_0402_6.3V4Z
C622
10U_0603_6.3V6M
C638
N16
GND#131 GND#72
AN2
but have another ball
AU37
DPE_VSSR#4 20mA
N18 AN30 1 @ 2 AW35 10mil
GND#132 GND#73 R484 0_0402_5% DPE_VSSR#5 +DPD_PVDD
N2 AN6 name in Broadway, AV19
GND#133 GND#74 DPD_PVDD 2 2 2
B
N21
GND#134 GND#75
AN8
that is XO_IN and 200mA DPD_PVSS
AR18
B
N23 GND#135 GND#76 AP11 20mil
N26 GND#136 GND#77 AP7 X0_IN2. AF34 DPF_VDD18#1 20mA
N6 AP9 +DPE_VDD18 AG34 10mil
GND#137 GND#78 +DPE_VDD18 DPF_VDD18#2
R15 AR5 AM37 +DPE_PVDD
GND#138 GND#79 @ DPE_PVDD
R17
GND#139 GND#80
AW34 1 2 20mil 120mA DPE_PVSS
AN38 +1.8VSDGPU
R2 B11 R490 0_0402_5%
GND#140 GND#81 VGA@ 1 VGA@ 1 VGA@ 1
R20
GND#141 GND#82
B13 AK33
DPF_VDD10#1 20mA
0.1U_0402_16V4Z
C631
1U_0402_6.3V4Z
C623
10U_0603_6.3V6M
C639
R22 B15 +DPE_VDD10 AK34 10mil
GND#142 GND#83 +DPE_VDD10 DPF_VDD10#2
R24 B17 AL38 +DPF_PVDD SM010030010
GND#143 GND#84 NC_DPF_PVDD
R27 GND#144 GND#85 B19 NC_DPF_PVSS AM35 200ma 120ohm@100mhz DCR 0.2
2 2 2
R6 GND#145 GND#86 B21
T11 B23 AF39
GND#146 GND#87 DPF_VSSR#1
T13 GND#147 GND#88 B25 AH39 DPF_VSSR#2
T16 B27 AK39
GND#148 GND#89 DPF_VSSR#3 L50
T18 GND#149 GND#90 B29 AL34 DPF_VSSR#4
T21 B31 AM34 BLM18AG121SN1D_0603
GND#150 GND#91 DPF_VSSR#5
T23 B33 2 1 +1.8VSDGPU
GND#151 GND#92 VGA@
T26 B7
GND#152 GND#93 R479 VGA@ 1 VGA@ 1 VGA@ 1
U15 B9
GND#153 GND#94
0.1U_0402_16V4Z
C619
1U_0402_6.3V4Z
C620
10U_0603_6.3V6M
C621
U17 C1 2 1 AM39
GND#154 GND#95 VGA@ DPEF_CALR
U2 C39
GND#155 GND#96 150_0402_1%
U20 GND#156 GND#97 E35
U22 E5 216-0729002 A12 M96_BGA962 2 2 2
GND#157 GND#98 MADI@
U24 GND#158 GND#99 F11
U27 F13
GND#159 GND#100
U6
GND#160 L46
V11 GND#161
V16 BLM18AG121SN1D_0603
GND#162
V18 2 1 +1.8VSDGPU
GND#163 VGA@
V21
GND#164 VGA@
V23
GND#165 1 VGA@ 1 VGA@ 1 For M96 are NC pins
0.1U_0402_16V4Z
C604
1U_0402_6.3V4Z
C605
10U_0603_6.3V6M
C606
V26 GND#166
A A
W2
GND#167
W6 GND#168 2 2 2
Y15 GND#169
Y17
GND#170
Y20 GND#171
Y22 A39
GND#172 VSS_MECH#1
Y24 GND#173 VSS_MECH#2 AW1
Y27 AW39
U13
GND#174
GND#175
VSS_MECH#3 Security Classification Compal Secret Data Compal Electronics, Inc.
V13 GND#176 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M96_Power/GND
216-0729002 A12 M96_BGA962 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
MADI@ Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 26 of 59
5 4 3 2 1
5 4 3 2 1
U1 U29 U2 U28
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R11 L1 B9 R381 L1 B9 R9 L1 B9 R376 L1 B9
243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ 243_0402_1% NC/CS1 VSSQ
J9 D1 J9 D1 J9 D1 J9 D1
MADI@ NC/CE1 VSSQ MADI@ NC/CE1 VSSQ MADI@ NC/CE1 VSSQ MADI@ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
+1.5VSDGPU X76@ X76@ X76@ X76@
Pull high for Madison and Park... +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
ODTA0_1
1
1
R16 R7 R14 R371 R369 R4 R13 R367 R377
MADI@ 56_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
B ODTA0 2 MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ B
24 ODTA0 1 1 2
R17 0_0402_5% MADI@ 15mil 15mil 15mil 15mil 15mil 15mil 15mil 15mil
2
2
R3 VREFCA_A1 VREFDA_Q1 VREFCA_A2 VREFDA_Q2 VREFCA_A3 VREFDA_Q3 VREFCA_A4 VREFDA_Q4
R5 0_0402_5% 56_0402_1%
1
1
ODTA1 2 1 1 2 1 1 1 1 1 1 1 1
24 ODTA1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
MADI@ R8 C18 R10 R370 C485 R372 C486 R6 C17 R12 C45 R368 C481 R378 C493
MADI@ 4.99K_0402_1% 4.99K_0402_1% C46 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
ODTA1_1 MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@ MADI@
2 2 2 2 2 2 2 2
2
2
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU
1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@ 1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@ 1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@
1U_0402_6.3V6K
C16
1U_0402_6.3V6K
C48
1U_0402_6.3V6K
C52
1U_0402_6.3V6K
C50
1U_0402_6.3V6K
C53
1U_0402_6.3V6K
C499
1U_0402_6.3V6K
C502
1U_0402_6.3V6K
C510
1U_0402_6.3V6K
C508
1U_0402_6.3V6K
C504
1U_0402_6.3V6K
C13
1U_0402_6.3V6K
C47
1U_0402_6.3V6K
C49
1U_0402_6.3V6K
C14
1U_0402_6.3V6K
C51
MADI@ 1 MADI@1 MADI@1 MADI@1 MADI@1 MADI@
1U_0402_6.3V6K
C479
1U_0402_6.3V6K
C503
1U_0402_6.3V6K
C507
1U_0402_6.3V6K
C509
1U_0402_6.3V6K
C495
24 CLKA0 1 2
R383 56_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MADI@ 2 2 2 2 2
24 CLKA0# 1 2
R379 56_0402_1%
+1.5VSDGPU
1
+1.5VSDGPU
C494
0.01U_0402_16V7K
2
MADI@ 1 MADI@1 MADI@1 MADI@1 MADI@
10U_0603_6.3V6M
C478
10U_0603_6.3V6M
C476
10U_0603_6.3V6M
C12
10U_0603_6.3V6M
C11
A
1 MADI@1 MADI@1 MADI@1 MADI@ VRAM P/N : A
MADI@
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
10U_0603_6.3V6M
C477
10U_0603_6.3V6M
C10
10U_0603_6.3V6M
C480
10U_0603_6.3V6M
C15
24 CLKA1 1 2
R384 56_0402_1% 2 2 2 2
2 2 2 2 Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
MADI@
24 CLKA1# 1 2
R380 56_0402_1%
1
C500 Security Classification Compal Secret Data Compal Electronics, Inc.
0.01U_0402_16V7K Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
2 MADI@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 27 of 59
5 4 3 2 1
5 4 3 2 1
U33 U4 U36 U6
1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
R429 L1 B9 R27 L1 B9 R469 L1 B9 R46 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1 243_0402_1% J9 D1
NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
VGA@ NCZQ1 VSSQ VGA@ NCZQ1 VSSQ VGA@ NCZQ1 VSSQ VGA@ NCZQ1 VSSQ
E2 E2 E2 E2
2
2
VSSQ VSSQ VSSQ VSSQ
E8 E8 E8 E8
VSSQ VSSQ VSSQ VSSQ
F9 F9 F9 F9
VSSQ VSSQ VSSQ VSSQ
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
Pull high for Madison and Park... K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
1
1
ODTB0_1
1
R433 R417 R28 R431
R43 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% R467 R430 R51 R80
B 56_0402_1% VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% B
ODTB0 R42 1 2 VGA@ VGA@ VGA@ VGA@
24 ODTB0
2
2
VGA@ VGA@
2
0_0402_5% VREFCB_A1 VREFDB_Q1 VREFCB_A2 VREFDB_Q2
R49 VREFCB_A3 VREFDB_Q3 VREFCB_A4 VREFDB_Q4
1
1
56_0402_1% 1 1 1 1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ODTB1 R50 1 2 R428 C543 R411 C523 R25 C62 R434 C544 1 1 1 1
24 ODTB1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% R468 C617 R432 C545 R45 C119 R82 C214
0_0402_5% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
ODTB1_1 2 2 2 2 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2
2
2 2 2 2
2
R415 56_0402_1%
1 2 +1.5VSDGPU +1.5VSDGPU
24 CLKB0
VGA@ +1.5VSDGPU +1.5VSDGPU
R414 56_0402_1%
24 CLKB0# 1 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
1U_0402_6.3V6K
C59
1U_0402_6.3V6K
C57
1U_0402_6.3V6K
C58
1U_0402_6.3V6K
C61
1U_0402_6.3V6K
C60
1U_0402_6.3V6K
C529
1U_0402_6.3V6K
C528
1U_0402_6.3V6K
C527
1U_0402_6.3V6K
C526
1U_0402_6.3V6K
C525
VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
1U_0402_6.3V6K
C217
1U_0402_6.3V6K
C212
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C213
1U_0402_6.3V6K
C125
1U_0402_6.3V6K
C612
1U_0402_6.3V6K
C616
1U_0402_6.3V6K
C613
1U_0402_6.3V6K
C615
1U_0402_6.3V6K
C611
1
C532 2 2 2 2 2 2 2 2 2 2
+1.5VSDGPU 2 2 2 2 2 2 2 2 2 2
0.01U_0402_16V7K
2 +1.5VSDGPU
VGA@
R470
56_0402_1%
24 CLKB1 1 VGA@ 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C540
10U_0603_6.3V6M
C73
10U_0603_6.3V6M
C535
10U_0603_6.3V6M
C67
10U_0603_6.3V6M
C195
10U_0603_6.3V6M
C187
10U_0603_6.3V6M
C594
10U_0603_6.3V6M
C601
56_0402_1%
2 2 2 2
24 CLKB1# 1 VGA@ 2
A 2 2 2 2 A
1
C614
0.01U_0402_16V7K
2
VGA@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 28 of 59
5 4 3 2 1
5 4 3 2 1
+LCDVDD
LCD POWER CIRCUIT +3VS C475 SG@
0.1U_0402_16V4Z
+3V +3VS 1 2
W=60mils
1
1
R349 1
NC
300_0603_5% R357 C463 +5VS DGPU_SELECT# 2 4 IGPU_SELECT#
16,17,30 DGPU_SELECT# A Y IGPU_SELECT# 16
100K_0402_5% U23
G
4.7U_0805_10V4Z INVT_PWM 2 8 U27
2 DPST_PWM_1 1A VCC INVTPWM SG@ SG@ 2
5 3 1
3
R353 PWMSEL_1# 2A 1B R365 100K_0402_5%
1 1OE# 2B 6
3
D 1K_0402_5% S Q30 IGPU_PWM_SELECT# 74AHC1G14GW_SOT3535
7 4
Q28 2OE# GND
2 2 1 2
D G G SN74CBTD3306CPWR_TSSOP8 +3VS C474 @ D
S 1 D AO3413L_SOT23-3 SG@ 0.1U_0402_16V4Z
3
1
2N7002E-T1-GE3_SOT23-3 C466 +LCDVDD 1 2
W=60mils
1
D 0.047U_0402_16V7K
1
PCH_ENVDD 2 Q29 2
16 PCH_ENVDD
G UMA@ 1 1
NC
1
G
R351 4.7U_0805_10V4Z 0.1U_0402_16V4Z U26
100K_0402_5% 2 2 @ @
30 DGPU_EDIDSEL_R# 1 2
3
R364 100K_0402_5%
2
74AHC1G14GW_SOT3535
D
091211 ADD R734 Fix CPT 4sec shut down flash issue 1 2
1
ENVDD 2 Q31
22 ENVDD
G 2N7002E-T1-GE3_SOT23-3 R736 R735
1
Pull Low at GPU side S DIS@ 0_0402_5% 0_0402_5% R734 100K_0402_5%
3
@ 2 1
NC
1 SG@ 2 PWMSEL_1# 2 4 IGPU_PWM_SELECT#
17 DGPU_PWMSEL#
2
R361 0_0402_5% A Y
G
Q16,Q17 U22
NEED ADD OPTION COMPONENT SG@
3
5
1
74AHC1G14GW_SOT3535
OE#
P
2 4 DPST_PWM_1 1 UMAO@ 2 INVTPWM
16 DPST_PWM A Y R358 0_0402_5%
G
U24 Reserved for UMA Only
74AHCT1G125GW_SOT353-5
3
2009/12/15 UMA@
C C
change P/N to SA00000U500
VBIOS PWM SETTING
CHANGE TO NORMAL INVT_PWM
37 INVT_PWM 1 DISO@ 2
R356 0_0402_5%
VGA_PNL_PWM 1 @ 2
22 VGA_PNL_PWM
R360 0_0402_5%
1
R355
SM010014520 3000ma 220ohm@100mhz DCR 0.04 10K_0402_5%
+INVPWR_B+
2
W=60mils D1
L31 2 1 B+ 6 3 USB20_CMOS_N8
FBMA-L11-201209-221LMA30T_0805 CH3 CH2
L30 2 1
FBMA-L11-201209-221LMA30T_0805 5 2 2009/8/27 ADD SWITCHABLE
1 1
+3VS Vp Vn SWITCHABLE +3VS
C471
680P_0402_50V7K
C470
68P_0402_50V8J L B1 DIS UMA ONLY
1
USB20_CMOS_P8 4 1 SEL1 TXOUT0+ 0_0402_5% 2 UMAO@1
UMAO@ R416 PCH_TXOUT0+
2 2 CH4 CH1 TXOUT0- PCH_TXOUT0- PCH_TXOUT0+ 16
R15 0_0402_5% 2 UMAO@1 R412
SEL2 PCH_TXOUT0- 16
CM1293-04SO_SOT23-6 H B2 UMA 0_0603_5%
@ SG@ TXOUT1+ 0_0402_5% 2 UMAO@1 R405 PCH_TXOUT1+
TXOUT1- PCH_TXOUT1- PCH_TXOUT1+ 16
0_0402_5% 2 UMAO@1 R410
LCD/LED PANEL Conn. PCH_TXOUT1- 16
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
TS3DV520ERHUR with 1 SEL pin U3
4 +3VS_SWITCH TXOUT2+ 0_0402_5% 2 UMAO@1 R401 PCH_TXOUT2+
VCC TXOUT2- PCH_TXOUT2- PCH_TXOUT2+ 16
W=60mils 10 1 1 1 0_0402_5% 2 UMAO@1 R399
B VCC PCH_TXOUT2- 16 B
JLVDS1 Place closed to JLVDS1 VGA_TXCLK+ 48 18
+LCDVDD VGA_TXCLK- 0B1 VCC TXCLK+ 0_0402_5% 2 UMAO@1 R393 PCH_TXCLK+
1 1 +INVPWR_B+ 47 1B1 VCC 27 PCH_TXCLK+ 16
41 2 +3VS VGA_TXOUT2- 43 38 SG@ SG@ SG@ TXCLK- 0_0402_5% 2 UMAO@
UMAO@1 R396 PCH_TXCLK-
G1 2 VGA_TXOUT2+ 2B1 VCC 2 2 2 PCH_TXCLK- 16
42 3 R729 42 50
G2 3 +LCDVDD_R @ VGA_TXOUT1+ 3B1 VCC
43 4 2 1 0_0402_5% +LCDVDD 37 56
G3 4 VGA_TXOUT1- 4B1 VCC C63 C54 C66 I2CC_SCL 0_0402_5% 2 UMAO@1 R418 PCH_LCD_CLK
44 5 +LCDVDD 1 1 1 36 PCH_LCD_CLK 16
G4 5 C464 C461 C458 VGA_TXOUT0- 5B1 TXCLK+ I2CC_SDA 0_0402_5% 2 UMAO@1 R420 PCH_LCD_DATA
45
G5 6
6 W=60mils VGA_TXOUT0+
32
6B1 A0
2
TXCLK-
PCH_LCD_DATA 16
46 7 +3VS 31 3
G6 7 INVTPWM 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z VGA_LCD_CLK 7B1 A1 TXOUT2-
8
8
2 2 2
22
8B1 A2
7 5/4 PCH_LCD_CLK& PCH_LCD_DATA
9 DISPOFF# VGA_LCD_DATA 23 8 TXOUT2+ +3VS
9 I2CC_SCL 9B1 A3 TXOUT1+
Pull high 2.2K change to 4.7K
10 10 A4 11
11 I2CC_SDA 12 TXOUT1- R29 1 UMA@ 2 4.7K_0402_5% PCH_LCD_CLK
11 A5 TXOUT0-
12 12 DAC_BRIG 37 A6 14
13 TXOUT0- 15 TXOUT0+ R32 1 UMA@ 2 4.7K_0402_5% PCH_LCD_DATA
13 TXOUT0+ DAC_BRIG PCH_TXCLK+ A7 I2CC_SCL
14 14 1 2 46 0B2 A8 19
15 C467 220P_0402_50V7K PCH_TXCLK- 45 20 I2CC_SDA
15 TXOUT1- INVTPWM PCH_TXOUT2- 1B2 A9
16 1 2 41
16 TXOUT1+ C468 220P_0402_50V7K PCH_TXOUT2+ 2B2 DGPU_SELECT#
17 40 17
17
18
19
18
19
20
TXOUT2-
TXOUT2+
DISPOFF# 1
C473
2
220P_0402_50V7K
PCH_TXOUT1+
PCH_TXOUT1-
PCH_TXOUT0-
35
34
30
3B2
4B2
5B2 GND
SEL
1
6 TXOUT0+
Discrete ONLY
0_0402_5% 2 DISO@ 1 R26 VGA_TXOUT0+
20 6B2 GND VGA_TXOUT0+ 22
21 PCH_TXOUT0+ 29 9 TXOUT0- 0_0402_5% 2 DISO@ 1 R24 VGA_TXOUT0-
21 TXCLK- PCH_LCD_CLK 7B2 GND VGA_TXOUT0- 22
22 25 13
22 TXCLK+ DISPOFF# 0_0402_5% 2 PCH_LCD_DATA 8B2 GND TXOUT1+ VGA_TXOUT1+
23 23 1 R363 BKOFF# 37 26 9B2 GND 16 0_0402_5% 2 DISO@ 1 R22
VGA_TXOUT1+ 22
24 21 TXOUT1- 0_0402_5% 2 DISO@ 1 R23 VGA_TXOUT1-
24 GND VGA_TXOUT1- 22
25 10K_0402_5% 2 1 R362 DGPU_EDIDSEL_R# 54 24
25 SEL2 GND TXOUT2+ 0_0402_5% 2 DISO@ 1 R21 VGA_TXOUT2+
26 26 GND 28 VGA_TXOUT2+ 22
27 R730 2 @ 1 0_0402_5% 33 TXOUT2- 0_0402_5% 2 DISO@ 1 R20 VGA_TXOUT2-
27 LOCAL_DIM 37 GND VGA_TXOUT2- 22
28 52 39
28 NC GND TXCLK+ 0_0402_5% 2 DISO@ 1 R18 VGA_TXCLK+
29
29 1208 Add Panel new feature 5
NC GND
44 VGA_TXCLK+ 22
30 R731 2 @ 1 0_0402_5% 51 49 TXCLK- 0_0402_5% 2 DISO@ 1 R19 VGA_TXCLK-
30 COLOR_ENG_EN 37 NC GND VGA_TXCLK- 22
31 31 GND 53
A A
32 57 55
32 Thermal_GND GND I2CC_SCL 0_0402_5% 2 DISO@ 1 R419 VGA_LCD_CLK
33 33 VGA_LCD_CLK 23
34 PI3LVD400ZFEX_TQFN56_11X5 I2CC_SDA 0_0402_5% 2 DISO@ 1 R421 VGA_LCD_DATA
34 VGA_LCD_DATA 23
35
35 1109 RF request SG@
36 36
37
37 +3VS PI3LVD400ZFE with 2 SEL pin
38 USB20_CMOS_N8 R1 2 1 0_0402_5%
38 USB20_CMOS_P8 USB20_N8 17
39 R2 2 1 0_0402_5%
39
40 40 1 1
USB20_P8 17 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
IPEX_20143-040E-20F C805 C806
CONN@ 22P_0402_50V8J 22P_0402_50V8J THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
@ 2 2
@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Wednesday, January 06, 2010 Sheet 29 of 59
5 4 3 2 1
A B C D E
1
2 1 1 2
CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF
1
C171
3
0.1U_0402_16V4Z
2
SM010005220 600ma 80ohm@100mhz DCR 0.25 +3VS
1 1
1
1 1 1 1 1 1 1 1 1 3
R466 R464 R446 C607 C592 C567 C618 C598 C590 9
C603 C593 C569 14 G 16
150_0402_1% 150_0402_1% UMAO@ UMAO@ UMAO@ UMAO@ UMAO@ UMAO@ 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4 17
2 2 2 2 2 2 G
UMAO@ 2 UMAO@ 2 2 UMAO@ 10
2
10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 15
22P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J 22P_0402_50V8J Change to 12pf for Discrete C110
C-H_13-12201513CP
100P_0402_50V8J CONN@
2
Change to 15pf for Discrete SM010012010 300ma 120ohm@100mhz DCR 0.4 CRT_DET# 18
1 2 CRT_HSYNC_2
+CRT_VCC L2 MBC1608121YZF_0603 DSUB_12
2
C194 1 2 0.1U_0402_16V4Z R67 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1 R41
L1 MBC1608121YZF_0603 1 1 100K_0402_5%
@
1
U7 C178 C164 DSUB_15
1
2 10P_0402_50V8J 10P_0402_50V8J C208 2 2
OE#
P
CRT_HSYNC 2 4 CRT_HSYNC_1 2 2 68P_0402_50V8J 1
A Y
G
C126 +CRT_VCC
74AHCT1G125GW_SOT353-5 68P_0402_50V8J
3
2
+CRT_VCC
C111 1 2 0.1U_0402_16V4Z
1
U5
OE#
P
CRT_VSYNC 2 4 CRT_VSYNC_1
A Y
G
+CRT_VCC
74AHCT1G125GW_SOT353-5
3
+3VS +3VS
SWITCHABLE
1
0.1U_0402_16V4Z R48 R78
4.7K_0402_5% 4.7K_0402_5%
2009/08/27 1
C273
1
C290
1
C271
1
C280
SG@ SG@ SG@ SG@
UMA only
2
2
G
0.1U_0402_16V4Z
2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z CRT_DDC_DATA 3 1 DSUB_12
PCH_CRT_R R536 2 UMAO@ 1 0_0402_5% CRT_R
D
16 PCH_CRT_R
Q3
2
G
PCH_CRT_G R534 2 UMAO@ 1 0_0402_5% CRT_G 2N7002E-T1-GE3_SOT23-3
16 PCH_CRT_G
+3VS PCH_CRT_B R532 2 UMAO@ 1 0_0402_5% CRT_B CRT_DDC_CLK 3 1 DSUB_15
16 PCH_CRT_B
D
3 U10 PCH_CRT_HSYNC R530 2 UMAO@ 1 0_0402_5% CRT_HSYNC Q2 3
16 PCH_CRT_HSYNC
4 1 CRT_R 2N7002E-T1-GE3_SOT23-3
VDD A0 CRT_G PCH_CRT_VSYNC R528 2 UMAO@1
UMAO@ 0_0402_5% CRT_VSYNC
16 2 16 PCH_CRT_VSYNC
VDD A1 CRT_B
23 VDD A2 5
29 6 CRT_HSYNC 16 PCH_CRT_CLK PCH_CRT_CLK R544 2 UMAO@ 1 0_0402_5% CRT_DDC_CLK
VDD A3 CRT_VSYNC
32 7
VDD A4 PCH_CRT_DATA R543 2 UMAO@ 1 0_0402_5% CRT_DDC_DATA
VGA_CRT_R 16 PCH_CRT_DATA
27
0B1 SEL1
8 DGPU_SELECT# 16,17,29 PCH DDC PU 2.2K on Page 17
VGA_CRT_G 25
VGA_CRT_B 1B1
22 2B1
VGA_CRT_HSYNC 20 9 CRT_DDC_CLK
VGA_CRT_VSYNC 3B1 A5 CRT_DDC_DATA
18 10
VGA_DDC_CLK 4B1 A6
12 5B1
VGA_DDC_DATA 14 30
6B1 SEL2 DGPU_EDIDSEL_R# 29
PCH_CRT_R 26
PCH_CRT_G 0B2
PCH_CRT_B
24
21
1B2
3
Discrete only
PCH_CRT_HSYNC 2B2 GND
19 11
PCH_CRT_VSYNC 3B2 GND VGA_CRT_R R537 2 DISO@ 1 0_0402_5% CRT_R
17 28 23 VGA_CRT_R
PCH_CRT_CLK 4B2 GND
13 5B2 GND 31
PCH_CRT_DATA 15 33 VGA_CRT_G R535 2 DISO@ 1 0_0402_5% CRT_G
6B2 GPAD 23 VGA_CRT_G
PI3V712-AZLEX_TQFN32_6X3~D VGA_CRT_B R533 2 DISO@ 1 0_0402_5% CRT_B
23 VGA_CRT_B
SG@
VGA_CRT_HSYNC R531 2 DISO@ 1 0_0402_5% CRT_HSYNC
23 VGA_CRT_HSYNC
VGA_CRT_VSYNC R529 2 DISO@ 1 0_0402_5% CRT_VSYNC
23 VGA_CRT_VSYNC
L B1 DIS VGA_DDC_CLK R527 2 DISO@ 1 0_0402_5% CRT_DDC_CLK
23 VGA_DDC_CLK
4 VGA_DDC_DATA R526 2 DISO@ 1 0_0402_5% CRT_DDC_DATA 4
23 VGA_DDC_DATA
H B2 UMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 30 of 59
A B C D E
5 4 3 2 1
+3VS
+3VS
HDMI connector
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R590 1 2 0_0603_5% W=40mils R616
1 1 1 1 1 1 1 HDMI@ 10K_0402_5% JHDMI1
C727 C725 C730 C731 C720 C721 C409 +HDMI_5V_OUT HDMI_HPD 19
UMAHD@ HP_DET
D21 F2 +HDMI_5V_OUT 18
2
UMAHD@ UMAHD@ UMAHD@ UMAHD@ UMAHD@ UMAHD@ UMAHD@ +5V
+5VS 2 1 +HDMI_5V 1 2 OE# 17 DDC/CEC_GND
2
0.1U_0402_16V4Z 2 2 2 2 2 2 @ HDMI@ HDMI_SDATA
1 D 16 SDA
1
CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF HDMI_SCLK 15
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C707 Q43 HDMI_HPD SCL
2 14 Reserved
D HDMI@ UMAHD@ G 1 13 D
CEC
1
0.1U_0402_16V4Z 2 S C410 HDMI_R_CK- 12 20
3
R256 HDMI@ CK- GND
11 CK_shield GND 21
2N7002E-T1-GE3_SOT23-3 UMAHD@ 0.1U_0402_16V4Z HDMI_R_CK+ 10 22
100K_0402_5% 2 HDMI_R_D0- CK+ GND
9 D0- GND 23
U45 8
2
HDMI_R_D0+ D0_shield
Option UMAHD@ VGAHD@ HDMI@ @ SG@ 7 D0+
HDMI_R_D1- 6
+3VS OE# @ D1-
UMA V X V X X OE# 25 1 2 5 D1_shield
R618 0_0402_5% HDMI@ HDMI_R_D1+ 4
D23 CH751H-40PT_SOD323-2 HDMI_R_D2- D1+
VGA X V V X X 2 VCC3V 3 D2-
11 28 HDMI_SCLK R625 1 HDMI@ 2 2.2K_0402_5%1 2 +HDMI_5V_OUT 2
VCC3V SCL_SINK HDMI_R_D2+ D2_shield
SG X V V X V 15 VCC3V 1 D2+
21 29 HDMI_SDATA R627 1 HDMI@ 2 2.2K_0402_5%1 2
VCC3V SDA_SINK SUYIN_100042MR019S153ZL
NO HDMI X X X X X 26 VCC3V
33 D24 CH751H-40PT_SOD323-2 CONN@
VCC3V HDMI_HPD HDMI@
40 VCC3V HPD_SINK 30
46 VCC3V
32 R629 1 UMAHD@
2 2.2K_0402_5% +3VS
R269 @ DDC_EN
+3VS 1 2 2.2K_0402_5% R637 1 UMAHD@2 2.2K_0402_5% +3VS
R253 1 @ 2 2.2K_0402_5% R638 1 UMAHD@2 2.2K_0402_5%
R273 1 UMAHD@2 2.2K_0402_5% CG_0 3 34 EQ_S0 R635 1 @ 2 2.2K_0402_5% SM070001310 400ma 90ohm@100mhz DCR 0.3
R252 CG_0 EQ_0
1 UMAHD@2 2.2K_0402_5% CG_1 4 CG_1 EQ_1 35 EQ_S1 R666 1 @ 2 2.2K_0402_5%
HDMI_TX2+ 13 48 1 2
OUT_D4+ IN_D4+ PCH_TMDS_D2 16 1 2
CG0 CG1 CG2 Swing Pre-amp Slew-rate HDMI_TX2- 14 47 L23
OUT_D4- IN_D4- PCH_TMDS_D2# 16
W CM-2012-900T_0805
0 0 0 450 0 0 HDMI_TX1+ 16 45 @ 4 3
OUT_D3+ IN_D3+ PCH_TMDS_D1 16 4 3
HDMI_TX1- 17 44
0 0 1 420 0 -3db OUT_D3- IN_D3- PCH_TMDS_D1# 16
HDMI_TX0- R168 1 HDMI@ 2 0_0402_5% HDMI_R_D0-
0 1 0 450 0 -3db (default) HDMI_CLK+ 19 OUT_D2+ IN_D2+ 42 PCH_TMDS_CK 16
HDMI_CLK- 20 41
0 1 1 460 0 -4db OUT_D2- IN_D2- PCH_TMDS_CK# 16
HDMI_TX1+ R183 1 HDMI@ 2 0_0402_5% HDMI_R_D1+
1 0 0 340 0 0 HDMI_TX0+ 22 39
OUT_D1+ IN_D1+ PCH_TMDS_D0 16
0 HDMI_TX0- 23 38 1 2
1 0 1 400 2db OUT_D1- IN_D1- PCH_TMDS_D0# 16
L25 1 2
1 1 0 400 2db 0 W CM-2012-900T_0805
@ 4 3
1 1 1 420 0 0 1
4 3
GND HDMI_TX1- R182
5 GND 1 HDMI@ 2 0_0402_5% HDMI_R_D1-
12 GND GND 49
18 GND
+3VS R228 1 @ 2 10K_0402_5% 24 HDMI_TX2+ R190 1 HDMI@ 2 0_0402_5% HDMI_R_D2+
GND
27 GND
16 PCH_DPB_HPD 1 UMAHD@2 HPD_SOURCE 31 GND 1 1 2 2
B R230 0_0402_5% L26 B
36 GND
37 W CM-2012-900T_0805
@ GND @
1 2 43 GND 4 4 3 3
R234 10K_0402_5% ASM1442 PN: SA00003GT00
HDMI_TX2- R188 1 HDMI@ 2 0_0402_5% HDMI_R_D2-
ASM1442T_QFN48_7X7 UMAHD@
1
G
VGAHD@ E
G
3
23 VGA_HDMI_DET 1 2 +3VSDGPU 2
23 VGA_HDMI_SCLK 3 1 HDMI_SCLK R714 18 DGPU_HPD_INT# 1 3 G
1
1 S
D
3
2
G
A
Q12 2N7002E-T1-GE3_SOT23-3 VGAHD@ R715 Q44 VGAHD@ A
C804 10K_0402_5% 2N7002E-T1-GE3_SOT23-3
23 VGA_HDMI_SDATA 3 1 HDMI_SDATA 12P_0402_50V8J VGAHD@ SG@
VGAHD@ 2 @ 2N7002E-T1-GE3_SOT23-3
S
1
2
Q13 2N7002E-T1-GE3_SOT23-3
C803
Place closed to JHDMI1 12P_0402_50V8J
2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
DDC to HDMI CONN HDMI Level Shift & Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 31 of 59
5 4 3 2 1
5 4 3 2 1
D D
1 GND
13 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C753 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 C751 1 SATA_PTX_C_DRX_N0 A+
13 SATA_PTX_DRX_N0 2 0.01U_0402_16V7K 3 A-
4
SATA_DTX_C_PRX_N0 C749 1 SATA_DTX_PRX_N0 GND
2 0.01U_0402_16V7K 5 B-
13 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C747 1 SATA_DTX_PRX_P0
2 0.01U_0402_16V7K 6
13 SATA_DTX_C_PRX_P0 B+
7
+3VS GND
1 +3VS 8
C745 V33
9 V33
10
0.1U_0402_16V4Z V33
11
2 GND
12
GND
13 GND
R669 1 2 0_0805_5% +5VS_HDD1 14
+5VS V5
100mils 15
V5
16 V5
17
10U_0805_10V4Z 0.1U_0402_16V4Z GND
18
Reserved
19 GND
1 1 1 1 20 V12
C735 C734 C733 C732 21 24
V12 GND
22 23
C V12 GND C
2 2 2 2
SANTA_192301-1
1U_0402_6.3V4Z 1000P_0402_50V7K CONN@
1
C687 1 SATA_PTX_C_DRX_P1 GND
13 SATA_PTX_DRX_P1 2 0.01U_0402_16V7K 2
C685 1 SATA_PTX_C_DRX_N1 A+
13 SATA_PTX_DRX_N1 2 0.01U_0402_16V7K 3
B A- B
4 GND
C680 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 5
13 SATA_DTX_C_PRX_N1 SATA_DTX_PRX_P1 B-
C678 1 2 0.01U_0402_16V7K 6
13 SATA_DTX_C_PRX_P1 B+
7 GND
R516 1 @ 2 1K_0402_1% 8
DP
9
R105 1 +5VS_ODD +5V
+5VS 2 0_0805_5% 10 17
+5V GND
80mils 11 MD GND 16
12 GND GND 15
13 14
GND GND
10U_0805_10V4Z 0.1U_0402_16V4Z
OCTEK_SLS-13SB1G_RV
1 1 1 1 CONN@
C642 C654 C653 C643
2 2 2 2
Place caps. near ODD CONN.
1U_0402_6.3V4Z 1000P_0402_50V7K
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 32 of 59
5 4 3 2 1
5 4 3 2 1
+3V_LAN
60mil
+3VALW R599 1 2
0_1206_5%
1 1
C716 C715
4.7U_0603_6.3V6K
D U39 2 2 D
35 LAN_MIDI2-
TRD2_N LAN_MIDI2- 34 +3V_LAN
34 LAN_MIDI2+
+LAN_GPHYPLLVDDL TRD2_P LAN_MIDI2+ 34
24 C322 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1- @
TRD1_N LAN_MIDI1- 34
2
32 LAN_MIDI1+ R195 R193
TRD1_P LAN_MIDI1+ 34
1K_0402_1% 1K_0402_1%
+LAN_PCIEPLLVDD 18
PCIE_PLLVDDL @
29 LAN_MIDI0- U12 @
LAN_MIDI0- 34
1
TRD0_N
21 PCIE_PLLVDDL 8 VCC A0 1
28 LAN_MIDI0+ 7 2
TRD0_P LAN_MIDI0+ 34 SPROM_CLK WP A1
6 3
C SPROM_DOUT SCL NC C
5 SDA GND 4
AT24C02_SO8
2
LINKLED# 48 2 1 LAN_LINK# 34
R595 R196 R194
0.1U_0402_16V7K 47 0_0402_5% 1K_0402_1% 1K_0402_1%
PCIE_DTX_PRX_P1 SPD100LED#
14 PCIE_DTX_C_PRX_P1 1 2 C699 17 PCIE_TXD_P @
1 2 C700 PCIE_DTX_PRX_N1 16 46
14 PCIE_DTX_C_PRX_N1
1
PCIE_TXD_N SPD1000LED#
22 PCIE_RXD_P
0.1U_0402_16V7K 23 45 2 1
LAN_PME# PCIE_RXD_N TRAFFICLED# R594 LAN_ACTIVITY# 34
14 PCIE_PTX_C_DRX_P1 4 WAKE# SM010005500 500ma 600ohm@100mhz DCR 0.38
LAN_RESET# 2 0_0402_5% 20mil
14 PCIE_PTX_C_DRX_N1 REST#
20 L22
R592 1 @ PCIE_REFCLK_P +LAN_XTALVDDH
15,35 PCH_PCIE_WAKE# 2 0_0402_5% 19 1 2 +3V_LAN
R589 1 PCIE_REFCLK_N
37 EC_PME# 2 0_0402_5% 1 BLM18AG601SN1D_2P
+3V_LAN R587 1 2 4.7K_0402_5% C301
0.1U_0402_16V4Z
R597 1 2 0_0402_5% 20mil
5,17,21,37 PLT_RST# 2
5 L64
MODE +LAN_BIASVDDH
14 CLK_PCIE_LAN 1 2
1 BLM18AG601SN1D_2P
14 CLK_PCIE_LAN#
C703
0.1U_0402_16V4Z
SPROM_DOUT
20mil 2
43
EEDATA L66
44 SPROM_CLK +LAN_AVDDH 1 2
R175 1 EECLK
+3VS 2 1K_0402_5% 40 1 1 BLM18AG601SN1D_2P
VMAIN_PRSINT C712 C706
R596 1 2 10K_0402_5% 1
LOW_PWR 0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil L65 2 2
B +1.2V_LAN_OUT B
SR_LX 11 1 2 +1.2V_LAN
4.7UH_PG031B-4R7MS_1.1A_20% SM010005500 500ma 600ohm@100mhz DCR 0.38
LAN_XTALO_R 13 8 1 1 20mil
XTALO SR_VFB C708 L63
LAN_XTALI 12 C710 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z BLM18AG601SN1D_2P
2 2
1 1
C302 C695
R575
1 2 LAN_RDAC 26 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
RDAC 2 2
SR_VDDP 10 +3V_LAN
1.24K_0402_1% 1 1
9 C318 C311
SR_VDD
20mil
L62
3 2 2 +LAN_GPHYPLLVDDL 1 2
14 LAN_CLKREQ# CLKREQ# +1.2V_LAN
4.7U_0603_6.3V6K 0.1U_0402_16V4Z BLM18AG601SN1D_2P
7 1 1
NC C698 C696
PAD
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
49
BCM57780A0KMLG_QFN48_7X7
20mil
L21
+LAN_AVDDL 1 2 +1.2V_LAN
BLM18AG601SN1D_2P
1 1
LAN_XTALI C709 C312
R571
200_0402_1%
2
Y3
1 2 LAN_XTALO Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title
25MHZ_20PF_7A25000012
C704 C702
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM57780
27P_0402_50V8J 27P_0402_50V8J Size Document Number Rev
2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 33 of 59
5 4 3 2 1
5 4 3 2 1
LAN Connector
D D
T16
1 TCT1 MCT1 24
33 LAN_MIDI0+ LAN_MIDI0+ 2 23 RJ45_MIDI0+
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0-
33 LAN_MIDI0- 3 TD1- MX1- 22 +3V_LAN 2 1
R518 1K_0402_5% 1
4 TCT2 MCT2 21
33 LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ 220P_0402_50V7K
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- LAN_ACTIVITY# C663
33 LAN_MIDI1- 6 TD2- MX2- 19
LAN_LINK# 2 C656 68P_0402_50V8J
JRJ45
7 18 @
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+
33 LAN_MIDI2+ 8 TD3+ MX3+ 17 2 1 9 Green LED+
33 LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2-
TD3- MX3- LAN_LINK#
33 LAN_LINK# 10 Green LED-
2
10 TCT4 MCT4 15
33 LAN_MIDI3+ LAN_MIDI3+ 11 14 RJ45_MIDI3+ D22 RJ45_MIDI0+ 1 14
LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR1+ SHLD1
33 LAN_MIDI3- 12 TD4- MX4- 13 PJDLC05C_SOT23-3 SHLD2 13
@ RJ45_MIDI0- 2 PR1-
RJ45_MIDI1+ 3 PR2+
1
350UH_IH-037-2
RJ45_MIDI2+ 4
C R549 R541 PR3+ C
1 1 1 1
1
C671 C681 C686 C690 75_0402_1% 75_0402_1% RJ45_MIDI2- 5 PR3-
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z RJ45_MIDI1- 6
2 2 2 2 PR2-
R525 R522 RJ45_MIDI3+ 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% PR4+
RJ45_MIDI3- 8
2
PR4-
RJ45_GND 2 1 11
+3V_LAN Yellow LED+
Place close to TCT pin R140 1K_0402_5% 1
40mil LAN_ACTIVITY# 12
220P_0402_50V7K 33 LAN_ACTIVITY# Yellow LED-
C297 68P_0402_50V8J
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 2 SANTA_130451-K
2 1
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 @ CONN@
C292
0.1U_0402_16V4Z
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 34 of 59
5 4 3 2 1
A B C D E
+3VS 2
R302
1
0_1206_5%
+3VS_W LAN For Wireless LAN
60mil
+3VS_W LAN +1.5VS +3VS_W LAN
1 1 1 1 1 1
C440 C423 C452 C441 C434 C442
17 17 18 18
19 20 W L_OFF#
19 20 W L_OFF# 37
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# 17
14 PCIE_DTX_C_PRX_N2 23 24 R303 1 2 0_0603_5% +3VS
23 24 R299 1 @
14 PCIE_DTX_C_PRX_P2 25 25 26 26 2 0_0603_5% +3V
27 28 0_0402_5%
27 28 MINI1_SMBCLK R292 1 @
29 29 30 30 2 PCH_SMBCLK 12,14,21
31 32 MINI1_SMBDATA 1 @ 2 PCH_SMBDATA 12,14,21
14 PCIE_PTX_C_DRX_N2 31 32
33 34 R288 0_0402_5%
14 PCIE_PTX_C_DRX_P2 33 34
35 35 36 36 USB20_N12 17
37 37 38 38 USB20_P12 17
+3VS_W LAN 39 39 40 40
41 42 (WWAN_LED#) R291 1 2 0_0402_5%
41 42
43 43 44 44 (WLAN_LED#) MINI1_LED# 37
2 45 46 2
0_0402_5% 45 46
47 47 48 48 (9~16mA)
1
R280 1 2 E51TXD_P80DATA1_R 49 50
37 E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52 R285
37 E51RXD_P80CLK 51 52
100K_0402_5%
G1
G2
G3
G3
2
ACES_88910-5204
53
54
55
56
CONN@
+3VS_W LAN
4 mm High
+3VS_W W AN
1
C460
3G@
2
0.1U_0402_16V4Z For 3G / GPS
3 +3VS_W W AN 3
To 3G Module Connect
2
+3VS_W W AN R350
+3VS +3VS_W W AN (Port 9) 100K_0402_5%
Peak: 2.75A JP4
1
Normal: 1.1A 1
1
2 2
3 W W AN_OFF#
3 W W AN_OFF# 37
1 3G@ 2 4 4 W W AN_LED# 37
R352 0_1206_5% 5
5
1 1 1 6 6 USB20_N13 17
7 7 USB20_P13 17
C465 + C801 C173 8
@ 3G@ 3G@ 8
9 9 USB20_N10 17
150U_B2_6.3VM_R35M 2 2 10U_0603_6.3V6M
10 10 USB20_P10 17
2
GND 11
47P_0402_50V8J 12
GND
1109 RF request ACES_87036-1001-CP
Close to WWAN CONN CONN@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & TV-Tuner)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Monday, January 04, 2010 Sheet 35 of 59
A B C D E
A B C D E
+3V
+3V
+5VALW
1
+USB_VCCB
+5VALW
1
+USB_VCCA U46
U17 1 8 R681
R250 GND VOUT 100K_0402_5%
1 GND VOUT 8 2 VIN VOUT 7
2 7 100K_0402_5% 3 6
2
VIN VOUT VIN VOUT
3 6 1 4 5 1 2 USB_OC#0 17
2
VIN VOUT C736 EN FLG R680
1 4 EN FLG 5 1 2 USB_OC#2 17
C424 R251 RT9715BGS_SO8 10K_0402_5% 1
RT9715BGS_SO8 10K_0402_5% 1 4.7U_0805_10V4Z C744
4.7U_0805_10V4Z C408 2
1 1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
2 SYSON#
SYSON#
43 SYSON#
1
5 2 +USB_VCCB
+USB_VCCA Vp Vn 1
C726 + C728
JUSB2
220U_6.3V_M_R17
2009/08/25 Update Footprint(follow NAL00)
1 W=100mils
2
USB20_P1_1 2 1
4 CH4 CH1 1 2 2
470P_0402_50V7K 3
CM1293-04SO_SOT23-6 USB Conn. 3
4 4
5
R667 1 @ 5
2 0_0402_5% (Port 1) 6 6 USB20_N0
USB20_N0 17
7 USB20_P0
7 USB20_P0 17
JUSB1 8
USB20_N1 8 USB20_N2
17 USB20_N1 1 1 2 2 1 VBUS 9 9 USB20_N2 17
L68 USB20_N1_1 2 10 USB20_P2
2 USB20_P1_1 D- 10 USB20_P2 17 2
3 D+ 13 GND 11 11
USB20_P1 4 3 4 14 12
17 USB20_P1 4 3 GND GND 12
5 GND
OCE2012120YZF_0805 6
@ GND ACES_85201-1205N
1 2 7 GND
R668 0_0402_5% 8 CONN@
GND
09/12/28 ADD USB common mode choke SUYIN_020133GB004M51PZR
S COM FI_ SUPERWORLD OCE2012120YZF CONN@
3 3
+3VALW +3VS
3
1 S 2
7 7
BT_ON# 1 BT@ 2 2 Q51 6
37 BT_ON# G 6 USB20_P11 17
R706 BT@ 5
Card Reader Conn. 10K_0402_5% D AO3413L_SOT23-3 5
4 (WLAN_BT_DATA)
USB20_N11 17
1
4 (WLAN_BT_CLK)
2 3 3
C788 W=40mils 2
BT@ 2
+BT_VCC 9 GND 1 1
+3VS 0.1U_0402_16V4Z
BT Wire Cable Note:
1
C445 1 ACES_87213-0800G
GND 10 1
GND 9 4.7U_0805_10V4Z C796
BT@
C795
BT@
R713
300_0603_5%
CONN@ Pin 3, Pin 4 NC
8 8 1 2
7 4.7U_0805_10V4Z BT@
7 2
6 5IN1_LED# 38
2
6 0.1U_0402_16V4Z
5 5
4 4
3 USB20_N9
3 USB20_N9 17 D
1
2 USB20_P9
2 USB20_P9 17
1 2 Q50
1 G 2N7002E-T1-GE3_SOT23-3
JCR1 S BT@
3
4 4
ACES_85201-08051
CONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB / BT / USBB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 36 of 59
A B C D E
5 4 3 2 1
ECAGND
ACES_85205-0400
@
D
+3VALW Place on MiniCard D
JP5
111
125
22
33
96
67
U32 1 1
9
2 E51RXD_P80CLK
2 E51TXD_P80DATA
3
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
3
4 4
ACES_85205-0400
EC_GA20 1 21 @
18 EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# +3VALW
18 EC_KBRST#
SERIRQ
2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 40 Board ID definition,
1109 RF request 13 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 ME_OVERRIDE 13
13 LPC_FRAME#
LPC_FRAME# 4 27 ACOFF
ACOFF 47,48
Please see page 3.
LFRAME# ACOFF/FANPWM2/GPIO13
2
C516 LPC_AD3 5 2 1 ECAGND
13 LPC_AD3 LAD3
22P_0402_50V8J LPC_AD2 7 PWM Output C491 0.01U_0402_16V7K R389
13 LPC_AD2 LAD2
2 1 R403 2 1 47_0402_5% 13 LPC_AD1
LPC_AD1 8 LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP
BATT_TEMP 45 Ra 100K_0402_5%
LPC_AD0 BATT_OVP
13 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 47
65 ADP_I 47
1
ADP_I/AD2/GPIO3A AD_BID0 AD_BID0
17 CLK_PCI_LPC 12 PCICLK AD Input AD3/GPIO3B 66
13 75 EC_PROJECTID
5,17,21,33 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
1
+3VALW R375 2 1 47K_0402_5% EC_RST# 37 76 1
EC_SCI# ECRST# SELIO2#/AD5/GPIO43 R382 C496
18 EC_SCI# 20 SCI#/GPIO0E
C487 2 1 0.1U_0402_16V4Z
15 PM_CLKRUN# 38 CLKRUN#/GPIO1D Rb 18K_0402_5%
68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 29 2
70 EN_DFAN1
EN_DFAN1 42
2
EN_DFAN1/DA1/GPIO3D IREF 0.1U_0402_16V4Z
+3VALW
DA Output IREF/DA2/GPIO3E 71 IREF 47
KSI0 55 72 CALIBRATE#
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 47
KSI1 56 KSI1/GPIO31
1 2 EC_SMB_CK1 KSI2 57 KSI2/GPIO32
+5VS
R392 2.2K_0402_5% KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 41
C 1 2 EC_SMB_DA1 KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 GFX_CORE_PW RGD
GFX_CORE_PW RGD 53
TP_CLK 2 1 C
R395 2.2K_0402_5% KSI5 60 85 W W AN_LED# R404 4.7K_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C W W AN_LED# 35
KSI6 61 PS2 Interface 86 TP_DATA 2 1
KSI6/GPIO36 PSDAT2/GPIO4D
1 2 LID_SW # KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK
TP_CLK 38
R408 4.7K_0402_5%
R422 100K_0402_5% KSO0 39 88 TP_DATA +3VALW
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 38
KSO1 40 KSO1/GPIO21
1 2 KSO1 KSO2 41 KSO2/GPIO22
3S/4S# 2 1
R374 47K_0402_5% KSO3 42 97 3S/4S# R423 100K_0402_5%
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 47
1 2 KSO2 KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 65W /90W #
65W /90W # 47
65W /90W # 2 1
R373 47K_0402_5% KSO5 SBPW R_EN R424 100K_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
SBPW R_EN 43
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 38
1 @ 2 EC_PME# KSO7 46 SPI Device Interface
R426 10K_0402_5% KSO8 KSO7/GPIO27
47 KSO8/GPIO28 PCH_TEMP_ALERT# Pull high at Page 18 (PCH side)
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 38 +3VALW
KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 38
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 38
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 38
1
KSO13 52
KSO14 KSO13/GPIO2D R394
53 KSO14/GPIO2E
KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 W W AN_OFF#
W W AN_OFF# 35 Ra 100K_0402_5%
KSO16 81 74 PCH_TEMP_ALERT# @
KSO16/GPIO48 CIR_RLC_TX/GPIO41 PCH_TEMP_ALERT# 18,21
KSO17 82 89 FSTCHG
FSTCHG 47
2
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# EC_PROJECTID
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 38
HIGH LOW 91 3G_LED# (CAPS_LED#)
CAPS_LED#/GPIO53 3G_LED# 38
1
EC_PROJECTID EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# 1
45 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# 38
EC_SMB_DA1 78 93 PW R_LED R397
45 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_LED 38
14,23 EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON 43,50 Rb 0_0402_5% C511
EC_SMB_DA2 80 121 VR_ON 0.1U_0402_16V4Z
14,23 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 39,54 2
127 ACIN @
ACIN 38,43,44
2
B AC_IN/GPIO59 B
4
R400 2 1 EC_SMB_DA2 E51TXD_P80DATA 30
2.2K_0402_5% E51RXD_P80CLK EC_TX/GPIO16 15P_0402_50V8J X1 15P_0402_50V8J
31 110
OSC
OSC
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# 15 2 2
ON/OFF 32 112 ENBKL
39 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 16,23
38 PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD 40
R402 1 2 GFX_CORE_PW RGD W LAN_LED# 36 GPI 115 SUS_PW R_DN_ACK
38 W LAN_LED# NUMLED#/GPIO1A GPXID4 SUS_PW R_DN_ACK 15
10K_0402_5% (NUM_LED#) SUSP#
NC
NC
GPXID5 116 SUSP# 39,43,47,49
117 PBTN_OUT#
GPXID6 PBTN_OUT# 5,15,21
118 EC_PME#
EC_PME# 33
3
EC_CRY1 GPXID7
122 XCLK1
2 1 E51TXD_P80DATA 15 SUSCLK 1 @ 2 EC_CRY2 123 XCLK0 V18R 124 32.768KHZ_12.5PF_Q13MC14610002
100K_0402_5% R508 R740 0_0402_5% 1
AGND
C539
GND
GND
GND
GND
GND
69
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 37 of 59
5 4 3 2 1
+3VALW 1
R391
2
0_0603_5%
C506 1 2 0.1U_0402_16V4Z To TP/B Conn.
20mil +5VS
+SPI_VCC
220mils
U30 @ JTP1
37 EC_SPICS#/FSEL# EC_SPICS#/FSEL# 1 CE# VDD 8 1 1
R406 1 2 4.7K_0402_5% SPI_WP# 3 6 EC_SPICLK_R R387 1 2 0_0402_5% EC_SPICLK 37 2 TP_CLK 37
WP# SCK 2
+3VALW R390 1 2 4.7K_0402_5% SPI_HOLD# 7 HOLD# SI 5 EC_SO_SPI_SI_R R388 1 2 0_0402_5% EC_SO_SPI_SI 37 3 3 TP_DATA 37
4 2 EC_SI_SPI_SO_R R407 1 2 0_0402_5% 4 LEFT_BTN#
VSS SO EC_SI_SPI_SO 37 4 RIGHT_BTN#
5 5
MX25L8005M2C-15G_SOP8 6
6
7 GND 1 1
8
GND C683 C682
150mils ACES_85201-0605N @ @
CONN@ 2 2
(Left) JKB1 U31 100P_0402_50V8J 100P_0402_50V8J
EC_SPICS#/FSEL# 1 8 +SPI_VCC
KSO0
KSO1
26
25
KSO0 G2
28
27
INT_KBD Conn. SPI_WP#
SPI_HOLD#
3
7
CE#
WP#
VDD
SCK
6
5
EC_SPICLK_R
EC_SO_SPI_SI_R TP_CLK LEFT_BTN#
KSO2 KSO1 G1 HOLD# SI EC_SI_SPI_SO_R
24 KSO2 4 VSS SO 2
2
KSO3 23 TP_DATA RIGHT_BTN#
KSO4 KSO3 MX25L1005AMC-12G_SOP8
22
KSO4
3
KSO5 21 KSI[0..7] @
KSO5 KSI[0..7] 37 +5VS
KSO6 20 Reserved for BIOS simulator. 0_0402_5% R386 D19 D18
KSO7 KSO6 KSO[0..17]
19 KSO[0..17] 37 Footprint SO8 PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
1
KSO8 KSO7
18 1
KSO9 KSO8 @ C684
17 KSO9
KSO10 16 C497 0.1U_0402_16V4Z
KSO11 KSO10 33P_0402_50V8K
15
KSO12 KSO11 2
14 KSO12
KSO13 13
1
KSO14 KSO13
12
KSO15 KSO14
11
KSO16 KSO15
10 KSO16
KSO17 9 SW2 SW3
KSI0 KSO17 SMT1-05-A_4P SMT1-05-A_4P
8
KSI1 KSI0 LEFT_BTN# RIGHT_BTN#
7 KSI1 3 1 3 1
KSI2 6
KSI3 KSI2
5 4 2 4 2
KSI4 KSI3
4 KSI4
KSI5 3
5
6
5
6
KSI6 KSI5
2 KSI6
KSI7 1
KSI7
(Right)
ACES_88747-2601
CONN@
2
KSO14 C33 1 2 100P_0402_50V8J KSO6 C25 1 2 100P_0402_50V8J 2 LID_SW# 2 LID_SW# +3VS
2 LID_SW# 37 2
3 ACIN_LED# 3 ACIN_LED# R272
KSO13 C32 100P_0402_50V8J KSO5 C24 100P_0402_50V8J 3 3G_LED# 3 3G_LED# @
1 2 1 2 4 3G_LED# 37 4
4 4
2
5 WLAN_LED# WLAN_LED# 37 5 WLAN_LED# Q54A 100K_0402_5%
KSO12 C31 100P_0402_50V8J KSO4 C23 100P_0402_50V8J 5 MEDIA_LED# 5 MEDIA_LED#
1 2 1 2 6 6
1
6 6
7 +3VS 7 +3VS 6 1 5IN1_LED# 36
7 PWR_LED# 7 PWR_LED#
8 8
KSI0 C37 100P_0402_50V8J KSO3 C22 100P_0402_50V8J 8 ON/OFFBTN# 8 ON/OFFBTN# MEDIA_LED# DMN66D0LDW-7_SOT363-6
1 2 1 2 9 9 ON/OFFBTN# 39 9 9
10 10
KSO11 C30 100P_0402_50V8J KSI4 C41 100P_0402_50V8J 10 10
1 2 1 2 11 11 3 4 PCH_SATALED# 13
GND GND
12 12
KSO10 C29 100P_0402_50V8J KSO2 C21 100P_0402_50V8J GND GND Q54B DMN66D0LDW-7_SOT363-6
1 2 1 2
ACES_85201-1005N ACES_85201-1005N
5
KSI1 C38 1 2 100P_0402_50V8J KSO1 C20 1 2 100P_0402_50V8J CONN@ CONN@
+3VS
KSI2 C39 1 2 100P_0402_50V8J KSO0 C19 1 2 100P_0402_50V8J
KSO9 C28 1 2 100P_0402_50V8J KSI5 C42 1 2 100P_0402_50V8J Power/SUS Battery 3G/WLAN BlueTooth ACIN
LED Status
KSI3 C40 1 2 100P_0402_50V8J KSI6 C43 1 2 100P_0402_50V8J ON SUS Full Charge 3G WLAN
KSO8 C27 1 2 100P_0402_50V8J KSI7 C44 1 2 100P_0402_50V8J
NEW70/80/90 Blue Amber Blue Amber Blue Amber
LED3 ACIN_LED#
1
PWR_LED# D
+3VS 1 7080@ 2 2 1
R343 2.2K_0402_5% B 37,43,44 ACIN 2 Q53
G @
HT-191NB5_BLUE S
3
LED1 2N7002E-T1-GE3_SOT23-3
1 7080@ 2 2 1 PWR_SUSP_LED#
+3VALW
R344 3.9K_0402_5% A
HT-191UD5_AMBER
PWR_LED# PWR_SUSP_LED#
6
3
LED4
Q26A Q26B
1 7080@ 2 2 1 BATT_GRN_LED# 2 5 DMN66D0LDW-7_SOT363-6
+3VALW BATT_GRN_LED# 37 37 PWR_LED 37 PWR_SUSP_LED
R341 2.2K_0402_5% B DMN66D0LDW-7_SOT363-6
2
2
1
4
HT-191NB5_BLUE R340 R335
100K_0402_5% 100K_0402_5%
LED2
1
1
1 7080@ 2 2 1 BATT_AMB_LED# BATT_AMB_LED# 37
R342 3.9K_0402_5% A
HT-191UD5_AMBER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Thursday, January 07, 2010 Sheet 38 of 59
A B C D E
Power Button
ON/OFF switch
+3VALW
2
1 1
R409
38 ON/OFFBTN#
100K_0402_5%
TOP Side
1
SW1 2 ON/OFF 37
SMT1-05-A_4P
1 3 ON/OFFBTN# 1
2 4 3 51ON#
51ON# 44
@ D12
6
5
CHN202UPT_SC70-3
1
D
EC_ON 2 Q32
37 EC_ON
G 2N7002E-T1-GE3_SOT23-3
2
S
3
R413
Bottom Side 10K_0402_5%
SW4
SMT1-05-A_4P 1
1 3
2 4
6
5
2 2
Test Only
Power ON Circuit
+3VS
+3VALW +3VALW
1
U21A U21B
R331 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
For South Bridge
14
14
180K_0402_5%
D7
P
P
2
1 2 1 2 3 4 SYS_PWROK_1 1 @ 2
37,54 VR_ON I O I O EC_PWROK 15,37
R332 0_0402_5%
G
CH751H-40PT_SOD323-2 2
@
7
C455
1U_0603_10V6K
@ 1
3 3
+3VS
+3VALW +3VALW
1
R333
10K_0402_1% U21C U21D
14
14
P
2
SUSP# 1 2 5 6 9 8 1 2
37,43,47,49 SUSP# I O I O VS_ON 52
2 R320 0_0402_5%
G
G
1
D
SUSP 2 Q25 C456
For VTT
43,49 SUSP
7
G 0.1U_0402_16V7K
1 SUSP# @
S 1 2
3
+3VS
+3VALW +3VALW
C448
1
1 2 0.1U_0402_16V4Z
R319
31.6K_0402_1% U21E U21F
14
14
P
2
G
1
4 D 4
2
2 Q23 C447
43 DGPU_PWR_EN#
7
G DIS@ DIS@
S 1U_0603_10V6K
3
2N7002E-T1-GE3_SOT23-3 1 DGPU_PWR_EN @
1 2
R316 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 39 of 59
A B C D E
5 4 3 2 1
+5VAMP
1 2
1
1 2 R339 0_0805_5%
R298 0_0805_5% R698
SM010014520 3000ma 220ohm@100mhz DCR 0.04 +3VS 10K_0402_5%
1 2
+5VAMP R329 0_0805_5%
2
U19
1 2
60mil 40mil
1
+5VS L28 1 2 0.1U_0402_16V4Z 1 C783 1U_0402_6.3V4Z
IN
1
FBMA-L11-201209-221LMA30T_0805
OUT 5 +VDDA 4.75V D32 R704 1 2
@ 1 1 2 CH751H-40PT_SOD323-2 R696 R283 0_0805_5%
L27 1 C444 C438 GND 10K_0402_5% 10K_0402_5%
2
FBMA-L11-201209-221LMA30T_0805 3 4 1 2
2
0.1U_0402_16V4Z SHDN BYP C439 C773
2
D 2 2 G9191-475T1U_SOT23-5 0.01U_0402_16V7K 1 2 MONO_IN D
@ @ 1U_0402_6.3V4Z GND GNDA
1
C
C780 1 R699
(output = 300 mA) 37 BEEP# 2 1 2 2
B Q49
1
R694
2
2.4K_0402_1%
1U_0402_6.3V4Z 560_0402_5% E 1 2
3
2SC2411K_SOT23-3 R670 0_0805_5%
C785 1 R701
2 1 2
13 PCH_SPKR
1
1U_0402_6.3V4Z 560_0402_5% 1 2
D31 R308 0_0805_5%
CH751H-40PT_SOD323-2
1 2
2
R707 0_0805_5%
GND GNDA
HD Audio Codec
+AVDD_HDA
SM010015410 300ma 80ohm@100mhz DCR 0.3 Place near Codec
40mil SM010032020 600ma 120ohm@100mhz DCR 0.25
L70 1 2 0.1U_0402_16V4Z
10mil 0.1U_0402_16V4Z +3VS_DVDD L71 1 2
+VDDA +3VS
FBMA-L11-160808-800LMT_0603 1 1 1 MBK1608121YZF_0603
C739 C772 1 1 1
C738 C760 C748 C746
C 10U_0805_10V4Z 10U_0805_10V4Z C
2 2 2
0.1U_0402_16V4Z 2 2 2
25
38
9
U48
Place near Codec 0.1U_0402_16V4Z
DVDD_IO
AVDD1
AVDD2
DVDD
14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT 41
272@amp
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT 41
1K_0402_1% C775 1 2 MIC2_C_L 16 39
INT_MIC_R R702 2 INT_MIC 4.7U_0603_6.3V6K MIC2_L LOUT2_L
External MIC 1
C776 1 2 MIC2_C_R 17 41
4.7U_0603_6.3V6K MIC2_R LOUT2_R
23 45
LINE1_L SPDIFO2
24 46
LINE1_R DMIC_CLK1/2
18 43
LINE1_VREFO NC
20 44 1 2 1 2 C752
LINE2_VREFO DMIC_CLK3/4 R686 0_0402_5% 22P_0402_50V8J
Internal MIC REF For EMI
272@ MIC2_VREFO 19
MIC2_VREFO
6 HDA_BITCLK_AUDIO 13
MIC1_L C777 1 MIC1_C_L BITCLK
41 MIC1_L 2 21 MIC1_L
4.7U_0603_6.3V6K
MIC1_R C778 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
41 MIC1_R MIC1_R SDATA_IN HDA_SDIN0 13
4.7U_0603_6.3V6K R687 33_0402_5%
MONO_IN 12 37
PCBEEP_IN MONO_OUT
B B
CBP 29
11 2.2U_0402_6.3VM
13 HDA_RST_AUDIO# RESET#
31 C754 1 2
CPVEE
13 HDA_SYNC_AUDIO 10 SYNC 10mil External MIC REF 1
28 MIC1_VREFO 272@
MIC1_VREFO C758
13 HDA_SDOUT_AUDIO 5
SDATA_OUT HP_RIGHT
32 HP_RIGHT 41
HPOUT_R 2 2.2U_0402_6.3VM MIC2_VREFO
2
GPIO0/DMIC_DATA1/2
3 30
R695 2 SENSE_A GPIO1/DMIC_DATA3/4 CBN
41 MIC_PLUG# 1 20K_0402_1% 13 SENSE A 10mil
R685 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF C764 1 2 0.1U_0402_16V4Z
41 HP_PLUG# SENSE B VREF
1
C765 1 2 10U_0805_10V4Z For EMI
37 EAPD
1
R672
2
0_0402_5%
47 EAPD JDREF 40 R673 1 2 20K_0402_1%
Place next pin27
Int. MIC R703
2.2K_0402_5%
48 33 HP_LEFT 15mil 15mil
SPDIFO1 HPOUT_L HP_LEFT 41
JP1
2
4 26 1 INT_MIC_L 1 2 INT_MIC_R
DVSS1 AVSS1 1 L29 FBMA-L11-160808-700LMT_2P
7 42 2
DVSS2 AVSS2 2
1
ALC272X-GR_LQFP48_7X7 C786
3
G1 220P_0402_50V7K
G2 4
2
DGND AGND ACES_88266-02001
CONN@
3
D10 SM010004010 300ma 70ohm@100mhz DCR 0.3
PJDLC05C_SOT23-3
@
A A
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC272X
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 40 of 59
5 4 3 2 1
A B C D E
1
16
15
6
U50 R710 @ R709
100K_0402_5% 100K_0402_5%
PVDD1
PVDD2
VDD
1 1
2
C792 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
3 GAIN1
GAIN1
1
1 2 1 2 AMP_C_RIGHT 17
40 AMP_RIGHT C779 0.47U_0603_10V7K R697 0_0603_5% RIN- SPKR+ @ R711 R708
ROUT+ 18
100K_0402_5% 100K_0402_5%
14 SPKR-
2
C793 1 ROUT-
2 0.47U_0603_10V7K 9 LIN+
4 SPKL+
LOUT+
1 2 1 2 AMP_C_LEFT 5
40 AMP_LEFT C791 0.47U_0603_10V7K R712 0_0603_5% LIN- SPKL-
8
LOUT-
NC 12
EC_MUTE# BYPASS
10 Keep 10 mil width
37 EC_MUTE# 19 SHUTDOWN
2
GND5
GND1
GND2
GND3
GND4
C794
0.47U_0603_10V7K
1
21
20
13
11
1
2 2
TPA6017A2PWPR_TSSOP20
3 3
6
MIC1_VREFO
SINGA_2SJ-0960-C01
MIC_PLUG# CONN@
HP_PLUG#
Headphone Out
2
D27 D29
2
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
Int. Speaker Conn. D30
PJDLC05C_SOT23-3
1
Left Side
JSPK2
1
SPKL+ R354 1 2 0_0603_5% SPK_L+ 1
SPKL- R359 1 2 0_0603_5% SPK_L- 2
1 R676 R688 MIC JACK
1
2 4.7K_0402_5%
20mil 4.7K_0402_5% JMIC1
2
3 1
G1
2
3
1 1 4
SM010004010 300ma 70ohm@100mhz DCR 0.3 D28
C743 C759
PJDLC05C_SOT23-3 MIC_PLUG# 5
40 MIC_PLUG#
220P_0402_50V7K 220P_0402_50V7K
2 2
Right Side
1
JSPK1 6
4 4
SPKR+ R348 1 2 0_0603_5% SPK_R+ 1 SINGA_2SJ-A960-C01
1
SPKR- R347 1 SPK_R- 1
2 0_0603_5% 2 2
CONN@
2
D9 3
G1
PJDLC05C_SOT23-3 4 G2
ACES_88266-02001 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
Size Document Number Rev
1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 41 of 59
A B C D E
H10 H15 H6 H17 H21 H20 H2 H1 H5 H3 H16 H22
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @ @ @ @ @
1
GNDA
H11
H_3P0
H14 H9 H13 H8
FAN1 Conn H_4P2 H_4P2 H_4P2 H_4P2
@
1
+5VS @ @ @ @
1
C542 10U_0805_10V4Z +5VS
1 2
1
U35 D13
1 8 1SS355_SOD323-2 H12 H4
EN GND @ H_4P0 H_4P0
2 VIN GND 7
+VCC_FAN1 3 6
2
VOUT GND D15
37 EN_DFAN1 2 1 4 5
R461 300_0402_5% VSET GND @ @
1 2
1
1 APL5607KI-TRG_SO8 @
BAS16_SOT23-3
C570 C568
0.1U_0402_16V4Z 10U_0805_10V4Z
2 1 2
H18 H19 H7
+3VS C563 H_3P4 H_3P0X3P5N H_3P0N
1000P_0402_50V7K
1 2
1
@ @ @
1
R445
10K_0402_5%
40mil
JFAN1
2
+VCC_FAN1
1 FD4 FD2 FD1 FD3
37 FAN_SPEED1 2
3
1
C562 ACES_85205-03001 @ @ @ @
1
1000P_0402_50V7K CONN@
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 42 of 59
A B C D E
+5VALW
2
R337
+5VALW +5VS 100K_0402_5%
U49 +3VALW Short J5 for PCH VCCSUS3.3
SI4800BDY-T1-GE3_SO8 J5 @
1
8 1 1 2 SYSON#
1 2 36 SYSON#
7 2 +3V
6
6 3 1 1 JUMP_43X79 40mil
1 1 5 C761 C767 R692 U14 @
C763 C766 470_0603_5% SI4800BDY-T1-GE3_SO8 Q27A
10U_0805_10V4Z 8 1 SYSON 2
37,50 SYSON
4
10U_0805_10V4Z 2 2
1U_0603_10V4Z 7 2 DMN66D0LDW-7_SOT363-6
1
1 2 2 6 3 1
1 1
1
10U_0805_10V4Z 1 5 C393 C392 R226 R345
3
C407 @ 100K_0402_5%
Q47B 10U_0805_10V4Z 470_0603_5%
4
10U_0805_10V4Z 2 2
1U_0603_10V4Z
20mil 10mil
3 1
2
2 1 5VS_GATE 5 SUSP 2
+VSB
R684
200K_0402_5% 1
4
6
2
SUSP 2 2 Q16B
4
6
200K_0402_5% 1 DMN66D0LDW-7_SOT363-6 R346
C421 100K_0402_5%
1
DMN66D0LDW-7_SOT363-6 Q16A @
SBPWR_EN# 2 @ 0.1U_0603_25V7K
1
2 SUSP
39,49 SUSP
1
DMN66D0LDW-7_SOT363-6
3
+3VALW TO +3VS
Q27B
+3VALW +3VS 5 DMN66D0LDW-7_SOT363-6
37,39,47,49 SUSP#
U20
1
SI4800BDY-T1-GE3_SO8
4
8 1 R338
7 2 10K_0402_5%
2
6 3 1 1
1 1 5 C449 C446 R315
2
C454 C451 470_0603_5%
10U_0805_10V4Z
4
10U_0805_10V4Z 2 2
1U_0603_10V4Z
2 2 2
10U_0805_10V4Z 3 1 +5VALW 2
+1.8VS to +1.8VSDGPU for GPU
2
+1.8VS +1.8VSDGPU
20mil 10mil 3VS_GATE SUSP
+VSB 2 1 5 U37 DIS@ R31
R322 SI4800BDY-T1-GE3_SO8 100K_0402_5%
200K_0402_5% 1 Q22B 8 1 @
4
6
C450 DMN66D0LDW-7_SOT363-6 7 2 1 1
1
1
2
6 3 C648 C664 SBPWR_EN#
+ 20 SBPWR_EN#
Q22A 0.1U_0603_25V7K 1 5 C624 DIS@ DIS@ R502
SUSP 2 2 C670 DIS@ 470_0603_5%
2 2
1U_0603_10V4Z DIS@
1
DIS@ 330U_2.5V_M_R15 10U_0805_10V4Z D
1
1
DMN66D0LDW-7_SOT363-6 2
10U_0805_10V4Z 2 Q1
37 SBPWR_EN
G @
1
S
3
20mil 10mil R30 2N7002E-T1-GE3_SOT23-3
Q35B
1211 EMI ADD 0.1U close PJ5 +1.5V to +1.5VS +VSB 2 1 1.8VSDGPU_GATE DMN66D0LDW-7_SOT363-6 5 VGA_ON#
100K_0402_5%
@
R505 DIS@
2
+1.5V +1.5VS 510K_0402_5% 1
4
6
1
U13 DIS@ C650
SI4800BDY-T1-GE3_SO8 R472 DIS@
10U_0805_10V4Z 8 1 Q35A @ 0.1U_0603_25V7K
7 2 VGA_ON# 2 DIS@ 2 +5VALW
1 1
2
6 3 C328 C338
2
1 1 1 1 5 R181 DMN66D0LDW-7_SOT363-6
510K_0402_5%
2
C374 C389 C809 C810 10U_0805_10V4Z 470_0603_5%
1
2 2
1U_0603_10V4Z D R326
4
2 2 2 2 G @ DIS@
10U_0805_10V4Z S 2N7002E-T1-GE3_SOT23-3
1
3
1
R184 D
510K_0402_5%
1
U40 S
3
R185 @ 0.1U_0603_25V7K AO4430L_SO8 R325
2 8 1 2N7002E-T1-GE3_SOT23-3
100K_0402_5%
SUSP 2 7 2 1 1 DIS@
2
2
6 3 C717 C713
2
Q9A 1 5 DIS@ DIS@ R593
1
D DIS@ 10U_0805_10V4Z
1
ACIN Q10 2 +5VALW
37,38,44 ACIN 2
G @ 10U_0805_10V4Z
3
S 2N7002E-T1-GE3_SOT23-3
3
2
20mil 10mil
Q40B R232
2 1 1.5VSDGPU_GATE DMN66D0LDW-7_SOT363-6 5 VGA_ON# 100K_0402_5%
+VSB
R586 DIS@ 2009/08/17 add VGA_ON# DIS@
510K_0402_5% 1
1
6
VGA_ON# 2 2
1
R200 R427 R524 R569 510K_0402_5% D
2
@ DMN66D0LDW-7_SOT363-6 G DIS@
1
1
D
S
2
3
4 ACIN Q38 R231 4
2
G @ DIS@
1
D D D D
S 2N7002E-T1-GE3_SOT23-3 22K_0402_5%
3
2
G G G @ G
S S S S
3
VIN
1 1
VIN PR295
1M_0402_1%
1 2
1
PL24 VIN
PJP1 SMB3025500YA_2P PR296 VS
DC_IN_S1 1 2DC_IN_S2 10K_0402_5%
1
1
2 PR297
2
3 84.5K_0402_1%
4 47,48 PACIN PR298
GND
8
PC208 PR299 22K_0402_5%
2
GND PC206 PC207 100P_0402_50V8J PC209 10K_0402_5% 3 1 2
P
ACES_50305-00441-001 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1
2
37,38,43 ACIN O
20K_0402_1%
- 2
1
PR301
PU18A
1
PC210
LM393DG_SO8 PC211
0.1U_0603_25V7K
4
PR302 PD1 1000P_0402_50V7K
2
10K_0402_1% GLZ4.3B_LL34-2
2
2
2
PR303
10K_0402_1%
1 2
RTCVREF
2
Vin Dectector 2
PJ23
+1.0VSPDGPU 2 2 1 1 +1.0VSDGPU
JUMP_43X118
VIN
PJ6
2
+3VALWP 2 2 1 1 +3VALW
PD2 PJ2
LL4148_LL34-2 JUMP_43X118 2 1
+VGFX_COREP 2 1 +VGFX_CORE
PD3 JUMP_43X118
1
3
LL4148_LL34-2 PJ4 3
BATT+ 2 1 2 2 1 1
1
PJ8
PR304 PR305 2 1 JUMP_43X118
PQ42 68_1206_5% 68_1206_5% +5VALWP 2 1 +5VALW
TP0610K-T1-E3_SOT23-3 JUMP_43X118
PR306
2
200_0603_5% PJ5
CHGRTCP 1 2 N1 3 1 +1.5VP 2 1 +1.5V
VS PJ11
2 1
JUMP_43X118
1
2 1 PJ7
+VSBP 2 1 +VSB
1
PR307 PC213 2 2
100K_0402_1% PC212 0.1U_0603_25V7K JUMP_43X39 1 1
0.22U_0603_25V7K JUMP_43X118
2
PR308
2
22K_0402_1%
1 2 PJ9
39 51ON# +1.05VS_VTTP 2 1
2 1 +1.05VS_VTT
PJ14 JUMP_43X118
2 1 PJ10
+1.8VSP 2 1 +1.8VS
2 2 1 1
RTCVREF JUMP_43X118
1
JUMP_43X118
PR309
PU14 200_0603_5% PJ15
PR310 PR311 G920AT24U_SOT89-3 2 1
560_0603_5% 560_0603_5% 3.3V PJ17 +VGA_COREP 2 1 +VGA_CORE
2
1 2 1 2 3 2 N2 2 1 JUMP_43X118
OUT IN +0.75VSP 2 1 +0.75VS
+CHGRTC PJ16
JUMP_43X39 2 2 1 1
1
4 GND PC215 4
PC214
10U_0805_10V4Z 1
1U_0805_25V4Z - PBJ1 + +RTCBATT
JUMP_43X118
2
2 1
+RTCBATT
ML1220T13RE
<BOM Structure>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 44 of 59
A B C D
A B C D
GND 10
GND 9
8 8
7
PH1 under CPU botten side :
7 EC_SMDA
6 6 CPU thermal protection at 92 degree C
2
5 EC_SMCA
5 TH PR542
4 4
3 PI 100_0402_1%
Recovery at 56 degree C
3
2 2
1
1
1
1 1
2
PJP2
SUYIN_200275GR008G13GZR PR543
100_0402_1% VL
CONN@ <40,41> EC_SMB_DA1 37
VMB
1
VL
1
PL44
<40,41> EC_SMB_CK1 37
1
SMB3025500YA_2P
BATT+
2
BATT_S1 1 2 PR544 PC381 PR545 PR546
1K_0402_5% 0.1U_0603_25V7K 10K_0402_1% 21K_0402_1% @ PR547
2
PR548 100K_0402_1%
1
1
6.49K_0402_1%
2
PC379 PC380 2 1 PU30
+3VALW P
1
1000P_0402_50V7K 0.01U_0402_25V7K 1 8
2
2
VCC TMSNS1
2
2 7 PR549
GND RHYST1
1
9.53K_0402_1%
2
PR550 3 6
1K_0402_1% OT1 TMSNS2 @ PR551
1
1
4 5 47K_0402_1%
OT2 RHYST2
2
G718TM1U_SOT23-8 PH1
1
100K_0402_1%_NCP15W F104F03RC
BATT_TEMP 37
2
MAINPW ON 18,46,48
1
2 2
@ PH2
100K_0402_1%_NCP15W F104F03RC
2
PQ44
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
0.22U_0603_25V7K
0.1U_0603_25V7K
1
1
PC221
PC222
PR325
3
100K_0402_1% 3
2
PR327
2
VL 22K_0402_1%
1 2
2
PR329
100K_0402_1%
PR330
1
1K_0402_5% PQ45 D
1 2 2
46 SPOK G 2N7002W -T/R7_SOT323-3
S
3
1
PC224
1U_0402_6.3V6K
2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 45 of 59
A B C D
5 4 3 2 1
ISL6237_B+
ISL6237_B+
B+
PR331
PL26
0_0805_5%
1 2 1 2
HCB4532KF-800T90_1812
10U_1206_25V6M
2200P_0402_50V7K
10U_1206_25V6M
2200P_0402_50V7K
D D
5
6
7
8
1
PC225
PC226
PC228
8
7
6
5
PC227
VL
1U_0603_10V6K
2
2
2
2
PC230
PQ46 PC229
AO4466_SO8 0.1U_0603_25V7K 4
4.7U_0603_6.3V6K
3/5V_VCC
1
1
3/5V_VIN
4
PC231
PQ47 +5VALWP
2
AO4466_SO8
3
2
1
PL27
1
2
3
PL28 4.7UH_SIL104R-4R7PF_5.7A_30%
7
4.7UH_SIL104R-4R7PF_5.7A_30% PU16 PC232 2 1
1 2 1U_0603_10V6K
VIN
V5FILT
LDO
+3VALWP 33 19 1 2
TP V5DRV
5
6
7
8
1
PQ49
8
7
6
5
UG3 26 15 HG5 AO4712_SO8
PR332 DRVH2 DRVH1 PR336
0_0402_5%
2
2
2
+
PR335
PC233 PC237
61.9K_0402_1%
4
13V_SNB
2
220U_6.3VM_R15 + 4 PC234 220U_6.3VM_R15
2
0.1U_0603_25V7K
1
2
@ PR337
SW 3 25 16 SW 5
1
3
2
1
680P_0603_50V7K 0.1U_0603_25V7K PC238
1
2
3
2
2 LG3 23 18 LG5 680P_0603_50V7K
1
DRVL2 DRVL1
@ 10K_0402_1%
2
PGND 22
2
C C
PR338
FB3 30 VOUT2
PR339
0_0402_5%
VOUT1 10
VL 32
1
REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 VREF2
PC239
0.22U_0603_25V7K 9
VSW
8 LDOREFIN
29 5V_SKIP 2 1
SKIPSEL PR340
VL
@ 0_0402_5%
1 2
20 28 PR341
PD7 PR342 NC PGOOD2 0_0402_5%
VS RLZ5.1B_LL34 100K_0402_1%
1 2 EN_LDO-1 1 2 EN_LDO 4 13 SPOK 45
EN_LDO PGOOD1 PR344 For +5VALWP
2
402K_0402_1%
200K_0402_5%
TONSE
VREF3
1
27 31 ILIM2 2 1
GND
5uA*PR344=10*Iocpmin*18mΩ*1.3
1
EN2 TRIP2
PR345 =>PR344=397KΩ~402KΩ
2
2
RT8206BGQW QFN 32P 267K_0402_1%
21
1
B @ PR346 B
PD8 0_0402_5% 5uA*402K=10*ILIMTmin*18mΩ*1.3
13/5V_NC
PR561 1SS355_SOD323-2 PR347 ILIMTmin=8.589A
13/5V_TON
806K_0603_1% 0_0402_5% 5uA*402K=10*ILIMTmax*15mΩ*1.1
1
1
@
PR349 1U_0603_10V6K
2
ILMIT=12.181A
PC241
PR348 47K_0402_5%
2VREF_ISL6237
0_0402_5% Iocp=9.89A~13.48A
18,45,48 MAINPWON 2 1 1 2
2
@ 0.047U_0402_16V7K
080414:PQ23 ,Del @
Iocpmin=4.72*1.2=5.664~5.7A
2
PC242
PC243
PQ50
3
5uA*PR345=10*Iocpmin*Rdsonmax*1.3
5uA*PR345=10*5.7A*18mΩ*1.3
2VREF_ISL6237
2 PR345=266.76K~267K
TP0610K-T1-E3_SOT23-3
5uA*267KΩ=10*ILIMTmin*18mΩ*1.3
ILIMTmin=5.705A
5uA*267KΩ=10*ILIMTmax*15mΩ*1.1
1
ILIMTmax=8.09A
Iocp=6.47A~8.86A
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 46 of 59
5 4 3 2 1
A B C D
Iada=0~4.74A(90W/19V=4.736A)
ADP_I = 19.9*Iadapter*Rsense
CP = 85%*Iada ; CP = 4.07A B+
Iada=0~3.42A(90W/19V=3.421A) CP = 85%*Iada ; CP = 2.91A
P2 P3 B+ CHG_B+
PQ51 AO4407A_SO8 PQ52 AO4407A_SO8 PR351 0.02_2512_1% PQ53 AO4407A_SO8
PJ18
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_25V7K
0.1U_0603_25V7K
1 1
CSIP PR352
5600P_0402_25V7K
4
4
1
1
PC244
PC245
47K_0402_1%
VIN
PC246
PC247
PQ54 TP0610K-T1-E3_SOT23-3 1 2
PC248
2
1
3 1 DCIN
1
P3
2
PR353 PD9
1
47K_0402_1% PR356 ACOFF
100K_0402_1%
0.1U_0603_25V7K
1 2
1
PR354 PQ55 10K_0402_1%
1
PC249
PR355
200K_0402_1% PDTC115EU_SOT323 1SS355_SOD323-2
2
PR357
1 1
PD10 200K_0402_1%
2
PR358 2 FSTCHG 1 2 VIN
2
3
2 1 2 1
47K PQ56 PD11 1SS355_SOD323-2 3 SUSP#
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# 37,39,43,49 PQ57 PD12
2 BAS40CW _SOT323-3 PDTC115EU_SOT323 2 1 2
2.2U_0603_6.3V6K
47K
PC250
PR359
3
1
10K_0402_5% wrong Value 1SS355_SOD323-2
FSTCHG 2 1 PU17 PC252
37 FSTCHG
1
0.1U_0603_25V7K
0.1U_0603_25V7K
2
1
PQ58 1 2 1 24 DCIN 2 1 PQ61D
1
VDD DCIN
1
1
PC253
PDTC115EU_SOT323 PR360 47K_0402_5% PC251 2 PACIN
100K_0402_1%
6251VDD 1 2 0.1U_0402_16V7K 2N7002W
G -T/R7_SOT323-3
PR362
2 PR361 2 23 S
3
ACSET ACPRN
1
150K_0402_1% PR363
PQ60 20_0402_5%
2
2
1
2
2 PC254
3
5
6
7
8
G 2N7002W -T/R7_SOT323-3 2 0.047U_0402_16V7K
37 3S/4S#
S 4 21 1 2 CSOP PQ62
3
1
CELLS CSOP PR364 AO4466_SO8
2
PC255 6800P_0402_25V7K 20_0402_5% 2
3 1 2 5 ICOMP CSIN 20 2 1
1
2
PQ63 D PR365 4
PC257 20_0402_5%
2
G 2N7002W -T/R7_SOT323-3 1 2 1 PR366 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2 TCR=50ppm / C
<40,41>
1
PR368 VCOMP CSIP PR367 PL29
S
3
3
2
1
ACON 0.01U_0402_25V7K PC258 1 2 7 18 LX_CHG 1 2 CHG 1 4
48 ACON ICM PHASE
@ 100P_0402_50V8J 0.02_1206_1%
4.7_1206_5%
5
6
7
8
1
37 ADP_I 2 3
PR370
PR371 PC259 6251VREF 8 17 DH_CHG
22K_0402_5% PR372 VREF UGATE PR373 PC260
1 2
PACIN 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K
10U_1206_25V6M
10U_1206_25V6M
44,48 PACIN 1 2
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ64
2
37 IREF CHLIM BOOT
1
PD13 4
0.01U_0402_25V7K
AO4466_SO8
1
1
PC263
PC264
PQ65 PR375
1
PC261
680P_0402_50V7K
2 10 ACLIM VDDP 15
PC262
100K_0402_1% RB751V-40_SOD323-2
2
2
1
2.55K_0402_1%
PR377
12.1K_0402_1% 20K_0402_1% 1 26251VDD
3
2
1
2
ACOFF 2 PR378 11 14 DL_CHG
37,48 ACOFF
2
1 VADJ LGATE
2
PR376
4.7_0603_5%
12 13 PC265
2
1
GND PGND 4.7U_0603_6.3V6K
3
2
1
PQ66 D ISL6251AHAZ-T_QSOP24
2
37 65W/90W# G 2N7002W -T/R7_SOT323-3
S
3
3
CP mode 3
VMB
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) <40,41>
where Vaclm=1.502V, Iinput=4.07A PR379
15.4K_0402_1%
1
1 2
37 CALIBRATE#
2
Ki VS PR380
Vchlim=Iref*(PR374/(PR372+PR374)) PR381 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
CC=0.6~4.48A =Iref*(100K/(80.6K+100K)) 31.6K_0402_1%
2
=Iref*0.5537 BATT-OVP=0.1112*VMB
Iref=0.7224*Ichanrge
0.01U_0402_25V7K
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)
1
PC266
=1.3842*Iref
1
Iref=0.7224*Ichanrge =>Ki=0.7224
IREF=0.43V~3.24V PR382
2
Kv 499K_0402_1%
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K
2
8
r=514K//514K//31.6K=28.14K PR383 PU13B
Vcell=0.175*Vadj+3.99v 10K_0402_1% LM358DT_SO8 5
P
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V +
1 2 7 0
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 37 BATT_OVP 6
-
G
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899
1
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv
0.01U_0402_25V7K
4
1
A=Vref*(R/(R+514K))=0.052 PR384
PC267
Kv=9.451 105K_0402_1%
Charging Voltage
BATT Type CV mode
2
(0x15)
2
4 4
D D
PR385 B+
VL 2.2M_0402_5% PR386
2 1 1K_1206_5%
1 2
TP0610K-T1-E3_SOT23-3
PR388 PQ67
PD14
1
VIN 1K_1206_5%
PR387 2 1 1 2 3 1
B+
VS 499K_0402_1%
1
PR390
PR389 LL4148_LL34-2 1K_1206_5%
2
100K_0402_1% 1 2
100K_0402_5%
100K_0402_5%
1
1
PR392
PU18B PR391
2
PR393
18,45,46 MAINPWON PD15 LM393DG_SO8 1K_1206_5%
2
2 5 1 2
P
C + C
1 7 O
47 ACON 3 6
0.01U_0402_25V7K
2
-
G
1
32.4
PC270
BAS40CW _SOT323-3 PR394
1000P_0402_50V7K
4
1
PC269 191K_0402_1%
PC268 PR395
2
0.1U_0603_25V7K
2
PRG++ 2
1
499K_0402_1%
PR396
1
100K_0402_5%
PQ68
PDTC115EU_SOT323
1 2
PR397 1 PR398
34K_0402_1% PQ69D 47K_0402_5% 37,47 ACOFF 2
2 1 2 2 1 PQ70
RTCVREF 2N7002W
G -T/R7_SOT323-3 PACIN 44,47 PDTC115EU_SOT323
1
S
3
PQ71 2
3
1
PDTC115EU_SOT323
@ PR399
66.5K_0402_1% 2 +5VALW
3
2
ACIN
Precharge detector
Min. typ. Max.
B B
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PRECHARGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 48 of 59
5 4 3 2 1
5 4 3 2 1
D D
C C
PL30
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% +1.8VSP
LX_1.8V 1 2
2
VFB=0.8V PR405
2
309K_0402_1%
1
PR563
PU20 4.7_1206_5% PC278 PC279
1
2
402K_0402_1%
1
1 2 1 10 1.8V_EN
FB EN/SYNC
1
2 GND GND 9
PC281 PC382
1 2 3 8 680P_0402_50V7K
2
SW SW
+5VALW 0.01U_0402_16V7K 4 7
IN IN
1
B 1 2 5 6 B
BS POK
1
@ PD16
PC282
10U_0805_10V4Z
PC283
10U_0805_10V4Z
PR566
0_0402_5% TP 11
B340A_SMA2
+1.5VS +1.5V
2
OP1 Short
OP2 Short
1
PJ24 PJ20
1
JUMP_43X39 JUMP_43X39
2
PU21
2
1 VIN VCNTL 6 +3VALW
2 GND NC 5
1
1
PC284 3 7 PC285
4.7U_0603_6.3V6K PR408 REFEN NC 1U_0402_6.3V6K
2
PR401 1K_0402_1% 4 8
22K_0402_5% OP2@ VOUT NC
2
0_0402_5% GND
APL5336KAI-TRL SO8
1 2
OP1@ PR409
0.1U_0402_16V7K
+0.75VSP
1
1
24.9K_0402_1% D OP1@ PQ102
1
D
39,43 SUSP
PC286
PC274 1 2 2 2N7002W -T/R7_SOT323-3 PR410
1
0.47U_0603_16V7K G SUSP 2 1K_0402_1%
2
2
1
S PQ72 G PC288
3
2
1U_0402_6.3V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSP/+0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 49 of 59
5 4 3 2 1
A B C D
PL31
FBMA-L18-453215-900LMA90T_1812
B+
51117_1.5V_B+ 2 1
EN_PSV
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode
1
3. HIGH=>Auto_skip mode
PC289
PC290
5
6
7
8
Because +1.5VSP has 17.74A power budget, it includes
2
PQ73
1
DDR3, VGA chip, VRAM, so must use molding choke. AO4466_SO8 1
PR411 4
280K_0402_1%
1 2
PR412
0_0402_5%
3
2
1
1 2 1.5V_EN BST_1.5V
1
37,43 SYSON
1
@ PR413 PR414 PL32
15
14
PC292
+1.5VP
1
47K_0402_5% @ PC291 PU22 0_0603_5% 1UH_FDUE1040D-1R0M-P3_21.3A_20%
0.1U_0402_16V7K 1 2BST_1.5V-1 1 2 1 2
EN/DEM
NC
BOOT
2
2
2 13 UG_1.5V 0.1U_0603_25V7K
TON UGATE
1
3 12 LX_1.5V
VOUT PHASE
5
6
7
8
PR415 1
4 11 +5VALW PQ74 4.7_1206_5%
VDD CS AO4456_SO8 + PC293
2
5 10 330U_6.3V_M
PR416 FB VDDP
1
100_0603_1% LG_1.5V 2
6 9 4
open-drain PGOOD LGATE
PGND
1 2 PC294
GND
+5VALW
680P_0603_50V7K
2
1
11K_0402_1%
1
@ PC297 RT8209BGQW _W QFN14_3P5X3P5 PC295
3
2
1
1
4.7U_0805_10V6K
PR417
47P_0402_50V8J
2
PC296 1 2
4.7U_0603_6.3V6K
2
2
2
Rds=4.5mΩ(Typ) 2
PR418 5.6mΩ(Max)
5.9K_0402_1% VFB=0.75V
1 2 VFB=0.75V
Vo=VFB*(1+PR418/PR419)=1.52V
1
Freq=282KHz(min) , 300KHz(typ)
PR419
5.76K_0402_1% Cesr=15m ohm
Ipeak=15.82A
2
Iocpmin=18.98A
∆I=((19-1.5)*(1.5/19))/(L*Freq)=4.899A
1/2∆I=2.449A
Iocp=18.09A~29.13A
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 50 of 59
A B C D
5 4 3 2 1
VGA@ PL13
FBMA-L11-322513-201LMA40T_1210 VGA_CORE
B+ 1 2 B+_CORE
F=1/(75*e-12*44.2)=300K
Ipeak=33A Imax=23.1A Iocp=39.6A
Iocpmin=(5.11K*26uA)/((5.6mohm/2)*1.2)=39.54A
7138_VCORE LX_VCORE
Iocpmin=39.54A
1
VGA@ PC164
1
10U_1206_25V6M VGA@ PC165 DH_VCORE
10U_1206_25V6M VGA@
2
@ PR182 1 2 1 2
2
D 10K_0402_1% PR184 0_0603_5%
BST_VCORE D
VGA@ PC166
2
+5VS 0.1U_0603_25V7K
18 VGA_PWROK
5
VGA@ PR185 VGA@ PQ38
0_0603_5% SI7686DP-T1-E3_SO8 @ PQ79
VGA@ PR186 SI7686DP-T1-E3_SO8
16
15
8
1
4.7_0603_5%
2
1 2 7138_VCORE 4
UG
BOOT
PHASE
GND
PGOOD
VGA@ PC167 4
2.2U_0603_6.3V6K
3 VIN PVCC 14 1 2
+3VS
3
2
1
7138_VCORE
3
2
1
4 13 DL_VCORE VGA@ PL14
VCC LG 0.36UH_PCMC104T-R36MN1R17_30A_20%
2
1
VGA@ PC168 VGA@ PU998 1 2 +VGA_COREP
@ PR187 2.2U_0603_6.3V6K APW7138NITRL_SSOP16
5
6
7
8
5
6
7
8
1
10K_0402_5% VFB=0.6V 12
2
PGND VGA@ PR191
1
VGA@ PR189 VGA@ PR190 VGA@ PQ75 VGA@ PQ78 4.7_1206_5% 1
1
1 2
9,43,52 VGA_ON EN ISEN
4 4 ESR=10mohm
FSET
2
1
NC
VO
FB
VGA@ PC170 680P_0603_50V7K 10_0402_5%
2
C 0.1U_0402_16V7K 2 1 GCORE_SEN C
GCORE_SEN 24
2
10
3
2
1
3
2
1
2
VGA@ PR193
4.99K_0402_1%
1
1
D
VGA@
36.5K_0402_1%
VGA@ PQ98 MAD@ PR197
1
1
2N7002W-T/R7_SOT323-3 68.1K_0402_1%
23,43,52 VGA_ON#
2 Rds=4.5m/5.6mOHM
1
1
G VGA@ PC172 VGA@ PR195
+3VS
PR196
S 22P_0402_50V8J 49.9K_0402_1% @ PC998
3
0.01U_0402_25V7K
2
2
PAK@ PR197
2
43.2K_0402_1%
1
VGA@ PR211
2N7002W-T/R7_SOT323-3
VGA@ PC174 10K_0402_5%
6800P_0402_25V7K
2
1 1
1
VGA@ PQ76
VGA@ PR199
1
D 10K_0402_5%
PAK@ PR198 2 1 2
PR195/PC172/PC174 must pop and modify in PVT. 8.87K_0402_1% G
2
S
1
MAD@ PR198 VGA@ PC175 @ PR200
9.53K_0402_1% 4700P_0402_25V7K 10K_0402_5%
1
B B
MAD@ PR201
31.6K_0402_1%
+3VS
1
PAK@ PR201
2
25.5K_0402_1% +3VS
@ PR555
2
10K_0402_5%
2
Core Voltage Level Core Voltage Level VGA@ PR210
10K_0402_5%
MADISON PRO PARK XT
1
GPU_VID1 GPU_VID0 VGA@ PR556
1
VGA@ PR202 VGA@ PQ99 D 10K_0402_5%
1
1
VGA@ PQ77 D 10K_0402_5% 2N7002W-T/R7_SOT323-3 2 2 1
GPU_VID1 23
1
2N7002W-T/R7_SOT323-3
1 1 0.90 V 0.93 V G
2 1 2
S
G
3
S VGA@ PR557
1
+3VS 10K_0402_5%
0 1 0.95 V 1.00 V VGA@ PC177
2
4700P_0402_25V7K
2
1 0 1.00 V 1.05 V X
@ PR204 @ PR558
2
10K_0402_5% 10K_0402_5%
0 0 1.05 V X 1.12 V
1
VGA@ PR559
1
VGA@ PQ100 D 10K_0402_5%
2N7002W-T/R7_SOT323-3 2 2 1
GPU_VID0 23
1
G
A A
S VGA@ PR560
3
10K_0402_5%
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/12/18 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP/+1.1VSDGPU
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NEW70 M/B LA-5891P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 29, 2009 Sheet 51 of 59
5 4 3 2 1
5 4 3 2 1
PL37
FBMA-L18-453215-900LMA90T_1812
2 1 6268_B+
B+
PR458 +5VS +3VS
0_0402_5%
10U_1206_25V6M
10U_1206_25V6M
1 2
LX_1.05VS_VTT
1
H_VTTPWRGD 5
2K_0402_1%
2K_0402_1%
PC326
PC327
DH_1.05VS_VTT
PR460
PR459
PGOOD=1V PR461
2
BST_1.05VS_VTT
1 2 1 2
@ PR462 0_0603_5%
2
D 1K_0402_1% PC328 D
1 2 +5VS 0.1U_0603_25V7K
5
PR463
0_0603_5% PQ82
SI7686DP-T1-E3_SO8
PR464
16
15
8
1
4.7_0603_5%
2
1 2 6268_VCORE_1.05VS_VTT 4
UG
BOOT
PHASE
GND
PGOOD
Layout Note: DCR=2.7mΩ(Typ)
3 14 1 2
VIN PVCC Close IC 3.0mΩ(Max)
3
2
1
PC329
2.2U_0603_6.3V6K
6268_VCORE_1.05VS_VTT
4 VCC LG 13 DL_1.05VS_VTT PL38 +1.05VS_VTTP
1UH_FDUE1040D-1R0M-P3_21.3A_20%
PU999 1 2
1
APW7138NITRL_SSOP16
1
TPCA8028-H_SOP-ADVANCE8-5
TPCA8028-H_SOP-ADVANCE8-5
PC330 12
2.2U_0603_6.3V6K PGND @
PQ83
PQ95
PR466 PR465
57.6K_0402_1% 4.7_1206_5%
39 VS_ON 1 2 5 11 1 2
1 2
EN ISEN
4 4 1
1
PR467
FSET
1
4.99K_0402_1% PC332 + PC333
NC
VO
FB
@ PR468 PC331 680P_0603_50V7K 390U_2.5V_M
2
10K_0402_5% 0.1U_0402_16V7K
10
3
2
1
3
2
1
C 2 C
2
90.9K_0402_1%
Fsw=1/(PR470*K)=231KHz,
57.6K_0402_1%
Rdson=2.3mΩ/3.2mΩ Material Note:
1
K=75*10^-12
22P_0402_50V8J
Layout Note: 330uF/9 mΩ, number
1
單單單單單單Pin15
PR469
+1.05VSP_VTT PC334 Close IC are 3, Power 1, HW 2
PR470
6800P_0402_25V7K
@ PC999
0.01U_0402_25V7K
Ipeak=25A 2
2
2
Imax=17.5A
1
PC336
@ PR471
Rsen(PR467)=2.2K 0_0402_5%
1 2 +1.05VS_VTTP
2
Iocp=31.19A~56.41A
Vref=(Rb/(Rtop+Rbot))*Vo PR472 @ PR473
5.11K_0402_1% 10_0402_5%
=>0.6=(6.65/(5.11+6.65))*Vo 1 2 1 2 VTT_SENSE 7
Vo=1.061V VFB=0.6V
PR564
0_0402_5%
1 2 +1.05VS_VTT
B +5VS B
1
+1.5V
PR476
6.65K_0402_1%
1
2
1
VGA@ PC320
1U_0402_6.3V6K @ PJ22
1
2
JUMP_43X118
2
2
1
6 VGA@ PC367
VCNTL 4.7U_0603_6.3V6K
5 3
2
POK FB
1
1
2
1
A A
2
2N7002W-T/R7_SOT323-3 D
1
23,43,51 VGA_ON# 2
G
S VGA@ PR529 Security Classification Compal Secret Data Compal Electronics, Inc.
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NEW70 M/B LA-5891P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 29, 2009 Sheet 52 of 59
5 4 3 2 1
5 4 3 2 1
UMA@ PL23
B+ FBMA-L18-453215-900LMA90T_1812
2 1 GFX_B+
2
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
UMA@ PR263
@ PC188 UMA@ PR264 0_0603_5% VSS_AXG_SENSE
UMA@ PC187
UMA@ PC125
UMA@ PC126
0.22U_0603_25V7K
1
1
0.1U_0402_25V6 1_0603_5%
UMA@ PC190
+5VALW 2 1
1 1
2
2
2
UMA@ PC189
1U_0402_6.3V6K UMA@ PR265 UMA@ PC191
22.6K_0402_1% 0.22U_0402_6.3V6K
1
1
UMA@ PR292
GFXVR_IMON 8
2 1 ISUM+
5
10_0402_1% UMA@ PC192
1000P_0402_50V7K ISUM-
1 2 BST_GFX 1 2 1 2
8 VSS_AXG_SENSE
1
29
10
11
12
13
14
1 2
2
9
+VGFX_COREP UMA@ PC195
DCR=1.1 mOHM
AGND
RTN
ISUM+
VDD
VIN
IMON
BOOT
ISUM
2 1 330P_0402_50V7K
3
2
1
UMA@ PR293
10_0402_1% 7 15 DH_GFX UMA@ PL10 +VGFX_COREP
VSEN UGATE 0.45UH_PCMB104T-R45MN_25A_20%
6 UMA@ PU12 16 LX_GFX 4 1
FB ISL62881HRZ-T_QFN28_4X4 PHASE
5
6
7
8
5
6
7
8
5 17 3 2
COMP VSSP
1
4 18 DL_GFX UMA@ PQ40 UMA@ PR268 1
VW LGATE
1
UMA@ PR294 AO4456_SO8 4.7_1206_5% UMA@
2 1 3 19 UMA@ UMA@ PR269 PR270 + UMA@ PC130
UMA@ PR271 UMA@ PR272 UMA@ PC197 RBIAS VCCP PQ41 3.65K_0805_1% 330U_X_2VM_R6M
47K_0402_1% 4 4 0_0402_5%
2
8.66K_0402_1% 825K_0402_1% 1000P_0402_50V7K 2 20 UMA@ PR273 AO4456_SO8
PGOOD VID0 UMA@ PR274 2
2 1 1 2 1 2 2 1 1 2 +5VALW
2
147K for CPU 1 21 0_0603_5% 2.61K_0402_1% UMA@ PH3
DPRSLPVR
CLK_EN# VID1
2
UMA@ PC196 1 2 1 2
47K for GPU
3
2
1
3
2
1
1
100P_0402_50V8J +VGFX_COREP UMA@ PC199
VR_ON
680P_0603_50V7K 10K +-5% TSM0A103J4302RE 0402
VID6
VID5
VID4
VID3
VID2
1
UMA@ PR275 UMA@ PC201 UMA@ PR276 UMA@ PC198
2
17.8K_0402_1% 22P_0402_50V8J 8.06K_0402_1% 2.2U_0603_6.3V6K
2 1 2 1 1 2 2 1
28
27
26
25
24
23
22
1 2
UMA@ PC200 UMA@ PR277
Rds=4.5mOHM(typ)
1
UMA@ PC202
0.1U_0402_16V7K
B 37 GFX_CORE_PWRGD B
1 2
2
0_0402_5% 2 UMA@
1 PR280 UMA@ PC203
0_0402_5% UMA@ GFXVR_VID_0 8
2 1 PR281 0.1U_0402_16V7K @ PR284
0_0402_5% UMA@ GFXVR_VID_1 8
2 1 PR282 UMA@ PR283 100_0402_1%
0_0402_5% UMA@ GFXVR_VID_2 8
2 1 PR285 UMA@ PR288 1.69K_0402_1%
0_0402_5% UMA@ GFXVR_VID_3 8
2 1 PR286 82.5_0402_1%
1
0_0402_5% UMA@ GFXVR_VID_4 8
2 1 PR287 1 2 1 2
0_0402_5% UMA@ GFXVR_VID_5 8
2 1 PR289
GFXVR_VID_6 8
2
0_0402_5% 2 UMA@
1 PR290 UMA@ PC204
0_0402_5% @ 1 PR291 GFXVR_EN 8 0.01U_0402_16V7K @ PC205
2
UMA@ PR567 GFXVR_DPRSLPVR 8
180P 50V J NPO 0402
1
0_0402_5% ISUM+
2 1 +1.05VS_VTT
ISUM-
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 53 of 59
5 4 3 2 1
8 7 6 5 4 3 2 1
+5VS
1
7 H_DPRSLPVR
PR565
7 H_PSI# 0_0805_5% 0 1 2 Auburndale 35W 0.975 38 1.9m 29 27
2
7 CPU_VID6 1 1 3 Clarksfield SV 0.95 51 1.9m 38 39
7 CPU_VID5
7 CPU_VID4
7 CPU_VID3
+5VS_3212 Clarksfield XE 0.95 65 TBD 48 TBD
+5VS_3212
7 CPU_VID2
7 CPU_VID1
7 CPU_VID0
1
+CPU_B+ PL39
PR481 FBMA-L18-453215-900LMA90T_1812
10_0603_5%
37,39 VR_ON 2 1 B+
2
G G
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_25V7K
220U_25V_M
1
499_0402_1%
PC339
PC341
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
1
PC344 +
PC345
PC343
2
2
2
+3VS 1U_0603_16V6K
PC342
5
2
+3VS PR491 PQ87 @ 2
1
0_0603_5% TPCA8030-H_SOP-ADV8-5
2
2
PR482
PR483
PR484
PR485
PR486
PR487
PR488
PR489
PR490
2 1
PR492
2
0_0402_5%
1 PU27 @ PQ86
PR493
PGND
1
48
47
46
45
44
43
42
41
40
39
38
37
0.36UH +-20% ETQP4LR36WFC 24A
1
3
2
1
3
2
1
1 2 CLK_EN# 3212_SW1 1 4
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PH0
PH1
PSI
VCC
DPRSLP
12 CLK_ENABLE# +CPU_CORE
PR497 0_0402_5%
2
2 3
5
12,15 VGATE 1 2 0_0603_5% 0.1U_0603_25V7K DCR=1.1m OHM
1
F F
1 36 2 1 2 1
EN BST1
1
1
PR499
4.7_1206_5% PR500
@ PR496 2 35 3212_DRVH1 @ 10_0402_5%
0_0402_5% PWRGD DRVH1 3212_DRVL1 3212_DRVL1
4 4
1 2
2
2
IMVP_IMON 3 34 3212_SW1
7 IMVP_IMON IMON SW1
2
PR502 PC347
1
100_0402_1% 680P_0603_50V7K
3
2
1
3
2
1
3212_CS_PH1
PR501 PC348 CLK_EN# 4 33 1 2 3212_CS_PH1 @
5.49K_0402_1% CLKEN SWFB1
0.068U_0402_16V7K
2
CSREF
PQ88
1
1
1000P_0402_50V7K 1 2 3212_FB PC352 6 31 3212_DRVL1 +CPU_B+
FB DRVL1 PC350
ADP3212MNR2G_QFN48_7X7
1
PC353 4.7U_0603_6.3V6K
2
150P_0402_50V8J PR504 7 30
E PR503 COMP PGND E
1.65K_0402_1% 39.2K_0402_1%
10U_1206_25V6M
2
1 2 1 2 1 2
1
2 1 8 29 3212_DRVL2 PC355 @ PC356
5.11K_0402_1% TRDET DRVL2
5
PR505 PR506 10U_1206_25V6M 0.1U_0603_25V7K
PC354
100_0402_1% PQ90
2
+5VS_3212 9 28 1 2 3212_CS_PH2 TPCA8030-H_SOP-ADV8-5
VARFR SWFB2
3
2
1
3
2
1
0_0603_5% 0.1U_0603_25V7K 3212_SW2 4 1
2
12 25 2 1 2 1
1
5
@ 499_0402_1%
CSSUM
SWFB3
CSREF
PWM3
1
RAMP
LLINE
PR511 0_0402_5% 49
IREF
RPM
OD3
ILIM
AGND PR512
RT
D D
1
2
1 2 4.7_1206_5%
5 H_PROCHOT#
@ PR513
13
14
15
16
17
18
19
20
21
22
23
24
1 2
2N7002W-T/R7_SOT323-3
D
PQ94
162K_0402_1%
1
1
2 3212_VRTT PC359
3212_CSCOMP
3212_CSCOMP
680P_0603_50V7K
3212_CS_PH2
PR514
PR516
3
2
1
3
2
1
2
S 80.6K_0402_1% @
3
CSREF
+5VS_3212 2.05K VGA@ PQ93 PQ92
2
TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5
1
1
1K_0402_1%
73.2K_0402_1%
680P_0402_50V7K
PC360
1
PR522
0.01U_0402_50V7K
2
PC363
PR523
2
165K_0402_1%
2
CSREF 1 2
2
2
100K_0402_1%_NCP15WF104F03RC
2 1 3212_CS_PH2
1
B PR525 130K_0603_1% B
@ PR526
100_0402_1%
2 1 +CPU_CORE
VCCSENSE
VCCSENSE 7
VSSSENSE
VSSSENSE 7
2 1
PR527 100_0402_1%
A @ A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/08/01 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Tuesday, December 29, 2009 Sheet 54 of 59
8 7 6 5 4 3 2 1
5 4 3 2 1
Adjust +1.05VS_VTTP OCP. Because we remove a LS MOS, so OCP must adjust. 0.2 52 Change PR467 from SD000004O80(S RES 1/16W 2.2K +-1% 0402) 2009-1029 to DVT
14 to SD034499180(S RES 1/16W 4.99K 0402 1%)
+1.8VSP2, Using MP2121 for 1.8V No need to use LDO for +1.8V.
0.2 49 Delete PU19 SA00001NC00 (S IC APL5913-KAC-TRL SO 8P) 2009-1029 to DVT
15 only. Delete all PU19 circiut.
B +1.8VSP2, Using MP2121 for 1.8V No need to use LDO for +1.8V. Delete PR402 SD034150280, PR404 SD034120280. B
23 issue. so when caculate OCP, Rdson must reduce 1/2. (S RES 1/16W 5.11K 0402 1%)
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Change PL40/PL41 from SHSH00000F000 S COIL 0.36UH +-20%
D CPU choke TOHO quality issue. Because TOHO has quality issue before, change to SF-I104-R36 23A to SH000005680 S COIL 0.36UH +-20% to DVT D
0.2 54 2009-1029
1 Panasonic choke. PCMC104T-R36MN1R17
to DVT
+VGA_COREP, voltage change. ATI updated Park output voltage. 0.2 51 Change PR197 from SD034649280 to SD034432280. 2009-1029
2
+VGA_COREP, voltage change. ATI updated Park output voltage. 0.2 51 Chnage PR198 from SD034953180 to SD034887180. 2009-1029 to DVT
3
+VGA_COREP, voltage change. ATI updated Park output voltage. 0.2 51 CHange PR201 from SD034316280 to SD034255280. 2009-1029 to DVT
4
When VGA_CORE start up, but VBIOS doesn't ready,
+VGA_COREP, initial state unknow. the VID is unknow, add pull down R. 0.2 51 Add PR557/PR560 SD028100280( S RES 1/16W 10K 0402 5%) to DVT
2009-1029
5
Because HW request that adjust power sequence,
+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW. Change PC369 from SE076104K80 to SE000000K80 to DVT
0.2 52 2009-1029
6 (S CER CAP 1U 0402 X7R)
Because HW request that adjust power sequence,
+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW. Change PR530 from SD028150380 to SD034270280 2009-1029 to DVT
0.2 52
7 (S RES 1/16W 27K 0402 1%)
Because HW request that adjust power sequence,
+1.0VSPDGPU,adjust power sequence. we will follow the value which given by HW. Delete PR562 SD028220280 (S RES 1/16W 22K +-5% 0402) 2009-1029 to DVT
0.2 52
C 8 C
Because HW request that adjust power sequence, Change PR409 SD028000080 to SD034249280( 24.9K 0402 1%) to DVT
+0.75VSP,adjust power sequence. we will follow the value which given by HW. 0.2 49 2009-1029
Change PC287 from SE076104K80 to SE000000K80
9
Change PR405 from SD034316380(S RES 1/16W 316K +-1% 0402) to DVT
=1.8VSP, voltage too small. Because +1.8VSP drop in HW side, increase +1.8VSP. 0.2 49 to SD034309380(S RES 1/16W 309K 0402 1%) 2009-1029
10
Because GFX_COREP has spike voltage issue, originally
+GFX_COREP, spike voltage issue. we add a schottcky diode to solve it, but Intel's Delete PD17 SCS00000Z00( S SCH DIO RB751V-40 SOD-323)
0.3 53 2009-1104 to DVT
11 command is that do not add it, because of overdriving,
so delete it now.
12 +GFX_COREP, EMI request. EMI request to add snubber. 0.3 53 Add PR268 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
2009-1104 to DVT
Add PC199 SE025681K80(S CER CAP 680P 50V K X7R 0603)
13 +1.05VS_VTTP, EMI request. EMI request to add snubber. Add PR465 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
0.3 52 2009-1104 to DVT
Add PC332 SE025681K80(S CER CAP 680P 50V K X7R 0603)
14 +VGA_COREP, EMI request. EMI request to add snubber.
Add PR191 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
0.3 51 2009-1104 to DVT
Add PC171 SE025681K80(S CER CAP 680P 50V K X7R 0603)
15
B Add PR415 SD001470B80(S RES 1/4W 4.7 +-5% 1206) B
+1.5VP, EMI request. EMI request to add snubber. 2009-1104 to DVT
0.3 50 Add PC294 SE025681K80(S CER CAP 680P 50V K X7R 0603)
16
Add PR370 SD001470B80(S RES 1/4W 4.7 +-5% 1206)
Charger, EMI request. EMI request to add snubber. 0.3 47 2009-1104 to DVT
Add PC262 SE074681K80 (S CER CAP 680P 50V K X7R 0402)
17
CPU_COREP, transient, load line CPU_COREP, transient, load line Change PR524/PR525 from SD014120380 to SD014130380.
modify. modify. 0.3 54
Change PR501 from SD034536180 to SD034549180
18 2009-1104 to DVT
Change PC362 from SE074391K80 to SE074681K80
Change PL40/PL41 from SH000005680 to SH12036BM00.
Add PC221 SE000005Z80 S CER CAP .22U 25V K X7R 0603.
+VSBP, EMI request. EMI request to add cap to reduce EMI noise on B+ 0.3 45 2009-1104 to DVT
Add PC222 SE042104K80 S CER CAP .1U 25V K X7R 0603
19
Add PR401 SD014220280 S RES 1/16W 22K 0402 5%
+1.8VSP BOM error. Loss +1.8VSP enable circiut. 0.3 49 2009-1104 to DVT
Add PC274 SE026474K80 S CER CAP 0.47U 16V K X7R 0603
20
Because ATI change Park output voltage, we saperate Change PR197 from SD034432280 to SD034681280.
+VGA_COREP, output voltage change. Park and Madison by PAK@ and MAD@. And Change Madison 0.4 51
Chnage PR198 from SD034887180 to SD034953180.
21 X63 BOM. 2009-1113 to DVT
Change PR201 SD034255280 to SD034316280.
A A
Because HW want to measure CPU_CORE IC power loss,
22 +CPU_COREP, power measure. Add 0805 R to saperate +5VS. 0.4 54 Add PR565 SD002000080 S RES 1/8W 0 +-5% 0805 2009-1113 to DVT
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D Intel release IMON RC time constant new request, Change PC348 from SE076103K80 S CER CAP .01U 16V K X7R 0402 D
+CPU_COREP, IMON design change. 0.4 54 2009-1113 to DVT
1 change PC348 to 0.068u to meet spec. to SE000003J80 S CER CAP 0.068U 16V K X7R 0402
+CPU_COREP, cost issue. SF000000G80 will cost up, change to SF22004M210. 0.4 54 Change PC343 from SF000000G80 to SF22004M210. 2009-1113 to DVT
2
Because Nippon cost up thier OS-CON cap, so we change Change PC233/PC237 from SF22001M300 S ELE CAP 220U 6.3V M
+3V/+5V cost issue. Nippon cap to Sanyo cap by sourcer request. 0.5 46 F60(6.3X5.7) PXC to SF22001M200 S ELE CAP 220U 6.3V M B 2009-1118 to DVT
3 C6 SVPC ESR15
+1.05VS_VTTP issue. +1.05VS_VTTP choke unique to +1.5VP. 0.5 52 Change PL38 from SH000008V80 S COIL 1UH +-20% PCMB103E-1R0MS2009-1118 to DVT
4 20A to SH000009U00 S COIL 1UH +-20% FDUE1040D-1R0M=P3 21.3A
In order to phase in 2nd source of APW7138, must add Add PC172 SE071220J80 S CER CAP 22P 50V J NPO 0402
+VGA_COREP 2nd source issue. Pin6 components to meet ISL6268 reqirement. 0.6 51 Add PC174 SE075682K80 S CER CAP 6800P 25V K X7R 0402 2009-1208 to PVT
5 Add PR195 SD034909280 S RES 1/16W 90.9K 0402 1%
In order to phase in 2nd source of APW7138, must add
6 +VGA_COREP 2nd source issue. Pin6 components to meet ISL6268 reqirement. 0.6 51 Change location PU23 to PU998. 2009-1208 to PVT
In order to phase in 2nd source, change ISL6268 to Change PU26 from SA00001HT80 S IC ISL6268CAZ-T SSOP 16P
+1.05VS_VTTP 2nd source issue. 0.6 52 2009-1208 to PVT
7 APW7138. to PU999 SA00002O600 S IC APW7138NITRL SSOP 16P
12
13
14
B B
15
16
17
18
19
20
A A
21
2 5090@1
C603 C593 C569 R342 680_0402_5%
1 1 1
15P_0402_50V8J: SE071150J80
12P_0402_50V8J: SE071120J80
VGA
2 1
U34 L47 DIS@ 0_0805_5%
PARK XT M2 A11: SA00003MC10 2 1
PARK@ L40 DIS@ 0_0805_5%
2 1
216-0774007 A11 PARK XT M2 L38 DIS@ 0_0805_5% PCH SKU Option
2 2
2 1
0_0805_5%: SD002000080 R259 10K_0402_5% GPIO19
UMAO@
PCB
ZZZ LA-5891P MB Rev0: DA80000H700
LA-5891P MB Rev1: DA80000H710
LA-5891P MB with Small Board Rev1: DAZ0C900100
LA-5891P REV1 M/B
X76
ZZZ
ZZZ
ZZZ
ZZZ
X765@
X76198BOL05 VRAM 512M AMD NEW70
4 AMD :SA00003PF10 4
ZZZ