DIgSILENT Technical Documentation

ABB REL 511

Power Factory
Relay model description
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ABB REL 511

Power Factory
Relay model description

Published by
DIgSILENT GmbH, Germany

Copyright 2011. All rights

reserved. Unauthorised copying
or publishing of this or any part
of this document is prohibited.

doc.TechRef, Build 524 18 Juli 2011

 Table of Contents

Table of Contents

1 MODEL GENERAL DESCRIPTION ........................................................................................................................... 4

2 RELAY NOT SUPPORTED FEATURES ...................................................................................................................... 6

3 REFERENCE MATERIAL ......................................................................................................................................... 7

ABB REL 511 Power Factory relay model description 3

 2 Relay not supported features

1 Model general description

The ABB REL 511 relay model consists of a main relay model and 8 sub relays:

- EF4
- IOC
- TEF
- TOC
- TOC2
- TOC3
- Voltage
- WEF1

The main relay contains the sub relays, the measurement elements, the starting element, the polarizing elements, the
directional element for the distance elements and the output logic.

More in detail the following functionalities are modelled in the main relay.

 Two measurement units (“Measure” and “Delta Measure” block). Please don’t forget to insert the nominal current and
the nominal voltage in all blocks.
 One starting unit implementing the phase selection logic (“Starting” block)
 One directional element (“Dir-Z” block).

 One power swing unit (“Power Swing” block)

 Two polarizing blocks (“Polarizing” and”Polarizing20” block). Please note that no user input is usually needed in these
blocks.

 Five trips zone for the phase loops each of them associated to a timer(“Z1P” and “ZT1P”, “Z2P” and “ZT2P”, “Z3P”
and “ZT3P”, “Z4P” and “ZT4P” , “Z5P” and “ZT5P”block)

 Five trips zone for the ground loops each of them associated to a timer(“Z1G” and “ZT1G”, “Z2G” and “ZT2G”, “Z3G”
and “ZT3G”, “Z4G” and “ZT4G” , “Z5G” and “ZT5G”block)

 One trip logic unit (“Output Logic” block)

The following functionalities are modelled in the subrelays:

“EF4” sub relay:

 Three directional time defined zero sequence overcurrent elements (“EF4 Step 1”, “EF4 Step 2” and ”EF4 Step 3”,
block)
 One directional inverse characteristic zero sequence overcurrent element with minimum activation threshold and
additional trip delay (“EF4 Step 4”, “EF4 tLow” and “EF4 Step 4 Imin” block)

“IOC” sub relay:

 One time defined phase overcurrent element (“Ioc Phase” block)
 One time defined residual overcurrent element (“Ioc residual” block)

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 2 Relay not supported features

“TEF” sub relay:

 One directional inverse characteristic zero sequence overcurrent element with minimum activation threshold and
additional trip delay (“TEF”, “TEF tLow” and “TEF Imin” block)

“TOC” subrelay:
 One inverse characteristic phase overcurrent element (“TOC Phase” block)
 One inverse characteristic residual overcurrent element (“TOC Residual” block)

“TOC2” sub relay:

 One not directional inverse characteristic phase overcurrent element with minimum activation threshold and
additional trip delay (“Toc2”, “Toc2 tLow” and “Toc2 I>Low” block)
 One time defined phase overcurrent element (“Toc2 I>High” block)

“TOC3” sub relay:

 One not directional inverse characteristic phase overcurrent element with minimum activation threshold and
additional trip delay (“Toc3”, “Toc3 tLow” and “Toc3 I>Low” block)
 One time defined phase overcurrent element (“Toc3 I>High” block)

“Voltage” sub relay:

 One phase overvoltage time defined element (“TOV Phase” block)
 One zero sequence overvoltage time defined element (“TOV Ground” block)
 One phase undervoltage time defined element (“TUV Phase” block)

“WEF1” sub relay:

 One directional time defined characteristic zero sequence overcurrent element (“WEF1 Dir” and “WEF1 delay” block)

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2 Relay not supported features

The following features are not supported:

 scheme communication logic for residual overcurrent protection (EFC)

 current reversal and weak end infeed logic for residual overcurrent protection (EFCA)
 thermal overloadprotection (THOL)
 pole slip protection
 radial feeder protection (PAP)
 automatic reclosing feature
 pole discordance protection (RPLD, 52 PD)
 current reversal and WEI logic for distance protection (ZCAL)
 scheme communication logic for distance protection (ZCOM)
 unbalance protection for capacitor banks (TOCC)
 breaker failure protection (BFP)
 power system and secondary system supervision
 directional sensitive power protection (WEF2)
 Loss of voltage check(LOD)
 Overload supervision (OVLD)
 Dead line detection (DLD)
 Fuse failure supervision (FUSE)
 Voltage transformer supervision (TCT)
 Synchrocheck
 broken conductor check (PTOC, 46)

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3 Reference material
The model implementation has been based on the information available in the “Technical reference manual ProtectIT Line
distance protection terminal REL 511*2.5 Document No: 1MRK 506 166-UEN Issued: November 2003” and in the “Application
manual ProtectIT Line distance protection terminal REL 511*2.5 Document No: 1MRK 506 168-UEN Issued: December 2003”
document.

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