electronics

Article
X-Type Step-Up Multi-Level Inverter with
Reduced Component Count Based on
Switched-Capacitor Concept
Erfan Azimi 1 , Aryorad Khodaparast 1 , Mohammad Javad Rostami 1 , Jafar Adabi 1, * ,
M. Ebrahim Adabi 2 , Mohammad Rezanejad 3 , Eduardo M. G. Rodrigues 4 and
Edris Pouresmaeil 5, *
1 Faculty of Electrical Engineering, Babol Noshirvani University of Technology, P.O. Box 474, Babolsar
47148-71167, Iran; Erfan.azimi.eab@gmail.com (E.A.); a.khodaparast.q@gmail.com (A.K.);
mjrostami1992@gmail.com (M.J.R.)
2 Department of Electrical Engineering, Delft University of Technology, 5031, 2600 GA Delft, The Netherlands;
ebrahim.adabi@tudelft.nl
3 Faculty of Electrical Engineering, University of Mazandaran, Babolsar 47416-13534, Iran;
m.rezanejad@umz.ac.ir
4 Management and Production Technologies of Northern Aveiro—ESAN, Estrada do Cercal 449,
Santiago de 13 Riba-Ul, 3720-509 Oliveira de Azeméis, Portugal; emgrodrigues@ua.pt
5 Department of Electrical Engineering and Automation, Aalto University, 02150 Espoo, Finland
* Correspondence: j.adabi@nit.ac.ir (J.A.); edris.pouresmaeil@aalto.fi (E.P.)




Received: 21 October 2020; Accepted: 17 November 2020; Published: 24 November 2020


Abstract: This paper aims to present a novel switched-capacitor multi-level inverter. The presented
structure generates a staircase near sinusoidal AC voltage by using a single DC source and a few
capacitors to step-up the input voltage. The nearest level control (NLC) strategy is used to control the
operation of the converter. These switching states are designed in a way that they always ensure
the self-voltage balancing of the capacitors. Low switching frequency, simple control, and inherent
bipolar output are some of the advantages of the presented inverter. Compared to other existing
topologies, the structure requires fewer circuit elements. Bi-directional power flow ability of the
proposed topology, facilitates the operation of the circuit under wide range of load behaviors which
makes it applicable in most industries. Besides, a 13-level laboratory prototype is implemented
to realize and affirm the efficacy of the MATLAB Simulink model under different load conditions.
The simulation and experimental results accredit the appropriate performance of the converter.
Finally, a theoretical efficiency of 92.73% is reached.

Keywords: multi-level inverter; self-balance; single source; bidirectional; switched capacitor

1. Introduction
Nowadays, due to the progress of power electronic devices, an increase in fossil fuel prices,
and global tendency towards emitting fewer greenhouse gases, most industries tend to utilize renewable
energy sources. Especially wind and solar energies have received a great deal of attention among
them. Various types of electrical power converters are used to connect these renewable energy sources
to the local grids, including inverters which perform the DC to AC power conversion. Multilevel
inverters (MLIs), which can generate a high-quality voltage, have become more applicable recently [1–3].
They are capable of generating near sinusoidal staircase voltage, which leads to a remarkable decrease
in voltage stresses across the switching devices (dv/dt) and total harmonic distortion (THD) of the
output. Therefore, the output filter would be reduced in size or even removed [2,4–8].

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MLIs play a significant role in applications such as fuel cells [9], solar panels [10], electric
MLIs play a significant role in applications such as fuel cells [9], solar panels [10], electric vehicles
vehicles [11], wind turbines, and connecting them to the network grid [12]. The evolution of MLIs
[11], wind turbines, and connecting them to the network grid [12]. The evolution of MLIs during time
during time is illustrated in Figure 1. As conventional MLI topologies, neutral point clamped (NPC) [13],
is illustrated in Figure 1. As conventional MLI topologies, neutral point clamped (NPC) [13], flying
flying capacitor (FC) [14], and cascaded H-bridge (CHB) [15] have some weaknesses. These topologies
capacitor (FC) [14], and cascaded H-bridge (CHB) [15] have some weaknesses. These topologies have
have a few advantages over two-level inverters such as: Less switching and conduction losses, higher
a few advantages over two-level inverters such as: Less switching and conduction losses, higher
efficiency, and remarkably more power quality. On the other hand, they suffer from sophisticated
efficiency, and remarkably more power quality. On the other hand, they suffer from sophisticated
control methods. Furthermore, NPC and FC struggle with voltage imbalance of their DC link capacitors
control methods. Furthermore, NPC and FC struggle with voltage imbalance of their DC link
and CHB requires several independent DC sources [16].
capacitors and CHB requires several independent DC sources [16].

Two Level Inverters Multi-Level Inverters

Classic application oriented topologies

MMC

CHB NPC FC Single Source SC Multi Source SC

1970s 1980s 1990s 2000s Present

 Inability to balance the voltage of

 Pulse-Shape voltage capacitors  Generating almost sinusoidal voltage
 High THD  Requiring several DC sources  Low THD
 High Voltage Stress on  Lack of redundancy in switching  Low stress voltage on each switch
each switch states  Generating low common mode voltage
 Generating High  Complexity of the control process for  Ability to operate in high/ low switching frequency
common mode voltage high voltage levels  Switching states redundancy
 Voltage amplitude reduction

Figure 1. Gradual progress of inverters’ overview.

Figure 1. Gradual progress of inverters’ overview.
Moreover, when an increase in output voltage levels (to lower the THD) is intended, the
Moreover,
semiconductor when an increase
devices in output
count will voltage
considerably levels (to
increase. Thelower the THD) is factors
above-mentioned intended, the the
restrict
semiconductor
application devices
of these count will considerably
converters increase.
in high voltage The As
levels [6]. above-mentioned factors
a result, attaining restrictpossible
maximum the
application of these converters in high voltage levels [6]. As a result, attaining maximum possible
voltage levels with the least number of DC input sources and semiconductor devices has become
voltage levels with the least number of DC input sources and semiconductor devices has become the
the main objective for experts in the field of MLIs. As an alternative, switched-capacitor multi-level
main objective for experts in the field of MLIs. As an alternative, switched-capacitor multi-level
inverters (SCMLIs) were proposed to cover these issues. In this context, many new converters were
inverters (SCMLIs) were proposed to cover these issues. In this context, many new converters were
designed to decrease the number of components such as semiconductors, DC sources, capacitors,
designed to decrease the number of components such as semiconductors, DC sources, capacitors, and
and implementation costs [4].
implementation costs [4].
The SCMLI circuits presented in [6,16], are comprised of the connection of a few DC/DC converters
The SCMLI circuits presented in [6,16], are comprised of the connection of a few DC/DC
and an H bridge to change the polarity of the output. The DC/DC part is made up of a serial connection
converters and an H bridge to change the polarity of the output. The DC/DC part is made up of a
of switched-capacitor cells. Using a single DC source and multiplying the input voltage are the main
serial connection of switched-capacitor cells. Using a single DC source and multiplying the input
advantages of these topologies [17]. However, they require many capacitors and switches, which
voltage are the main advantages of these topologies [17]. However, they require many capacitors and
increases the size, complexity, and overall cost of these structures. Furthermore, using an H bridge
switches, which increases the size, complexity, and overall cost of these structures. Furthermore,
in these circuits oblige the four switches to withstand the maximum of the output voltage [18]. As a
using an H bridge in these circuits oblige the four switches to withstand the maximum of the output
result, the need for high voltage switches restricts the application of such topologies in medium and
voltage [18]. As a result, the need for high voltage switches restricts the application of such topologies
high voltage. Hence, to overcome this concern, several step-up SCMLI with a single input source are
in medium and high voltage. Hence, to overcome this concern, several step-up SCMLI with a single
presented in [19–21]. In this case, voltage stress across the circuit elements has been reduced, which
input source are presented in [19–21]. In this case, voltage stress across the circuit elements has been
leads to the reduction of the total standing voltage (TSV) of the structure. However, the appliance of
reduced, which leads to the reduction of the total standing voltage (TSV) of the structure. However,
series diodes with switches in [19] prevents the power flow back to the source. Bidirectional power
the appliance of series diodes with switches in [19] prevents the power flow back to the source.
flow ability, prevents the capacitors from over-charging and potential damages. Ergo, the excess charge
Bidirectional power flow ability, prevents the capacitors from over-charging and potential damages.
is fed back to the input source. As a result, another crucial character for an SCMLI circuit is whether
Ergo, the excess charge is fed back to the input source. As a result, another crucial character for an
the inverter can be used in application with bi-directional power flow or not. This paper presents a
SCMLI circuit is whether the inverter can be used in application with bi-directional power flow or
novel switched-capacitor multilevel converter suitable for medium and high power usage.
not. This paper presents a novel switched-capacitor multilevel converter suitable for medium and
high power usage.
Electronics 2020,
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The proposed topology requires no external circuit or complex control algorithm to maintain its
The
capacitors’proposed
voltage topology
The proposed requires
balance. The
topology no
no external
voltage
requires boostingcircuit
external or
or complex
and reducing
circuit control
control algorithm
the semiconductor
complex algorithm to
to maintain
devices its
count are
maintain its
capacitors’
the advantages
capacitors’ voltage
voltage balance.
of the The
presented
balance. voltage
structure
The voltage boosting and reducing
over conventional
boosting the semiconductor
and reducingtopologies. devices
Since thedevices
the semiconductor proposed count are
circuit
count are
the
the advantages
inherently
advantages of
of the
generates theapresented structure
bipolar voltage
presented over
without
structure conventional
over using topologies.
an H-bridge,
conventional Since the
the switching
topologies. Since thelosses
proposed circuit
and voltage
proposed circuit
inherently
stresses generates
across the a bipolar
semiconductor voltage without
devices are using
reduced an H-bridge,
considerably. the switching
inherently generates a bipolar voltage without using an H-bridge, the switching losses and voltage losses and voltage
stresses
Theacross
stresses rest of
across the semiconductor
thethis devices
paper is organized
semiconductor devicesas are reduced
arefollows: considerably.
reducedSection 2 describes the proposed structure, its
considerably.
The
operating rest
The rest of this
of this paper
principles, paperisisorganized
capacitors organized
charging as asfollows:
paths,follows:
and the Section 2 describes
modulation
Section thethe
strategy
2 describes in proposed
detail.
proposed structure,
Astructure,
comparative its
its operating
study, along principles,
with the capacitors
determinationcharging
of the paths,
circuitand the modulation
capacitances, powerstrategy
loss in detail.
analysis,
operating principles, capacitors charging paths, and the modulation strategy in detail. A comparative A comparative
and efficiency
study,
study, along
along with
calculations are the
the determination
withcarried out in Section
determination of
of the 3. circuit
the Then, capacitances,
circuit the simulation
capacitances, power loss
and loss
power analysis,
experimental
analysis, andand efficiency
results of the
efficiency
calculations
proposed are
invertercarried
are out in
brought Section
in 3.
Section Then,
4. At the simulation
last, conclusionandofexperimental
calculations are carried out in Section 3. Then, the simulation and experimental results of5.the
this paper is results
added of
to the proposed
Section
inverter
proposedare brought
inverter areinbrought
Section in
4. At last, conclusion
Section of this paper
4. At last, conclusion is added
of this papertoisSection
added to 5. Section 5.
2. Proposed Topology: Structure and Operating Principals
2. Proposed Topology:
2. Proposed Topology: Structure and and Operating Principals
Principals
Figure 2 depicts Structure
the proposed Operating
switched capacitor topology. This circuit structure uses 3
Figure
capacitors 22depicts
Figureand depictsthethe
a single proposed
DC sourceswitched
proposed boostcapacitor
to switched
the inputtopology.
voltage
capacitor 6This circuit
times
topology. andstructure
This generate
circuit uses 3 capacitors
13 levels
structure in the
uses 3
and a
output.single DC
Likewise,source
it to boost
consists the
of input
15 voltage
power 6 times
switches and generate
(including 13
13 levels in the output.
uni-directional
capacitors and a single DC source to boost the input voltage 6 times and generate 13 levels in the and Likewise,
one bi-
it consists
directional)
output. ofand
15 power
Likewise, 14 it switches
driving of(including
circuits
consists to form
15 power13 uni-directional
theswitches and
required (including
current one
13 bi-directional)
paths. uni-directionalandand14 one
driving
bi-
circuits to form the required current paths.
directional) and 14 driving circuits to form the required current paths.
S1 S8 S11 S13
S1 C 1 S6 S8 S11 S13
C1 S4 S6 +
S4 +
a S3 S10 C3 3Vin b
VinS10 C3 3Vin
a S3 Vin b
-
S5
C2 S5 S7 -
S2 C2 S7 S9 S12 S14
S2 S9 S12 S14
Figure 2. Schematic of the proposed X-Type (13-level prototype).
Figure 2. Schematic of the proposed X-Type (13-level prototype).
Figure 2. Schematic of the proposed X-Type (13-level prototype).
Eachlevel
Each levelofofthethe staircase
staircase outputoutput voltage
voltage is achieved
is achieved by a predetermined
by a predetermined combinationcombination of
of capacitors
capacitors
and/orEach and/or
level
the DC ofthe
source.theDC source. A
A staircase
high-quality high-quality
output can voltage
voltage
voltage can be
beisobtained
achieved obtained
by provided
a predetermined
provided that: that: Allare
capacitors
combination
All capacitors of
charged
are charged
capacitors and/or
sufficiently, sufficiently,
the DC
voltages voltages
source.
of the of the capacitors
A high-quality
capacitors and
voltage
and voltages voltages
can the
across across
be obtained the switches
switchesprovided
does not that:does
exceed not
Alltheir exceed
capacitors
rated
values and the capacitors’ voltage drop remains in an acceptable range [22]. As shown in Figure in
their
are rated
charged values and
sufficiently,the capacitors’
voltages of voltage
the drop
capacitors remains
and in
voltages an acceptable
across the range
switches [22].
does As shown
not exceed
3,
Figure
their 3, Cvalues
rated 1 and Cand
2 arethe
charged directly
capacitors’ by thedrop
voltage inputremains
source up to acceptable
in an Vdc. Capacitor C3 can
range [22].beAscharged
shown up
in
C 1 and C2 are charged directly by the input source up to Vdc . Capacitor C3 can be charged up to 3Vdc
to 3V
Figure
by byCa1combination
dc 3,
a series series
and C2combination
of C1 , Cof
are charged C1, C2,by
directly and
theDC source
input (Figure
source up to3c).
Vdc. Capacitor C3 can be charged up
2 , and DC source (Figure 3c).
to 3Vdc by a series combination of C1, C2, and DC source (Figure 3c).

C1 C1
+ +
C1 C1
a C3 +3Vin b a C3 +3Vin b
Vin Vin
a C3 3V
- in b a C3 3V
- in b
Vin Vin
C2 C2
- -
C2 C2

(a) (b)
(a) Figure 3. Cont. (b)
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Electronics 2020, 9, 1987 4 of 18

C1
+

a C3 3Vin b
Vin
-
C2

(c)
Figure 3. Charging path for (a) C1 , (b) C2 , and (c) C3.

Table 1 brings the switching states and their relevant capacitors’ state of charge. In addition,
charging, discharging, and no change states of the circuit capacitors are shown by “N”, “H”,
and “-”, respectively.

Table 1. Corresponding switching states of the proposed circuit.

State Active Switches Output Voltage C1 C2 C3

Figure 3. Charging path for (a) C1, (b) C2, and (c) C3.
1 S1 ,S4 ,S5 ,S9 ,S10 ,S11 ,S14 +6Vdc H H H

Table 21 brings the

S1 ,S3switching
,S4 ,S7 ,S9 ,S10states +5Vdc
,S11 ,S14and their relevant H state ofNcharge. InH addition,
capacitors’
3
charging, discharging, S1 ,S 3 ,S5no
and ,S6 ,Schange
9 ,S10 ,S11states +5Vdc capacitors are
,S14 of the circuit N shown H H
by “▲”, “▼”, and “-
”, respectively.
4 S1 ,S6 ,S7 ,S9 ,S10 ,S11 ,S14 +4Vdc - - H
5 S1 ,S4 ,S5 ,S8 ,S9 ,S11 ,S12 ,S14 +3Vdc H H N
Table 1. Corresponding switching states of the proposed circuit.
6 S1 ,S3 ,S4 ,S7 ,S9 ,S12 ,S14 +2Vdc H N -
7 State
S1 ,S3 ,S5 Active
,S6 ,S9 ,S12Switches,S14 Output
+2Vdc Voltage C N 1 C2 CH3 -
1 S1,S4,S5,S9,S10,S11,S14 +6Vdc ▼ ▼ ▼
8 S1 ,S6 ,S7 ,S9 ,S12 +1Vdc - - -
2 S1,S3,S4,S7,S9,S10,S11,S14 +5Vdc ▼ ▲ ▼
9 S1 ,S4 ,S5 ,S8 ,S9 ,S11 ,S12 ,S13 0 H H N
3 S1,S3,S5,S6,S9,S10,S11,S14 +5Vdc ▲ ▼ ▼
10 S42 ,S4 ,S5 ,SS81,S
,S96,S,S11 ,S,S,S
7,S912 10,S1411,S14 0 +4Vdc H- - ▼ H N
11 5 S2 ,SS6 ,S1,S7 ,S
4,S 8 ,S
5,S ,S13
118,S 9,S11,S12,S14 −1Vdc
+3Vdc ▼- ▼ ▲ - -
12 6S2 ,S3 ,S5S,S1,S 3,S
6 ,S 4,S
8 ,S 117,S,S139,S12,S14 +2Vdc
−2Vdc ▼
N ▲ H - -
13 7 S ,S ,S
S2 ,S3 ,S4 ,S7 ,S8 ,S11 ,S13
1 3 5 ,S 6 ,S 9 ,S 12 ,S 14 +2V
−2Vdc dc ▲
H ▼ N- -
14 8 S 1,S6,S7,S9,S12
S2 ,S4 ,S5 ,S8 ,S9 ,S11 ,S12 ,S13 +1V
−3Vdc dc
H - - H- N
9 S1,S4,S5,S8,S9,S11,S12,S13 0 ▼ ▼ ▲
15 S2 ,S6 ,S7 ,S8 ,S10 ,S12 ,S13 −4Vdc - - H
10 S2,S4,S5,S8,S9,S11,S12,S14 0 ▼ ▼ ▲
16 S2 ,S3 ,S5 ,S6 ,S8 ,S10 ,S12 ,S13 −5Vdc N - -
11 S2,S6,S7,S8,S11,S13 −1Vdc - - -
17 12S2 ,S3 ,S4S,S28,S,S310,S,S5,S
,S13
126,S 8,S11,S13
−5Vdc
−2Vdc H
▲ ▼ N - H
18 13S2 ,S4 ,S5S,S28,S,S310,S,S4,S ,S13
127,S 8,S11,S13 −6Vdc
−2Vdc ▼
H ▲ H - H
14 S2,S4,S5,S8,S9,S11,S12,S13 −3Vdc ▼ ▼ ▲
15 S ,S ,S ,S ,S
The procedure of generating voltage levels is as follows:
2 6 7 8 10 ,S 12 ,S 13 −4V dc - - ▼
16 S2,S3,S5,S6,S8,S10,S12,S13 −5Vdc ▲ - -
• Level +6Vdc : Figure 4a illustrates the current path for generating this ▼ level.
▲ Capacitors
▼ C1 , C2 , and
17 S2,S3,S4,S8,S10,S12,S13 −5Vdc
C3 are discharged across the load in series with the input source.
18 S2,S4,S5,S8,S10,S12,S13 −6Vdc ▼ ▼ ▼
• Level +5Vdc : Two different switching states can be used to make this level. One is through the
series connection
The procedure ofofgenerating
C1 , C3 , and DC source
voltage levels while
is ascharging
follows: C2 simultaneously. The other is through
series connection of C2 , C3 , and DC source while charging C1 simultaneously.
•• Level +4V
Level +6Vdc: :Figure 4a illustrates the current path for generating this level. Capacitors C1, C2, and
dc C3 and DC source make this level together.
C3 are discharged across the load in series with the input source.
• Level +3Vdc : This level is built with the help of C1 and C2 along with the DC source. Moreover,
• Level +5Vdc: Two different switching states can be used to make this level. One is through the
C3 can be charged at the same time.
series connection of C1, C3, and DC source while charging C2 simultaneously. The other is
through series connection of C2, C3, and DC source while charging C1 simultaneously.
 Electronics 2020, 9, x FOR PEER REVIEW 5 of 18

• Level
Electronics +4V
2020, 9, dc:
1987 C3 and DC source make this level together. 5 of 18
• Level +3Vdc: This level is built with the help of C1 and C2 along with the DC source. Moreover, C3
can be charged at the same time.
• • Level +2V
Level dc :dcTo
+2V : Tomake
makethis thislevel,
level,there
thereare are two twoswitching
switching states. First,
states. C1Cis1 is
First, discharged
dischargedacross
across thethe
load with the DC source and at the same time C is charged. Second,
load with the DC source and at the same time2 C2 is charged. Second, the capacitor2C2 and the the capacitor C and the
input source
input source supply
supply thethe
load and
load and simultaneously
simultaneously C1Cis1 charged.
is charged.
• • Level +1V
Level +1V dc dc: The voltage source is only used to makethis
: The voltage source is only used to make thisvoltage
voltagelevel
level(Figure
(Figure4b).
4b).
• • Level zero: There are two switching states to form the level
Level zero: There are two switching states to form the level zero: First by turning zero: First by turning thethe
S1 ,SS18, ,SS8,11S,11,
and S switches on. Second using the switches S , S , S , and S
and13S13 switches on. Second using the switches2 S29, S9,12S12, and14S14. Moreover, 3C3 can be . Moreover, C can be charged
charged
through
throughthethe C1C,C , 2and
1, 2C DC
, and DC source,
source, asas
shownshown ininFigure
Figure 4c.4c.
• • Negative
Negative voltage
voltage levels
levels −1V
of of −1V , −2Vdcdc,, ....,
dc ,dc−2V . . ,−6V
−6V are
dc dc are obtained
obtained similarly.
similarly.

C1 C1
+ +

a C3 3Vin b a C3 3Vin b
Vin Vin
- -
C2 C2

(a) (b)

C1 C1
+ +

a C3 3Vin b a C3 3Vin b
Vin Vin
- -
C2 C2

(c) (d)
Figure 4. Current paths for generating different voltage levels (a) +6Vdc , (b) +1Vdc , (c) zero, (d) −3Vdc .

Figure 4. Strategy
2.1. Modulation Current paths for generating different voltage levels (a) +6Vdc, (b) +1Vdc, (c) zero, (d) −3Vdc.

2.1.Figure 5a shows
Modulation the control procedure of producing a near sinusoidal waveform, with a 50 Hz
Strategy
reference frequency. The switching angles ti (i = 0, 1, 2, . . . , n) are selected based on nearest level
controlFigure
(NLC) 5a shows Then,
method. the control procedure
by applying theseofpredetermined
producing a near timesinusoidal waveform,
intervals to the circuitwith
withatheir
50 Hz
reference frequency. The switching angles ti (i = 0, 1, 2, ..., n) are selected based on nearest level control
corresponding switching states, the desired output waveform is shaped. This strategy tracks the closest
(NLC)level
voltage method.
of the Then,
sampleby applying
staircase these predetermined
waveform to the referencetime [23]. intervals to the circuit with their
corresponding
By using thisswitching
method, thestates,
timetheintervals
desired of output waveform
each voltage is to
level shaped.
produceThis
thestrategy
desiredtracks
outputthe
closest voltage level of the sample staircase waveform to the reference [23].
voltage is estimated. Then, using the switching states of Table 1 and based on the charging and
discharging modes of the capacitors, the appropriate switching state for making each voltage level is
selected (Figure 5b) [20].
Electronics 2020, 9, x FOR PEER REVIEW 6 of 18

6 Vdc6
Vsampled

Electronics 2020,
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2020, 9, FOR PEER REVIEW 66 of
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18
5 Vdc 5

Output Voltage Output Voltage

Vrefrence
4 Vdc4
6 Vdc6
Vsampled
3 Vdc3
5 Vdc 5 Sample Time Ts
2 Vdc2 Vrefrence
4 Vdc4 V= Vdc round (Vref/ Vc)
Vdc/2
Vdc1
3 Vdc3
Sample Time Ts
0
2 Vdc2 ti 5
V= Vdc round (Vref/ Vc)
(a)
Vdc/2
Vdc1

0
ti 5

(a)

(b)

Figure 5. Nearest level control (NLC) method for the proposed 13-level switched-capacitor multi-
level inverter (SCMLI) (a) NLC scheme waveform and (b) logic.

By using this method, the time intervals of each (b) voltage level to produce the desired output
voltage is estimated. Then, using the switching states of Table 1 and based on the charging and
discharging Nearestoflevel
Figure 5.modes
Figure the control
level control(NLC) method
(NLC)
capacitors, the forfor
method thethe
appropriate proposed
proposed
switching 13-level switched-capacitor
13-level
state multi-level
forswitched-capacitor multi-
making each voltage level is
inverter
level (SCMLI)
inverter (a) NLC
(SCMLI) (a) scheme
NLC waveform
scheme and (b)
waveform and logic.
(b) logic.
selected (Figure 5b) [20].
2.2. Extended Topology
By usingTopology
2.2. Extended this method, the time intervals of each voltage level to produce the desired output
voltage is estimated.
The proposed X-Type Then, topology
using thecan switching statesinofcase
be extended Table 1 and output
a higher based on the charging
is required. and
For high
The
discharging proposed X-Type topology
modes of theancapacitors,
power AC application, extensionthe can be extended
for appropriate in case
switching
the simple module a higher output
state for making
is introduced is required.
each voltage
to achieve For high
level is
higher voltage
power AC
selected
levels. application,
(Figure
So that, 5b)use
by anaextension
[20].of single inputfor source
the simple
and module
(𝑛 n3 + 1)iscapacitors,
introduced(2n to +
achieve higher
1) voltage voltage
levels can
levels. So that, by use of a single input source
be generated. It depends on the type of application and and ( + 1) capacitors, (2n + 1) voltage levels
the output voltage required. In some cases, can be
3
2.2.
the Extended
generated. ItTopology
input source depends on the
is capable of type of application
supplying and load
the required the output
currentvoltage
in highrequired. In some cases,
voltage application. the
Hence,
input source
Figure 6 versionis capable
is of supplying
preferred. Moreover, thewhen
required loadDC
multiple current
sources in are
high voltage such
available application.
as solar Hence,
panels,
The proposed X-Type topology can be extended in case a higher output is required. For high
Figure
this can6beversion
a veryisgood
preferred.
option Moreover,
to collect when multiple DC sources are
andavailable such toas each
solarother
panels,
power AC application, an extension forall
theof simple
the lowmodule
voltage panels
is introduced connect them
to achieve higher voltagein
this can
order to be
reacha very good
higher AC option
outputtovoltages
collect allinof the stand-alone
both low𝑛 voltage and panels and
grid connect application.
connected them to each other
levels. So that, by use of a single input source and ( + 1) capacitors, (2n + 1) voltage levels can be
in order to reach higher AC output voltages in both 3stand-alone and grid connected application.
generated. It depends on the type of application and the output voltage required. In some cases, the
input source is capable of supplying the required load current in high voltage application. Hence,
Figure 6 version is preferred. Moreover, when multiple DC sources are available such as solar panels,
this can be a very good option to collect all of the low voltage + panels and connect+ them to each other
in order to reach higher AC output voltages in both stand-alone and grid connected application.
a Vin 3Vin 3Vin b
- -

+ +

a Vin 3Vin 3Vin b

Figure 6. Schematic of the extended
-
X-Type structure.
structure. -

Moreover, as some applications normally use low voltage DC sources, high amounts of currents
are drawn from the sources in the case of single DC source when a boost AC output voltage is required.
This may limit the power ranges of SCMLIs due to high current ratings of some power semiconductors.
Figure 6. Schematic of the extended X-Type structure.
Electronics 2020, 9, x FOR PEER REVIEW 7 of 18

Moreover, as some applications normally use low voltage DC sources, high amounts of currents
are drawn
Electronics from
2020, the
sources in the case of single DC source when a boost AC output voltage
9, 1987 is
7 of 18
required. This may limit the power ranges of SCMLIs due to high current ratings of some power
semiconductors. This problem can be solved by using multiple DC sources to split the amount of
This problem can be solved by using multiple DC sources to split the amount of input current between
input current between different sources and different semiconductors. On the other hand, size of
different sources and different semiconductors. On the other hand, size of capacitors reduces as they are
capacitors reduces as they are able to balance their voltage using paths through more DC sources. It
able to balance their voltage using paths through more DC sources. It seems that hybrid SCMLI with
seems that hybrid SCMLI with multiple DC sources is an intermediate solution for the drawbacks of
multiple DC sources is an intermediate solution for the drawbacks of single DC source SCMLI (high
single DC source SCMLI (high current ratings at high power application) and cascaded MLIs (high
current ratings at high power application) and cascaded MLIs (high number of DC sources). Besides,
number of DC sources). Besides, by modular connection of SC cells, voltage of last cells may reduce.
by modular connection of SC cells, voltage of last cells may reduce. To achieve higher output voltages,
To achieve higher output voltages, it is needed to add some DC sources between the modules to keep
it is needed to add some DC sources between the modules to keep the voltage in an acceptable range.
the voltage in an acceptable range.
To overcome these problems, as shown in Figure 7, several basic SCMLI units of Figure 2 can
To overcome these problems, as shown in Figure 7, several basic SCMLI units of Figure 2 can be
be cascaded to achieve higher output voltage levels. This method would be useful where a few DC
cascaded to achieve higher output voltage levels. This method would be useful where a few DC
sources or DC links are accessible. The amount of different DC sources can be equal or asymmetric
sources or DC links are accessible. The amount of different DC sources can be equal or asymmetric
which depends on the number of required voltage levels and the type of application.
which depends on the number of required voltage levels and the type of application.

a V1 V2 Vk b

1st Cell 2nd Cell kth Cell

Figure 7. Circuit expansion of the proposed multilevel inverter (MLI).

Figure 7. Circuit expansion of the proposed multilevel inverter (MLI).
In the context of step-up SCMLI in a real application, it is essential to design a topology to use
In thepossible
maximum context standard
of step-uprating
SCMLI in aswitches.
of the real application, it is
Therefore, theessential to design
input voltage a topology
should be raisedtountil
use
maximum possible standard rating of the switches. Therefore, the input voltage should
the peak inverse voltage (PIV) is less than a certain acceptable range percentage (x%) of the switchesbe raised
until the
rated peak(Vinverse
voltage SW ) as voltage (PIV)
PIV < x%V SW is. less than a certain acceptable range percentage (x%) of the
rated 𝑆𝑊 rated 𝑆𝑊
switches rated voltage (𝑉𝑟𝑎𝑡𝑒𝑑 ) as PIV < x%𝑉𝑟𝑎𝑡𝑒𝑑 .
3. Discussion
3. Discussion
3.1. Determination of Capacitance
3.1. Determination of Capacitance
The voltage drop of the circuit capacitors in a switched capacitor converter (due to repeated
The and
charging voltage drop of cycles)
discharging the circuit capacitors
should in acceptable
stay in an a switchedrange.
capacitor
The converter (due
scale of this to repeated
range depends
charging
on and discharging
the capacitance, cycles)
discharge time,should stay
and the in an
load acceptable
current. range. The
The smaller scale ofthe
the ripple, thislower
rangethe
depends
power
on the and
losses capacitance, discharge
the higher time, and
the capacitors’ the load[21,24].
efficiency current.The
Themaximum
smaller thedischarge
ripple, the lower
rate (∆Q)the power
for each
losses andisthe
capacitor the capacitors’ efficiency [21,24]. The maximum discharge rate ( Q ) for each
higherby:
obtained
capacitor is obtained by: Zt f
∆Q = t Iout sin(2π fre f t)dt (1)
f

Q  ts I out sin(2 f ref t ) dt (1)

where, fref is the output frequency and Iout tis s the amplitude of the load current. Besides, [ts , tf ] is

the longest possible time interval in which each capacitor is discharged, assuming the worst case [2].
where, fref is the output frequency and Iout is the amplitude of the load current. Besides, [ts, tf] is the
On the other hand, the maximum output current can be calculated by:
longest possible time interval in which each capacitor is discharged, assuming the worst case [2]. On
the other hand, the maximum output current can V be calculated 6Vinby:
Iload−max = load−max = (2)
VloadR max 6VRin
I  max   (2)
Note that the capacitances C1 andload C2 are the same.R As the R voltage of C3 is three times the input,
then its capacitance is one third of the other two capacitors. Then, the maximum discharge rate can be
Note that the capacitances C1 and C2 are the same. As the voltage of C3 is three times the input,
achieved by:
then its capacitance is one third of the other two capacitors. Then, the maximum discharge rate can
Zt f Zt f
be achieved by: 6Vin
∆Q = Iload−max sin(2π fre f t)dt = sin(2π fre f t)dt (3)
R
ts ts
Electronics 2020, 9, x FOR PEER REVIEW 8 of 18

tf tf
6Vin
Q   I load  max .sin(2 . f ref .t )dt   .sin(2 . f ref .t )dt (3)
Electronics 2020, 9, 1987 ts ts
R 8 of 18

Taking k as the acceptable ripple percentage (or ripple curtailment), the capacitance is obtained
Taking k as the acceptable ripple percentage (or ripple curtailment), the capacitance is obtained as
as follows:
follows:
Qc ∆Qc 6 6 t f tf

Z
Ceq Ceq ≥
KV
 ⇒CeqCeq ≥ kR sin(2  .fref ref
sin(2π f t) .dt
t ). dt (4)(4)
K .Vin in k .R ts ts
Since Ceq is formed by the series connection of the three capacitors, its capacitance is one fifth of
Since Ceq is formed
C1 . Accordingly, by the series
the variation of the connection
determinedof the three capacitors,
capacitance versus the its loadcapacitance is one
(R) changes withfifth of
regard
Cto1. the
Accordingly, the variation of the determined capacitance
ripple curtailment is illustrated in Figure 8. versus the load (R) changes with regard
to the ripple curtailment is illustrated in Figure 8.

(a)

(b)
Figure 8.
Figure Capacitance curve
8. Capacitance curve versus
versus load
load and
and ripple
ripple constraint
constraint for
for (a)
(a) C
C11 and
and C
C22and
and(b)
(b)CC3.3 .

3.2. Power Loss Analysis

3.2. Power Loss Analysis
Generally, power loss in switched-capacitor converters are classified into three groups: switching
Generally, power loss in switched-capacitor converters are classified into three groups:
loss, conduction loss, and the loss caused by capacitor voltage ripple [2,20,25,26].
switching loss, conduction loss, and the loss caused by capacitor voltage ripple [2,20,25,26].
3.2.1. Switching Losses
3.2.1. Switching Losses
Switching loss caused by a delay in switch’s turn-on and turn-off time, is one of the major
Switching for
contributions lossthe
caused
powerbyloss.
a delay in switch’s turn-on
Semiconductors andkind
have this turn-off time,
of loss is one of the
intrinsically. When major
the
contributions for the power loss. Semiconductors have this kind of loss intrinsically.
Semiconductor switch turns on, gate-emitter voltage reaches the threshold voltage and also the When the
Semiconductor
collector current switch turnsand
increases on,collector-emitter
gate-emitter voltage reaches
voltage the threshold
has a downward voltage
trend until and also the
it reaches the
collector current increases and collector-emitter voltage has a downward trend until it
on-state voltage of the switch that shows the turn on cycle is over. Similarly, in an opposite way inreaches the
on-state
turn-off voltage
cycle and of at
thethe
switch
end ofthat showscycle,
turn-off the turn on cycle is
gate-emitter over. Similarly,
reaches in anvoltage.
the saturation oppositeCollector
way in
Electronics 2020, 9, 1987 9 of 18

current and emitter voltage rise and finally the turn-off process ends [27]. Turn-on and turn-off loss for
active switches is calculated by Equations (5) and (6).
R ton R ton  I  −Vo f f −state 
on−state
Ps,on = fs 0
Vo f f −state (t)is (t)dt = fs 0 ton t t ( t − t )
on dt
of f (5)
1
= 6 fs Vo f f −state Ion−state ton

R to f f R to f f  Vo f f −state  −I 
on−state
Ps,o f f = fs 0
Vo f f −state (t)is (t)dt = fs 0 t t t ( t − to f f ) dt
of f of f (6)
1
= 6 Vo f f −state Ion−state to f f
f s

where, Voff-state and Ion-state are off-state voltage and switch current when the switch becomes fully
turned on, respectively. Switching losses which is the sum of turn-on and turn-off loss is calculated by
Equation (7):
NXswitch  
Psw = Psj,on + Psj,o f f (7)
j=1

3.2.2. Conduction Losses

Conduction loss for power switches and power diodes is calculated by [2,23]:

sw D
Pcon−L = (k1 Von + k2 Von )iav−L + (k1 Rsw D 2
on + k2 Ron )irms−L (8)

sw , V D are the on-state voltage of switch and the on-state voltage of diode, respectively.
where, Von on
Additionally, Rsw D
on is on-state resistance of switches and Ron is on-state resistance of diode [22,25].
The parasitic resistance of the circuit elements in each level (Vj = 0, ±1Vin , ±2Vin , ±3Vin , ±4Vin , ±5Vin ,
and ±6Vin ) are listed in Table 2. Irms and Iavg are the root mean square (RMS) and average current of
semiconductors that obtain from Equation (9). It should be noted that k1 and k2 are the number of the
switches which have been shown in this table.
s
2 tb 2 tb
Z Z
iav (nVdc ) = [Im sin tdt] , irms (nVdc ) = (Im sin t)2 dt (9)
π ta π ta

Table 2. Equivalent parasitic resistance for each level.

Output Voltage Level Equivalent Parasitic Resistance

0 6Ron sw + 1Ron D
±1Vin 3Ron sw + 3Ron D
±2Vin 4Ron sw + 3Ron D
±3Vin 6Ron sw + 2Ron D
±4Vin 5Ron sw + 2Ron D
±5Vin 6Ron sw + 2Ron D
±6Vin 7Ron sw

Finally, the total conduction losses for the proposed 13-level X-Type inverter can be calculated by:

6
X −6
X
(kV ) (mVdc )
Ptotal
con = 2 Pcon dc + 2 Pcon (10)
k =1 m=−1
Electronics 2020, 9, 1987 10 of 18

3.2.3. Losses Due to the Capacitors Voltage Ripple

The difference between the input DC voltage and the capacitor voltage is the essential of the
capacitor ripple loss [19]. The ripple of the capacitor’s voltage obtained from:
Z td
1
∆Vripple,C = iC (t)dt (11)
C tc

It is worth mentioning Ic is the capacitor current and [tc , td ] is the discharge time of the capacitor
that the period of discharge time for 13-level X-Type converter. So, the capacitor’s voltage ripples losses
obtain from Equation (12). Finally, sum of the losses and efficiency are calculated by Equation (13),
where Pin and Pout are the converter’s input and output powers, respectively.

fre f  2

PRip = Ci ∆Vripple,C (12)
2
Pout Pout
η= = (13)
Pout + PLoss Pout + PSw + PCon + PRip

3.3. Comparative Study

A comparative study is conducted between the proposed structure and several recently published
articles on single-source structures in Table 3. This comparison is based on the number of capacitors,
semiconductor devices (diodes and active switches), starter circuits, bi-directional power flow ability,
PIV, and TSV per (2n + 1) output levels.

Table 3. Comparison between the proposed converter and other topologies.

Items [21] [16] [27] [6] [19] X-Type

n
No. of Capacitors n−1 n−1 n−1 n−1 n−1 3 +1
5
No. of Switches 3n + 4 n+5 2n + 4 3n + 1 5n − 1 3n + 5
5
No. of Drivers 3n + 4 n+5 2n + 4 3n + 1 5n − 1 3n + 4
No. of Series Diodes 0 2n − 2 2n − 2 0 0 0
PIV(×VIN ) n n n n 1 3
TSV(×VIN ) 7n − 3 n2 + 6n + 4 n2 + 5n + 1 n2 5n − 1 5n + 2
2 + 5n
Polarity Generating H-bridge H-bridge H-bridge H-bridge inherent inherent
Bi-Directional
NO NO YES NO NO YES
Power Flow

According to the table, the proposed structure requires a smaller number of capacitors
(approximately one-third) to generate the same output level. The circuits introduced in [6,16,21] consist
of two parts for generating voltage levels and polarity. Therefore, they are not suitable for high-voltage
applications. However, [19] and the proposed circuit can change the polarity of the load voltage
without the need for an auxiliary circuit. Furthermore, the PIV and TSV in [19] are the lowest among
other structures; however, it uses the most semiconductor components. It should be noted that the
diodes in [16,19] limit the ability to absorb power from the load whenever it is needed.
To better understand the relative superiority of the proposed structure, the graphical comparison
of the number of semiconductors used, capacitors, and TSV for different number of output levels is
illustrated in Figure 9.
 Electronics 2020, 9, x FOR PEER REVIEW 11 of 18

To better understand the relative superiority of the proposed structure, the graphical
comparison
Electronics 2020, 9,of the number of semiconductors used, capacitors, and TSV for different number11of
1987 of 18
output levels is illustrated in Figure 9.

50
[16]
[19]
[6]

Number of Semiconductors
40 [28]

[21]
30

20 [Proposed]

10

0
0 5 10 15 20 25
Number of Levels

(a)

(b)

[16]

[28]

[6]

[21] [Proposed]

[19]

(c)

Figure 9. Comparison of the parameters in terms of number of levels, (a) number of semiconductor,
(b) capacitors, and (c) total standing voltage (TSV).
Electronics 2020, 9, x FOR PEER REVIEW 12 of 18

Figure 9. Comparison of the parameters in terms of number of levels, (a) number of semiconductor,
Electronics 2020, 9, 1987
(b) capacitors, and (c) total standing voltage (TSV). 12 of 18

4. Performance Evaluation
4. Performance Evaluation
This section presents a set of both simulation and experimental results in order to accredit the
This section presents a set of both simulation and experimental results in order to accredit the
performance and effectiveness of the proposed model for a 13-level X-Type converter.
performance and effectiveness of the proposed model for a 13-level X-Type converter.
4.1. Simulation Results
4.1. Simulation Results
To evaluate the function of the proposed 13-level X-Type converter, simulation studies are
To evaluate the function of the proposed 13-level X-Type converter, simulation studies are
conducted in MATLAB Simulink environment with the characteristics listed in Table 4.
conducted in MATLAB Simulink environment with the characteristics listed in Table 4.
Table
Table4.4.Simulation
Simulationparameters
parametersin
inMATLAB.
MATLAB.
Parameters
Parameters Values Values
Input DC Source (Vin) 30 V
Input DC Source (Vin ) 30 V
BoostRatio
Boost Ratio(n)(n) 6 6
Output frequency (fo )(fo)
Output frequency 50 Hz 50 Hz
Capacitances
Capacitances (C)(C) 1 = CµF,
C1 = C2 =C4700 2 = 4700
C3 = µF,
2200 = 2200 µF
C3 µF
Load (Z
Load (Z )
L L) 90
90 Ω, 318 mHΩ, 318 mH

It should be noted that because of using low voltage capacitors, their physical dimensions are
It should be noted that because of using low voltage capacitors, their physical dimensions are
remarkably small. Figure 10a,b displays the voltage waveform and the output current under the
remarkably small. Figure 10a,b displays the voltage waveform and the output current under the
resistive and resistive-inductive load, respectively. At inductive load, the output current is smooth.
resistive and resistive-inductive load, respectively. At inductive load, the output current is smooth.
Figure 10c shows the harmonic spectrum of the output voltage. The output’s THD is 6.42%. It can be
Figure 10c shows the harmonic spectrum of the output voltage. The output’s THD is 6.42%. It can be
seen that the amplitude of all unwanted harmonics are kept below 5% satisfying the IEEE-Std. 519-
seen that the amplitude of all unwanted harmonics are kept below 5% satisfying the IEEE-Std. 519-2014.
2014.
200 200 Voltage (V) 27×Curr ent (A)
Vo lta g e (V) 2 7× C u rren t (A)

100 100

0 0

-100
-100

-200
-200 0.94 0.95 0.96 0.97 0.98 0.99 1
0.94 0.95 0.96 0.97 0.98 0.99 1 Time(sec)

(a) (b)

(c)

Figure 10. Simulation results, (a) resistive load (ZL = 90 Ω), (b) resistive-inductive load (ZL = 90 Ω +
318 mH), and (c) harmonics spectrum.
Electronics 2020, 9, x FOR PEER REVIEW 13 of 18

Electronics 2020, 9, 1987 13 of 18

Figure 10. Simulation results, (a) resistive load (ZL = 90 Ω), (b) resistive-inductive load
(ZL = 90 Ω + 318 mH), and (c) harmonics spectrum.
In order to highlight the capability of the proposed structure in an instantaneous load change
In order
condition, the to highlightscenario
following the capability of the proposed
was implemented structure
in a way inload
that the an instantaneous loadZchange
changes between L1 and
condition, the following scenario was implemented in a way that the load changes between
ZL2 . Figure 11a shows the output current changes during instantaneous change. Likewise, during Z L1 and

Z L2. Figure 11a shows the output current changes during instantaneous change. Likewise, during this
this condition, the capacitors follow the reference voltage representing the right function of the circuit
condition,
which the capacitors
is shown follow the reference voltage representing the right function of the circuit
in Figure 11.
which is shown in Figure 11.
1

0.5
1.2 A
Iout (A)

0 1.2 A

-0.5 1.6 A

-1
1 1.5 2 2.5 3
Time (sec)
(a)
32 32

30 30
Vc1

Vc2

28 28

26 26

24 24
0.5 1 1.5 2 2.5 3 0.5 1 1.5 2 2.5 3
Time(sec)
Time(sec)
(b) (c)

90

88

86
Vc3

84

82

80
0.5 1 1.5 2 2.5 3
Time(sec)

(d)
Figure 11. Simulation results under sudden load change, (a) output current, (b) VC1 , (c) VC2 , and
(d) VC3 .
Figure 11. Simulation results under sudden load change, (a) output current, (b) VC1, (c) VC2, and (d)
VC3.
4.2. Experimental Results
Experimental
4.2. Experimental model for a 13-level converter was tested to verify the function of the circuit in the
Results
power electronics laboratory (see Figure 12a). Characteristics of the experimental model are listed
 Parameters Values
Input DC voltage (Vin) 30 V
Boost Ratio (n) 6
Output Frequency (fo) 50 Hz
Electronics 2020, 9, 1987 Capacitances (C) C1 = C2 = 4700 µ F, C3 = 2200 µ F 14 of 18

Load (ZL) 90 Ω, 318 mH

in Table 5. Switching MainpulsesSwitches (MOSFET)
were generated by AVR-ATMEGA16AIRFP460microcontroller. The switching
Opto-coupler Driver HCPL-3120
process is written in BASCOM software and loaded onto the microcontroller. Similarly, for preventing
Main Control Chip AVR ATMEGA16A
damage to the low-voltage devices, the power circuit and control circuit were isolated electrically by
Voltage Probe PINTEK DP-50
utilizing opto-coupler HCPL3120 in gate driver circuit which is shown in Figure 12b.
Current Probe FLUKE 80i-110s AC/DC

(a)

Isolated 20(v) DC Supply

0-20 v
0-5 v 0-5 v Power
Optocoupler
Buffer Switches
HCPL3120
ATM16 IC 74HC04 Vin Driver Vout

(b)
Figure 12.(a)
Figure12. (a)Experimental
Experimentalsetup
setupand
and(b)
(b)switching
switchingschematic
schematicofofmain
mainswitches
switches(MOSFETs).
(MOSFETs).
Table 5. Specifications of the proposed 13-level X-Type inverter.
Output voltage and current under resistive and resistive-inductive loads are shown in Figure
13a,b A voltage source of Parameters
30 V is considered as input. The maximum Values
output voltage is 180 V and also
each voltage step is 30 V. An
Input DCimportant
voltage (Vinfeature
) of this structure is the
30 Vcapability of boosting the input
Boost Ratio (n) 6
Output Frequency (fo ) 50 Hz
Capacitances (C) C1 = C2 = 4700 µF, C3 = 2200 µF
Load (ZL ) 90 Ω, 318 mH
Main Switches (MOSFET) IRFP460
Opto-coupler Driver HCPL-3120
Main Control Chip AVR ATMEGA16A
Voltage Probe PINTEK DP-50
Current Probe FLUKE 80i-110s AC/DC

Output voltage and current under resistive and resistive-inductive loads are shown in Figure 13a,b.
A voltage source of 30 V is considered as input. The maximum output voltage is 180 V and also each
voltage step is 30 V. An important feature of this structure is the capability of boosting the input voltage,
Electronics 2020, 9, 1987 15 of 18

Electronics 2020, 9, x FOR PEER REVIEW 15 of 18

about, six times and as an example of the voltage of the switches, the voltage across the S1 is displayed
voltage, about, six times and as an example of the voltage of the switches, the voltage across the S1 is
in Figure 13c.
displayed in Figure 13c.

Voltage (V) Current (A)

(a)

Voltage (V) Current (A)

(b)

(c)

Figure Experimental
13.13.
Figure Experimental waveforms,
waveforms, (a)(a)
resistive load
resistive load L=
(Z(Z 9090Ω),
L = Ω),(b)
(b)resistive-inductive load(ZL = 90 Ω
resistive-inductiveload
+ 318
(ZL mH),
= 90 Ωand (c)mH),
+ 318 voltage
andof
(c)Svoltage
1. of S1.
Electronics 2020, 9, 1987 16 of 18
Electronics 2020, 9, x FOR PEER REVIEW 16 of 18

The transient performance of the proposed structure is evaluated by the load changing between
The transient performance of the proposed structure is evaluated by the load changing between
ZL1 = 250 Ω and ZLP (ZLP = ZL1 || ZL2 , ZL2 = 170 Ω) sequentially. In this way, the converter is
ZL1 = 250 Ω and ZLP (ZLP = ZL1|| ZL2, ZL2 = 170 Ω) sequentially. In this way, the converter is operating
operating normally under load ZL1 and suddenly another load (ZL2 ) is connected in parallel. To better
normally under load ZL1 and suddenly another load (ZL2) is connected in parallel. To better
demonstrate the impact of such sudden load change, ZL2 is connected and disconnected repeatedly.
demonstrate the impact of such sudden load change, ZL2 is connected and disconnected repeatedly.
Figure 14 illustrates the results of the function of the converter under sudden load changes. As revealed
Figure 14 illustrates the results of the function of the converter under sudden load changes. As
in this figure, the capacitors follow the reference voltage, and their voltages fluctuate within an
revealed in this figure, the capacitors follow the reference voltage, and their voltages fluctuate within
acceptable range. So, the proposed converter has no need for any complex algorithm or external circuit
an acceptable range. So, the proposed converter has no need for any complex algorithm or external
for balancing the capacitor’s voltage.
circuit for balancing the capacitor’s voltage.

3.6 A
1.4 A

(a)

(b) (c)
Figure 14. The experimental results under sudden change in the load (a) output voltage and current,
capacitors’ voltage (b) C1 , and (c) C2 , C3 .
Figure 14. The experimental results under sudden change in the load (a) output voltage and current,
capacitors’ voltage (b) C1, and (c) C2, C3.
5. Conclusions
In this paper, a 13-level single-source inverter with boosting capability is introduced. The ability to
5. Conclusions
increase the input Voltage six times without using any inductor or transformer and also the self-balance
of theIncapacitor’s
this paper,voltage
a 13-level single-source
without the use inverter with boosting
of an external capability
controller is introduced.
are the main Theof
advantages ability
this
to increase A
converter. thecomparative
input Voltage six times
study with without usingtopologies
some recent any inductor or transformer
shows and alsostructure
that the proposed the self-
balance of
reduced thethe capacitor’s
number voltage without
of semiconductor the use of an
components external to
compared controller are the main
other structures, advantages
which would
of this converter. A comparative study with some recent topologies shows that the proposed
structure reduced the number of semiconductor components compared to other structures, which
would reduce the implementing cost. This structure has less TSV and PIV than similar structures
Electronics 2020, 9, 1987 17 of 18

reduce the implementing cost. This structure has less TSV and PIV than similar structures which
provides conditions to reach higher levels. In particular, the modulation strategy, the calculation
of the capacitance, the switching losses, and, also, conduction loss for the proposed structure have
been investigated. The efficiency of the 13-level structure presented is 92.73%, and, also, the THD
of output voltage for the proposed structure is 6.42%. Finally, experimental results of the proposed
converter, verify its correct operation under different (resistive and resistive-inductive) loads and also
instantaneous load change on the output. By analyzing the results, the proposed inverter is regarded
as a suitable choice for renewable energy applications with low number of DC sources and also it is
appropriate for voltage boosting at the output.

Author Contributions: Investigation, J.A.; methodology, E.M.G.R.; supervision, E.P.; writing—original draft
preparation, E.A., A.K., M.J.R., M.E.A. and M.R.; writing—review and editing, E.P.; All authors have read and
agreed to the published version of the manuscript.
Funding: This research received no external funding.
Conflicts of Interest: The authors declare no conflict of interest.

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