electronics

Article
An RF Approach to Modelling Gallium Nitride Power
Devices Using Parasitic Extraction
Nikita Hari 1 , Sridhar Ramasamy 2 , Mominul Ahsan 3 , Julfikar Haider 3 and
Eduardo M. G. Rodrigues 4, *
1 Centre for Photonics and Electronics, Department of Engineering, University of Cambridge,
J J Thomson Avenue, Cambridge CB3 0FA, UK; nikitahari@ieee.org
2 Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology,
Kattankulathur, Tamil Nadu 603203, India; sridharr@srmist.edu.in
3 Department of Engineering, Manchester Metropolitan University, John Dalton Building, Chester Street,
Manchester M1 5GD, UK; M.Ahsan@mmu.ac.uk (M.A.); j.haider@mmu.ac.uk (J.H.)
4 Management and Production Technologies of Northern Aveiro—ESAN, Estrada do Cercal 449,
Santiago de Riba-Ul, 3720-509 Oliveira de Azemeis, Portugal
* Correspondence: emgrodrigues@ua.pt




Received: 13 October 2020; Accepted: 11 November 2020; Published: 26 November 2020


Abstract: This paper begins with a comprehensive review into the existing GaN device models.
Secondly, it identifies the need for a more accurate GaN switching model. A simple practical process
based on radio frequency techniques using Vector Network Analyser is introduced in this paper as
an original contribution. It was applied to extract the impedances of the GaN device to develop
an efficient behavioural model. The switching behaviour of the model was validated using both
simulation and real time double pulse test experiments at 500 V, 15 A conditions. The proposed model
is much easier for power designers to handle, without the need for knowledge about the physics or
geometry of the device. The proposed model for Transphorm GaN HEMT was found to be 95.2%
more accurate when compared to the existing LT-Spice manufacturer model. This work additionally
highlights the need to adopt established RF techniques into power electronics to reduce the learning
curve while dealing with these novel high-speed switching devices.

Keywords: gallium nitride; power electronics; power device; parasitics; device modelling; switching
model; Vector Network Analyser

1. Introduction
To enable commercialisation of GaN high-speed power switching circuits, there are problems
caused by parasitics that need to be overcome. Ultra-fast dv/dt and di/dt cause significant instability
issues stemming from the inductive, capacitive, package and PCB parasitic elements [1]. With devices
having near ideal characteristics, the effect due to parasitics can have a detrimental impact on their
switching performance that can no longer be neglected.
The cause and effect of parasitics on GaN switching performance have been explored in a few
different ways in the literature. The effects of parasitics have been studied focusing on resonances
and self-sustained oscillations [2–4]. These are more pronounced for GaN circuits due to its complex
structures and operation at high frequency and current levels [5]. Thus, it is imperative that power
application designers have an idea about how to evaluate the effects of these parasitics when switching
at very high speeds. Many techniques are suggested for dealing with this issue:

1. The first method is to make use of different GaN HEMT physics models to experimentally extract
the parasitic elements of the device studying their effects [6]. Although there have been detailed

Electronics 2020, 9, 2007; doi:10.3390/electronics9122007 www.mdpi.com/journal/electronics

Electronics 2020, 9, 2007 2 of 19

studies regarding this, development of physics and analytical models are very time consuming.
There is only one major study available on behavioural model of the GaN cascode which is
discussed later on in this paper.
2. The second method is to study the effect of parasitics through experimental switching waveforms.
However, this is a highly intuitional and observational method. The validity of the experiments
depends on the accuracy of the measurement systems in use, and they mostly fail to predict the
reasons behind these observations [7,8].
3. The third method is to use software (e.g., TCAD, Ansoft or Maxwell Q3D) simulations to extract
parasitics to model the device. This requires knowledge about the physics and geometry of the
devices, which are complex and not always available to the designer. It also does not fully explain
the underlying reasons behind the observations [9].

Accurate non-linear or large-signal behavioural models for HEMTs are crucial for proper circuit
and systems design and do not exist as of now. The models that exist now are complex, preventing
the understanding of the switching behaviour for the power designer. Considering all these facts,
this paper first reviews the device and package parasitics of three different commercial GaN HEMTs.
Secondly, it introduces RF process to accurately extract the impedances of the circuit. The switching
behavioural model is then developed from the extracted parasitic impedances using a Vector Network
Analyser (VNA). Numerical simulation in LT-Spice modelling was used to demonstrate the behavioural
model. A double pulse test was performed for comparing the simulation results with experimental
results to validate the dynamic performance of the developed model. This research paper proposes a
new behavioural model of GaN for application engineers without the need for any in depth knowledge
about the physics nor geometry of the device.

2. Existing GaN Models: A Review

Although several GaN HEMT devices are reported, very few reliable device switching models
have been developed for GaN HEMTs—the proposed models are as listed in Table 1.

1. Behavioural Models: In [10], based on the Efficient Power Conversion Corporation (EPC) device
model, a small-signal SPICE model of GaN HEMT is developed. In [11], a behavioural model is
constructed with a GaN HEMT in cascode with a Si MOSFET.
2. Semi-Physics based Models: The Statz model is customised to model both static and dynamic
characteristics of GaN HEMTs based on EPC devices [12]. In [13], calorimeter measurements are
used to develop a loss model for the GaN HEMT.
3. Physics based Models: The 2-DEG charge density is measured to design an analytical model of a
GaN HEMT device [14]. Other physics-based models which takes in to account in-depth physics
of the device are presented in [15,16].
4. Numerical Models: A Sentaurus TCAD model for a GaN HEMT device is developed in [17].

Table 1. Review of existing GaN models [18].

Authors Year Type of Model Contribution Simulation Tool

Power-loss estimation for AC-AC
Okamoto [19] 2011 Behavioural SPICE
converter.
Parameter determination:
Khandelwal [20,21] 2012 Physics carrier-velocity saturation, channel ADS
length modulation and self-heating
Yigletu [22] 2013 Physics Measurement of 2DEG charge density ADS
Waldron [23] 2013 Semi-Physics Static and dynamic characteristics SPICE
Hoffmann [24] 2014 Semi-physics Electrical and RC thermal model SPICE
Huang [25] 2014 Behavioural Capacitance models Unspecified
Mantooth [26] 2015 - Review -
 Khandelwal
2012 Physics saturation, channel length modulation ADS
[20,21]
and self-heating

Yigletu [22] 2013 Physics Measurement of 2DEG charge density ADS

Waldron
Electronics 2020, 9, 2007 Semi- 3 of 19
2013 Static and dynamic characteristics SPICE
[23] Physics
Hoffmann Semi-
The above models2014 are accurate in terms of explaining
Electrical and the
RC device
thermaloperation.
model However, they are
SPICE
[24] physics
complex and not always suitable for study of dynamic/switching performance. The GaN parasitic
Huang [25] 2014 Behavioural Capacitance models Unspecified
model developed by Huang investigates the dynamic performance of the device by exploring the
Mantooth
switching performance2015 of the GaN- cascode. However, it Reviewis not generic to the other available
- GaN
[26]
device structures.
The literature survey presented in Table 1 proves that switching events are challenging to measure
The literature survey presented in Table 1 proves that switching events are challenging to
and characterise. Additionally, it is difficult to separately determine circuit-level parasitics. The existing
measure and characterise. Additionally, it is difficult to separately determine circuit-level parasitics.
models clearly fail to achieve this. Furthermore, the methods used for modelling are very time intensive
The existing models clearly fail to achieve this. Furthermore, the methods used for modelling are very
and involve many methodologies from analytical analysis to customised measurement circuitry
time intensive and involve many methodologies from analytical analysis to customised measurement
development. This paper identifies two factors that need to be resolved for developing an accurate
circuitry development. This paper identifies two factors that need to be resolved for developing an
and simple GaN behavioural model:
accurate and simple GaN behavioural model:
1.
1. Anapproximate
An approximate model
model based
based on
on the
the parasitics
parasitics of
of GaN
GaN devices
devices without
without the
the need
need for
for delving
delving into
into
the detailed physics of the structure
the detailed physics of the structure
2.
2. Extracting the
Extracting the parasitics
parasitics of
of the
the device
device using
using aa simple,
simple, practical
practical and
and accurate
accurate methodology
methodology

3. Developing
3. Developing aa GaN
GaN HEMT
HEMT Behavioural
Behavioural Model
Model
The main
The main objective
objective in
in this
this modelling
modelling is is to
to establish
establish aa predictive
predictive account
account of of the
the switching
switching voltage
voltage
and current
and current flow
flow through
through the
the GaN device as
GaN device as aa function
function of of the
the applied
applied voltages
voltages using
using the
the double
double pulse
pulse
testing experiment.
testing experiment.
For device
For device models,
models, the
the electrical
electrical variables
variables and and their
their dependencies
dependencies needsneeds toto be
be captured
captured with with
precision. The
precision. The device
device engineers
engineers consider
consider accuracy
accuracy and and simulation
simulation time
time asas crucial
crucial factors.
factors. A A simple
simple
device model generally provides fast simulation speed but compromises on the
device model generally provides fast simulation speed but compromises on the physics-based aspects physics-based aspects
of device
of device behaviour
behaviour and and simulation
simulation accuracy.
accuracy. Thus,Thus,for fordetermining
determiningthe theoperation
operationof of a device,
a device, a
a physics-based analytical model is usually used for simulation, but it is very complex
physics-based analytical model is usually used for simulation, but it is very complex to understand. to understand.
In addition,
In addition, it
it is
is tediously long and
tediously long and is is not
not practical
practical for for circuit
circuit design. Thus, the
design. Thus, the choice
choice ofof aa model
model isis
dependent on
dependent the practical
on the practical application
application forfor which
which it it is
is intended. Based on
intended. Based on these
these factors,
factors, aa basic
basic device
device
modelling procedure can be generalised, as shown in the block diagram
modelling procedure can be generalised, as shown in the block diagram of Figure 1. of Figure 1.

Figure 1. Block
Block diagram
diagram for power device modelling.

semiconductor device
For power semiconductor device models,
models, the
the intended
intended use
use is typically
typically as a power switch in
power electronics
electronics applications.
applications.Usually
Usuallyfor
forpower
powerdevices,
devices,Double-Pulse
Double-Pulse test
test (DPT)
(DPT) circuit
circuit is used
is used to
to validate the switching behaviour of the device model. Additionally, it is sometimes used for
device characterisation if the dynamic performance is of interest for the investigation. Based on the
experimental validation results, the proposed model may be either selected or rejected. If the device
model cannot be accepted, a new device model needs to be designed repeating the above process.
In this paper, the process designed for GaN HEMT modelling is as elaborated in Figure 2.
 Electronics 2020, 9, x FOR PEER REVIEW 4 of 20

validate the switching behaviour of the device model. Additionally, it is sometimes used for device
characterisation if the dynamic performance is of interest for the investigation. Based on the
experimental validation results, the proposed model may be either selected or rejected. If the device
Electronics
model2020, 9, 2007
cannot be accepted, a new device model needs to be designed repeating the above process.4In
of 19
this paper, the process designed for GaN HEMT modelling is as elaborated in Figure 2.

Figure
Figure 2. Flow
2. Flow diagram
diagram of the
of the GaNGaN device
device modelling
modelling design
design usingusing
VNAVNA measurement
measurement and results.
and DPT DPT
results.
3.1. Overview of Parasitics for a High-Voltage GaN HEMT Device
3.1. Overview of Parasitics for a High-Voltage GaN HEMT Device
In power electronics applications, the parasitic impedances of the high-speed switching device play
In power
a detrimental roleelectronics
in limiting applications,
its maximum theachievable
parasitic impedances of the
performance. high-speed
Unlike switching
commercial device
applications
playon
based a traditional
detrimentalpower role indevices,
limitingthese
its maximum
high speed achievable performance.
GaN switching devicesUnlike commercial
have their spectral
applications based on traditional power devices, these high speed GaN switching
content in the radio frequency region. This can lead to spurious and oscillatory circuit behaviour devices have their
due
spectral content
to resonances in the
excited radio
in the frequency
parasitic region. To
elements. This can lead to
investigate, spurious
analyse andand oscillatory
mitigate circuit
this unstable
behaviour
behaviour, it isdue to resonances
important excited inengineers
that application the parasitic
haveelements. To investigate,
an approximate analyse
estimation andimpedance
of these mitigate
this unstable behaviour, it is important that application engineers have an
values. Although direct measurement of impedance using LCR can be done, it is limited due approximate estimation of to
these impedance values. Although direct measurement of impedance using LCR can be done, it is
accuracy [27]. Based on the established practical efficacy of the proposed approach for RF devices,
limited due to accuracy [27]. Based on the established practical efficacy of the proposed approach for
VNA measurement is used in this work. It was validated through the demonstration of a modelling
RF devices, VNA measurement is used in this work. It was validated through the demonstration of a
study using commercially-available GaN HEMT devices. The measured impedances were validated
modelling study using commercially-available GaN HEMT devices. The measured impedances were
through switching experiments.
validated through switching experiments.
The parasitics of the enhancement mode GaN HEMTs/GITs structure are as shown in Figure 3.
As shown in Figure 4, the cascode device has an additional set of parasitic elements due to the low
voltage Si device.
The original GaN device structure was of normally ON-type and hence not preferred in power
applications due to safety and acceptability considerations. As a solution to this, the power device
engineers came up with the cascode structure to convert it into normally OFF-type. As shown in
Figure 4, a normally OFF-type low-voltage Si MOSFET (typically 30 V) is connected in cascode to a
normally ON-type high-voltage GaN HEMT (600 V+). Additionally, the source of the MOSFET is
 Cpd
Cpd
S G D
Lg
Ls Ld
Electronics 2020, 9, 2007 Rg 5 of 19

V*
Cgs Cgd
Electronics 2020, 9, x FOR PEER REVIEW 5 of 20
connected to the gate of the HEMT. This combinational design produces an effective normally OFF
device.
TheInparasitics
this structure,
of thethe
Rs gate of the
enhancement Rgs Si MOSFET
mode GaN Rgd is used to Rd
HEMTs/GITs regulate the ON/OFF
structure state in
are as shown of Figure
the GaN3.
HEMT.
As shownThisin operational
Figure 4, theflexibility makes has
cascode device the
Gm e
GaN
an
-jɷt V*
HEMT
additionalcascode
set of more convenient
parasitic elements and
due adaptable
to the low
with theSigeneric
voltage device.Si drivers though it compromises the very high switching speed of GaN.

Rds Cpd
Cpd Cds
S G D
Lg
Ls Intrinsic Device Ld
Rg

V*
Figure 3. Structure of GaN HEMT
Cgs with parasitic
Cgd elements (adapted from [28]).

The original GaN device Rsstructure was Rgs of normally Rgd ON-type Rdand hence not preferred in power
applications due to safety and acceptability considerations. As a solution to this, the power device
Gm e -jɷt V*
engineers came up with the cascode structure to convert it into normally OFF-type. As shown in
Figure 4, a normally OFF-type low-voltage Si MOSFET (typically 30 V) is connected in cascode to a
normally ON-type high-voltage GaN HEMT (600 V+). Additionally, the source of the MOSFET is
connected to the gate of the HEMT. This combinational Rds
design produces an effective normally OFF
Cds
device. In this structure, the gate of the Si MOSFET is used to regulate the ON/OFF state of the GaN
HEMT. This operational flexibility makesIntrinsic
the GaNDevice HEMT cascode more convenient and adaptable
with the generic Si drivers though it compromises the very high switching speed of GaN.
Figure 3. Structure
Structure of GaN HEMT with parasitic elements (adapted from [28]).

The original GaN S D D

device structure was of normally ON-type and GaN-HEMT hence not (650V)
preferred in power
C gs’ g’
applications due to safety and acceptability considerations. As a solution to this,Cgd’the power device
Ls’ Rs’ Rd’ Ld’
S’
engineers came up with the cascode structure to convert it into normally OFF-type. As shown in
G d’
Figure 4, a normally
D OFF-type low-voltage Si MOSFET (typically Ld 30 V) is connected in cascodeDto a
Silicon- FET Rd’ GaN
normally ON-type high-voltage GaN (600V)
GaN HEMT (600(30V) V+). Additionally,
Rd the source of the MOSFET is
G G Normally ON
d Silicon
connected to the gate of the HEMT. This combinational Cgd design produces an effective normally OFF
Ld’
Rsu’
G Lg
S structure, the gate of the Si MOSFET
device. In this is
Rg used to regulate the ON/OFF
Lsu’ Cds’ state of the GaN
Cds
HEMT. ThisSoperational flexibility makes the GaN HEMT cascode more convenient S
and adaptable
Cgs
Silicon (30V)
with the genericNormally
Si drivers
OFF
though it compromises the very shigh switching
Ls Rs speed of GaN.Rcs Lcs

GaN-HEMT (650V)
S D D
(a) (b)
Cgs’ g’ Cgd’
Ls’
Rd’ Ld’ Rs’
Figure 4. 4.(a)(a)
Figure Cascode GaN
Cascode HEMT
GaN TO-220
HEMT package;
TO-220 and
package; (b)(b)
and simplified
simplified S’
bonding
bonding diagram
diagram (adapted
(adapted
G d’
from [29]).
from [29]). D Ld D
Silicon- FET Rd’ GaN
GaN (600V) (30V) Rd
GAccording
According G totoHuang
HuangCascode
Cascode device
Normally model,the
ON model,
device themost
Cgd
d
most critical
critical internal inductances
internal inductances
Silicon are
are as
as shown
shownin
Ld’
Figure 5a.
in Figure 5a. FigureS
5b shows the layout of the
shows the layout of the GaN GaN HEMT
G HEMT
Lg cascode inside a conventional
Rg cascode inside a conventional Rsu’ TO package.
TO package.
Lsu’ Cds’
Thearrangement
arrangementofofthe thedevice
deviceshows
showsthatthatparasitic
parasiticinductances
inductancesare C areprimarily
ds
primarilycaused causeddueduetotothethe
The S
interconnection
interconnection
Sbetween
between
Siliconthethe
(30V) device
device die,
die, the
the leads
leads andand
Cgs
other
other interconnections.
interconnections. AsAs the the device
device currents
currents
s Ls Rs
withrapid Normally
rapidtransitions
transitions areOFF
restricted Rcs Lcs
with are restricted toto such
such a acompact
compact area,
area, the the coupling
coupling effects
effects between
between different
different
conductors become significant and cause deviation from the expected behaviour. In this paper, we use
this Cascode model which has been highly regarded by the power electronics community. According to
(a) (b)
this model, Lint3 is the current source inductance (CSI) for both Si MOSFET and GaN HEMT, as shown
in Figure 5a.4.Thus,
Figure it is theGaN
(a) Cascode most critical
HEMT parasitic
TO-220 inductance.
package; Lint1 is estimated
and (b) simplified bonding to be the(adapted
diagram second most
from
critical [29]).
inductance. This is because it is the CSI of the high-voltage GaN HEMT which contributes to
the majority of switching loss when compared to Si. Ls is found to be the third most critical inductance.
According to Huang Cascode device model, the most critical internal inductances are as shown
in Figure 5a. Figure 5b shows the layout of the GaN HEMT cascode inside a conventional TO package.
The arrangement of the device shows that parasitic inductances are primarily caused due to the
interconnection between the device die, the leads and other interconnections. As the device currents
with rapid transitions are restricted to such a compact area, the coupling effects between different
be the second most critical inductance. This is because it is the CSI of the high-voltage GaN HEMT
which contributes to the majority of switching loss when compared to Si. Ls is found to be the third
most critical inductance.
It is observed that available simulation models neglect some of these parasitic inductances,
which are
Electronics critical
2020, 9, 2007in understanding the dynamic behaviour of the device. 6 of 19

Second Critcal
D
Lint1 LD

G
LG Lint3 Lint2

Most Critcal
LS Third Critcal

S
(a)

Lint1 GaN

Si
G S S D
D
G
Lint3 Lint2

LG Ls LD

Gate Source Drain

(b)
Figure 5. Cascode GaN HEMT: (a) package parasitic inductance schematic; and (b) TO-220 package
simplified bonding diagram (adapted from
from [30]).
[30]).

It is observed
The that of
development available simulation
the model models
in this work neglecton
is based some of these parasitic
the assumption inductances,
that for which
GaN, the device
are critical in understanding the dynamic behaviour
parasitics are based on this arrangement. To validate of the device.
proposed work, the developed model is
basedTheon development of the model
a two-port impedance in this workusing
measurement is based
VNA. onThe
the assumption that forthe
impedance across GaN,
G-D,the device
G-S and
parasitics are based the
D-S are measured, on this arrangement.
inductance To validate
and capacitance the proposed
values work, These
are extracted. the developed
values aremodel
also
is based onwith
compared a two-port
LT-SPICEimpedance measurement
model values suppliedusing
by theVNA. The impedance
manufacturers and withacross the G-D,
existing G-S
papers
and D-S
where are measured,
a similar proceduretheisinductance
used for SiCand capacitance
modules. values
The final are extracted.
switching model isThese values arefrom
thus developed also
compared
this withdata
extracted LT-Spice
and model values in
is simulated supplied by the
LT-Spice. Themanufacturers and with
simulation results are existing papers where
then compared with
a similar procedure
available is used
manufacturer for models
device SiC modules. The final switching
with experimental waveformsmodel is thus
from DPT.developed from this
extracted data and is simulated in LT-Spice. The simulation results are then compared with available
3.2. Behaviouraldevice
manufacturer Modelling of High-Voltage
models GaN HEMT
with experimental waveforms from DPT.
The proposed
3.2. Behavioural modelling
Modelling design procedure
of High-Voltage GaN HEMT is based on developing a dynamic behavioural
model, as shown in Figure 6. This analysis is based on the two-port representation and is estimated
The proposed modelling
via frequency-dependent design procedure
impedance is basedtaken
measurements on developing
between athe
dynamic behavioural
source, gate and model,
drain
as shown in Figure 6. This analysis is based on the two-port representation and is estimated via
frequency-dependent impedance measurements taken between the source, gate and drain terminals.
As discussed above, within the device package, it is the device linkage and package which are
dominantly inductive, while the semiconductor die is principally capacitive. This simple model
estimates that for any two terminals chosen for analysis, the impedance sweep will output a second-order
RLC network. This simplification has been used by many research groups and is proved to produce
approximate inductance values with minimum error. Based on the existing models and device
parameter extraction, the small signal model of GaN HEMT in Figure 6 can be approximated as shown
in Figure 7 [31].
are dominantly
are dominantly inductive,
inductive, while
while the
the semiconductor
semiconductor die
die is
is principally
principally capacitive.
capacitive. This
This simple
simple model
model
estimates that for any two terminals chosen for analysis, the impedance sweep will
estimates that for any two terminals chosen for analysis, the impedance sweep will output a second-output a second-
order RLC
order RLC network.
network. ThisThis simplification
simplification has
has been
been used
used byby many
many research
research groups
groups andand isis proved
proved to to
produce approximate inductance values with minimum error. Based on the
produce approximate inductance values with minimum error. Based on the existing models and existing models and
device parameter
device parameter
Electronics extraction, the
2020, 9, 2007extraction, the small
small signal
signal model
model of
of GaN
GaN HEMT
HEMT in in Figure
Figure 66 can
can be
be approximated
approximated
7 of 19
as shown in Figure
as shown in Figure 7 [31]. 7 [31].

Lg Rfdg Ld
G Lg Rg Cdg Rfdg Rd Ld D
G Rg Cdg Rd D
Vi
Vi Rdg
Rdg

Cgs
Cgs
Ids Cgs
Rfgs Ids Rgs Cgs
Rfgs Rgs
Ri
Ri

Cgsp Cdsp
Cgsp Cdsp

Rs
Rs

Ls
Ls
IIds
ds==gm
gm V τώ
Vie-j-jτώ
S
S ie S
S

Figure 6.
Figure Small signal
6. Small signal model
model of
of GaN
GaN HEMT
HEMT (adapted
(adapted from
from [31]).
[31]).

Lg Cg Ld
Lg Rg ΔZg Cd ΔZd Rd Ld
G Rg ΔZg Cg Cd ΔZd Rd D
G D

Cs
Cs

ΔZs
ΔZs

Rs
Rs

Ls
Ls
S S
S S

Figure 7.
Figure 7. Simplified
Simplified parasitic circuit
Simplifiedparasitic circuit model
model of
of GaN–reduced
GaN–reduced zero
zero bias
bias form
form (adapted
(adapted from
from [31]).
[31]).

The small-signal
small-signal equivalent
equivalentcircuit
circuitmodel
modeldeveloped
developeddoes doesnot notintend
intendto to obtain
obtain thethe specifics
specifics of
The small-signal equivalent circuit model developed does not intend to obtain the specifics of
of semiconductor
semiconductor die die
die and and wire-bond
and wire-bond interconnections.
wire-bond interconnections.
interconnections. Thus, Thus,
Thus, in in
in thisthis work,
this work,
work, the the measured
the measured lumped lumped
semiconductor
inductance
inductance values
values are
arecompared
compared to the
to extracted
the valuesvalues
extracted of the model
of the proposed
model by Huangby
proposed to Huang
determine to
inductance values are compared to the extracted values of the model proposed by Huang to
the individual
determine the wire-bond
individual inductances
wire-bond of the TO packages.
inductances of the TOSince SMD package
packages. Since SMDis devoid
packageof such
is large
devoid
determine the individual wire-bond inductances of the TO packages. Since SMD package is devoid
interconnection
of such
such large inductances, it isinductances,
large interconnection
interconnection assumed to be zero in this work. beMeasuring thework.
combined impedance
of inductances, itit isis assumed
assumed to be
to zero in
zero in this
this Measuring
work. Measuring the
the
for each possible
combined impedancepairing
for of terminals
each possible for the device
pairing of will produce
terminals for thea set of three
device will combineda inductance
produce set of three
combined impedance for each possible pairing of terminals for the device will produce a set of three
values.
combined
combined These combinedvalues.
inductance
inductance inductance
values. These
These values are related
combined
combined to the individual
inductance
inductance values are
values parasitic
are related
related inductance
to the
to values in
the individual
individual
the equivalent
parasitic
parasitic inductancecircuit
inductance of Figure
values
values in the6equivalent
in the by linear Equations
equivalent circuit of
circuit (1)–(3).
of Figure
Figure The
66 by
by device
linear
linear capacitance
Equations
Equations is considered
(1)–(3).
(1)–(3). The device
The device
intrinsic and
capacitance shows
is the
considered reduced zero-bias
intrinsic and equivalent.
shows the reduced zero-bias
capacitance is considered intrinsic and shows the reduced zero-bias equivalent. equivalent.
+ Rd +
Ld +
+ + Ls +
+ + Rs =
+ = Lds +
= +Rds
+ (1)
(1)
(1)
+
+ + +
+ + =
= +
+ (2)
(2)
Ld + Rd + Lg + Rg = Ldg + Rdg (2)
++ ++ + + = = +
+ (3)
(3)
Lg + Rg + Ls + Rs = Lgs + Rgs (3)

Figure 7 is simplified for zero bias conditions depending on the device structure to simplify the
circuit model to a symmetry form in favour of parameter extraction.

3.2.1. Packaging Impedance Analysis

The analysis procedure used in this work is adopted from the technique employed in [32] for
extracting SiC module impedances. This technique is based on the use of a Vector Network Analyser
 Figure 7 is simplified for zero bias conditions depending on the device structure to simplify the
circuit model to a symmetry form in favour of parameter extraction.

3.2.1. Packaging Impedance Analysis

Electronics 2020, 9, 2007 8 of 19
The analysis procedure used in this work is adopted from the technique employed in [32] for
extracting SiC module impedances. This technique is based on the use of a Vector Network Analyser
(VNA)
(VNA)totomeasure
measureimpedances
impedancesand andcompute
computeinductances
inductancesfromfromit.it.This
Thisisisdone
doneasasan
anextension
extensionofofthe
the
procedures outlined for RF devices in
procedures outlined for RF devices in [33].[33].
InInthis
this study,
study, the frequency
frequency sweep
sweepwas wasdone
doneusing
usinganan Agilent
Agilent E5061B
E5061B Network
Network Analyzer.
Analyzer. This
This experiment
experiment waswas carried
carried outout between
between 100100
HzHzand
and3 3GHz.
GHz.AAcritical
critical step
step for this procedure
procedure isisthe
the
calibration of the VNA, as shown in Figure 8. Proper calibration must be performed
calibration of the VNA, as shown in Figure 8. Proper calibration must be performed every time the every time the
set-up
set-upisisdetached
detachedfrom
fromthe thedevice
devicemount
mountororwhen
whenthe
thetest
testrig
rigisisdisturbed
disturbedororchanged
changedininany
anyway.
way.

Figure8.8.VNA
Figure VNAcalibration
calibrationand
andset-up
set-upfor
forimpedance
impedanceextraction.
extraction.

This
Thiswork
workisisbased
basedon onthe
thefull
fulltwo-port
two-portcalibration
calibrationprocedure
proceduredescribed
describedinin[34].
[34].The
The“short”,
“short”,
“open”
“open” and “load” steps were carried out using the calibration apparatus. Custom adapter PCBwas
and “load” steps were carried out using the calibration apparatus. Custom adapter PCB was
used
usedtotoimplement
implement“through”
“through”calibration
calibrationstep
stepviaviaextending
extendingthe thecalibration
calibrationplane.
plane.The
ThePCB
PCBused
usedfor
for
mounting
mountingthe thedevice
deviceisisasasshown
shownininFigure
Figure9,9,and
andthe
thetest
testsetup
setupused
usedtotoapply
applythese
thesecharacterisation
characterisation
procedures
procedures
Electronics
isisshown
2020, 9, xshown
ininFigure
FOR PEER Figure10.
REVIEW10. 9 of 20

(a) (b)
Figure 9. PCB
PCB designed
designed for
for GaN
GaN device
device fixture
fixture for: (a)
(a) SMD
SMD packages;
packages; and
and (b)
(b) TO.
TO.
 (a) (b)
Electronics 2020, 9, 2007 9 of 19
Figure 9. PCB designed for GaN device fixture for: (a) SMD packages; and (b) TO.

Figure 10.
Figure 10. Measurement set-up for
Measurement set-up for GaN
GaN device
device impedance
impedance extraction
extraction using
using VNA.
VNA.

3.2.2. DUT Device

3.2.2. DUT Device under
under Test
Test
Using the prescribed
Using the prescribed techniques,
techniques,ititwas
waspossible
possibletotocurve-fit
curve-fiteach
eachterminal
terminal pair
pair inin
thethe module
module to
to a series
a series RLCRLC equivalentmodel.
equivalent model.AsAsdiscussed
discussedininthe
theprevious
previoussections,
sections, the
the effective
effective capacitance
capacitance is is
contributed by the paralleled HEMT and anti-parallel diode intrinsic capacitance,
contributed by the paralleled HEMT and anti-parallel diode intrinsic capacitance, and the effective and the effective
inductance
inductance isisthe theseries and
series andparallel combination
parallel of the
combination of wire bondsbonds
the wire and interconnects structures
and interconnects within
structures
the module
within [35,36]. [35,36].
the module
An
An illustration of
illustration of the
the curve-fit
curve-fit agreement
agreement achieved
achieved byby this
this procedure
procedure for
for Transphorm
Transphorm HEMT HEMT is is
shown
shown in in Figure
Figure 11.
11. This
This plot
plot represents
represents the
the impedances
impedances of of the
the GaN
GaN HEMT
HEMT terminal
terminal pairs
pairs with
with the
the
gate
gate biased
biased turned
turned OFF.
OFF. InIn this
this plot,
plot, the device impedance
the device impedance structure
structure contains
contains additional
additional higher-order
higher-order
terms which are not captured by the simple series LC model and are beyond
terms which are not captured by the simple series LC model and are beyond the scope of the scope of this
this work.
work.
However,
However, the the primary
primary resonant
resonant frequency
frequency can
can be
be easily
easily determined
determined from
from the
the curves,
curves, and
and itit is
is used
used to
to
formulate an estimate of the equivalent lumped inductance for this
formulate an estimate of the equivalent lumped inductance for this terminal pair.terminal pair.
Electronics 2020, 9, x FOR PEER REVIEW 10 of 20
Magnitude (log) and Phase

Frequency (Hz)
Figure
Figure 11.11. Impedanceresponse
Impedance response for
for the
the terminals
terminalsofofTransphorm
Transphormdevice.
device.

In Figure 11, the impedance responses are plotted from 500 Hz to 3 GHz. For the devices, until
688 kHz, the impedance is very high, and then, with increase in frequency, the impedance decreases
significantly and again increases after 1 kHz. The response is similar to a series RLC circuit for DS
and GS terminals as expected. (The light blue colour graph shows the simulated response of the RLC
circuit. The dark blue graph with noise is the experimental measured response of the RLC circuit).
In Figure 11, there is a considerable difference (lengths a and b) between the simulation and
Electronics 2020, 9, 2007 10 of 19

In Figure 11, the impedance responses are plotted from 500 Hz to 3 GHz. For the devices, until
688 kHz, the impedance is very high, and then, with increase in frequency, the impedance decreases
significantly and again increases after 1 kHz. The response is similar to a series RLC circuit for DS
and GS terminals as expected. (The light blue colour graph shows the simulated response of the RLC
circuit. The dark blue graph with noise is the experimental measured response of the RLC circuit).
In Figure 11, there is a considerable difference (lengths a and b) between the simulation and VNA
measurement response. This can be attributed to the fact that the actual device parasitics are not only
composed of a series RLC structure. It is due to a parallel combination of other elements such as the
capacitor, as shown in the above figures.
In general, it is observed that, until 500 kHz, there is very high impedance and then the circuit
behaves inductive with self-resonant frequency at 29 MHz. The impedance response after around
370 MHz becomes dominated by the transmission line behaviour of the co-axial cable and PCB vias,
which is highlighted in Figure 11. This is due to the five-point model behaviour of the coaxial cable,
the details of which are outside the framework of this research work.
For Transphorm HEMT device, due to the two-device structure, the parasitic inductance is slightly
higher than Panasonic GIT. The values are much higher than GaN systems devices because both are
TO packaged devices. The PCB terminal inductance is also measured to account for the inductance
due to the track inductance and cable inductance. Based on the extracted impedance values in the ON
and OFF states, the behavioural model is framed based on extracting the inductance values. Then,
finding the capacitance from the resonant frequency of the curve, this is further simulated in LT-Spice
and tuned for the values of inductance to verify the accuracy.
The obtained values are plugged into Equations (1)–(3) to extract the aggregate inductance values
for all pairings of terminals. The inductances due to PCB are subtracted from the measured values and
the final results are presented in Table 2. The individual circuit inductance values are listed in Table 3.

Table 2. Measured lumped inductance of the terminals of the devices.

Combined Inductance (nH) LGD LDS LSG

Transphorm GaN HEMT (VNA) 7.45 4.99 5.04
Panasonic GaN GIT (VNA) 4.465 2.565 3.10
GaNSystems GaN HEMT (VNA) 3.02 1.880 2.76

Table 3. Derived inductance values of gate, drain and source terminals.

Inductance (nH) LG LD LS
Transphorm GaN HEMT (VNA) 3.75 3.7 1.29
Transphorm SPICE model 2.8 2.06 1.04
Panasonic GaN GIT (VNA) 2.815 1.67 0.895
Panasonic SPICE model 2.97 1.55 1.0
GaNSystems GaN HEMT (VNA) 1.04 1 0.67
GaNSystems SPICE model NA NA NA

Based on the extracted impedance values in the ON and OFF states, the behavioural model is
framed based on extracting the inductance and capacitance values from the curve. This is further
simulated in LT-Spice and tuned for the values of inductances to verify the accuracy. Figure 11 shows
that the impedance response obtained for the experimental and simulated responses are in agreement.
This simplified behavioural model is then used in simulation to predict the effect of various parasitics
on the switching performance.
At low frequencies, reactance is very small and might be masked by capacitive reactance, which
makes the extraction challenging. At higher frequencies, there are errors caused due to text fixture and
calibration issues. For GaN, extraction is extremely complicated as inductances in the package are very
small (≤5 nH). This very small inductance is thus extremely susceptible to systematic errors introduced
various parasitics on the switching performance.
At low frequencies, reactance is very small and might be masked by capacitive reactance, which
makes the extraction challenging. At higher frequencies, there are errors caused due to text fixture
and calibration issues. For GaN, extraction is extremely complicated as inductances in the package
Electronics
are very small2020,
(≤59, 2007
nH). This very small inductance is thus extremely susceptible to systematic 11 of 19
errors
introduced by poor calibration. Since the calibration standards used are not true open/shorts,
scattering(s) parameters Since
by poor calibration. can be theapplied to de-embed
calibration standards for
usedvalidating theopen/shorts,
are not true impedance scattering(s)
measurements.
However, here,can
parameters thebeextracted
applied tovalues arefor
de-embed directly compared
validating to the measurements.
the impedance manufacturer However,
model inductance
here,
theand
values extracted
foundvalues
to beare directly
very closecompared to the manufacturer
and reasonable, as shown in model
Tableinductance
3. values and found to
be very close and reasonable, as shown in Table 3.
4. Switching Tests: Double Pulse Test
4. Switching Tests: Double Pulse Test
To validate the model, the performance of the simulation using the proposed model was
To validate the model, the performance of the simulation using the proposed model was compared
compared
with thewith the performance
performance of the commercial
of the commercial device
device using an using anrigexperimental
experimental rig (DPT
(DPT in this case). in this
The test
case).rigThe test rig
is shown in is shown
Figure in Figure
12 and 12 andby
was supplied was supplied
Sanken Inc as by
partSanken Inc as part of
of our collaborative ourwith
work collaborative
them.
workThis with them. This circuit can be customised to use TO and other SMD packages
circuit can be customised to use TO and other SMD packages and is thus preferred for convenience and is thus
preferred for convenience
and flexibility. andvoltages
The supply flexibility. The drive
for gate supplyarevoltages for gate
customised drivetoare
according thecustomised according
specification and
to the specification
structure and device
of the GaN structure of the
under test.GaN device under test.

Figure 12. Prototype

Figure of of
12. Prototype thethe
DPT
DPTwith
withthe
theinbuilt gatedrive
inbuilt gate drivecircuitry
circuitry (provided
(provided by Sanken
by Sanken Inc). Inc).

The The
test test
set set
up up is as
is as follows:
follows:
1. 1. 500
500 V V dc-bus,
dc-bus, 15from
15 A A from inductiveload
inductive load
2. 2. Customised measurement
Customised measurement set-up set-up
3. Agilent oscilloscope with double pulse signal from Agilent waveform generator
4. Electrical power from bench top power supplies

The device current measurement is done using a current probe. The voltage measurements were
checked using a precision probe. The circuit was tested using GaN Systems, Transphorm, Panasonic
and Sanken devices. Due to restricted access to the full datasheet and discrete Sanken devices, it is not
investigated further in this work. The switching characteristics for the devices tested are detailed in
the following sections:

4.1. GaN Systems GS66508B HEMT (650 V, 30 A, SMD Package)

Figure 13 shows the switching characteristics at 200 ns per division. After the initial start,
the switching voltage Vds rises sharply with a high dVds /dt around 10,000 V/s. Afterwards, there is
only a small overshoot with no considerable ringing. The current fall measured appears noisy due to
interaction of the measurement circuitry with other components on the board. There is a rise in the
Vds before turn OFF and is mirrored in the Vgs dropping. At turn ON, the current reaches its on state.
All throughout, the gate voltage remains fairly clean with only very small ringing.
 Figure 13 shows the switching characteristics at 200 ns per division. After the initial start, the
switching voltage Vds rises sharply with a high dVds/dt around 10,000 V/s. Afterwards, there is only
a small overshoot with no considerable ringing. The current fall measured appears noisy due to
interaction of the measurement circuitry with other components on the board. There is a rise in the
Vds before
Electronics turn
2020, OFF and is mirrored in the Vgs dropping. At turn ON, the current reaches 12
9, 2007 itsofon
19
state. All throughout, the gate voltage remains fairly clean with only very small ringing.

Figure 13.
Figure Switchingwaveforms
13. Switching waveformsfor
forGaN
GaNSystems
Systems GaN
GaN HEMT.
HEMT.

4.2. Panasonic GIT PGA26C09DV (600 V, 30 A, TO Package)

4.2. Panasonic GIT PGA26C09DV (600 V, 30 A, TO Package)
In Figure 14, at turn OFF, the dVds/dt is around 35,000 V/s with no overshoot. The current waveform
In Figure 14, at turn OFF, the dVds/dt is around 35,000 V/s with no overshoot. The current
is free of very high frequency ringing and shows a sluggish fall. As the voltage rises and the free wheel
waveform is free of very high frequency ringing and shows a sluggish fall. As the voltage rises and
diode turns ON, the current falls rapidly. The gate waveform also falls rapidly with no much ringing.
the free wheel diode turns ON, the current falls rapidly. The gate waveform also falls rapidly with
At turn ON, the current rises very rapidly with a very small overshoot and the voltage then falls in
no much ringing. At turn ON, the current rises very rapidly with a very small overshoot and the
steps. The voltage and current capture is distorted due to measurement inconsistencies. The voltage
voltage then falls in steps. The voltage and current capture is distorted due to measurement
falls with2020,
Electronics an initial
9, x FORfast
PEER /dt followed by a step fall.
dVREVIEW
dsfalls 13 of 20
inconsistencies. The voltage with an initial fast dVds/dt followed by a step fall.

Figure 14.
Figure Switching waveforms
14. Switching waveforms for
for Panasonic
Panasonic GaN
GaN GIT.
GIT.

4.3. Transphorm Cascode GaN HEMT TPH3212PS (600 V, 30 A TO Package)

4.3. Transphorm Cascode GaN HEMT TPH3212PS (600 V, 30 A TO Package)
Transphorm is a cascode device, hence can be driven the same as a Si FET. However, since this
Transphorm is a cascode device, hence can be driven the same as a Si FET. However, since this
driver is made with the stringent gate voltage control, for using Transphorm, the gate voltage was
driver is made with the stringent gate voltage control, for using Transphorm, the gate voltage was
increased to +8 V. This caused some unexpected variation of gate voltage. In Figure 15, at turn
increased to +8 V. This caused some unexpected variation of gate voltage. In Figure 15, at turn OFF,
OFF, the dVds/dt is around 42,000 V/s, with a second-order response with overshoot and oscillations.
the dVds/dt is around 42,000 V/s, with a second-order response with overshoot and oscillations. The
The current fall is rapid initially followed by a slow fall. The gate voltage has a very clear dip at turn
current fall is rapid initially followed by a slow fall. The gate voltage has a very clear dip at turn OFF
OFF before the voltage rise. This final stage is accompanied by a slow rise in the gate voltage. The gate
before the voltage rise. This final stage is accompanied by a slow rise in the gate voltage. The gate
voltage continues to build up with a steep rise until the device is fully ON.
voltage continues to build up with a steep rise until the device is fully ON.
 driver is made with the stringent gate voltage control, for using Transphorm, the gate voltage was
increased to +8 V. This caused some unexpected variation of gate voltage. In Figure 15, at turn OFF,
the dVds/dt is around 42,000 V/s, with a second-order response with overshoot and oscillations. The
current fall is rapid initially followed by a slow fall. The gate voltage has a very clear dip at turn OFF
before
Electronics the9, voltage
2020, 2007 rise. This final stage is accompanied by a slow rise in the gate voltage. The gate13 of 19
voltage continues to build up with a steep rise until the device is fully ON.

Figure Switching
15.15.
Figure Switchingwaveforms for the
waveforms for theTransphorm
Transphorm GaN
GaN HEMT
HEMT cascode.
cascode.

5. Simulation of the
5. Simulation Double
of the Pulse
Double PulseTests
TestsUsing
Using the ProposedModel
the Proposed Model and
and Manufacturer
Manufacturer Model
Model
For this
For research, the proposed
this research, behavioural
the proposed modelmodel
behavioural was demonstrated and validated
was demonstrated by redesigning
and validated by
redesigning
the LT-Spice the LT-Spice
model providedmodel
byprovided by the manufacturer.
the manufacturer. The parameters
The parameters of the
of the existingmodel
existing model were
were customised
customised to bring to bring
the the model
model into alignment
into alignment withwith
thethe extractedmeasurements.
extracted measurements. Figure
Figure16a,b is is a
16a,b
a replication of the simplified zero bias model of Figure 7. The manufacturer and proposed
replication of the simplified zero bias model of Figure 7. The manufacturer and proposed models are models
are both simulated in LT-Spice for comparison, as shown in Figure 16.
both simulated
Electronics 2020, 9, xin LT-Spice
FOR for comparison, as shown in Figure 16.
PEER REVIEW 14 of 20

L3
R4
2 R3
L2
3.5n
D1 C1 C2 S2 2
160µ
OP SC 600 470µ 0.47µ C3 -
V3 L10 + C1 V8
R10
DC

2 600p SW 160p DC

3.5n R9
400 2
S2 L1 L2 400
C10 - 0.8n
C9
2.2n
+
600p SW 150p C2
L8 L9 200p
0.8n 2.2n
C8
200p V7 R7
1.5
DC

V5 R7
1.5
DC
PULSE
PULSE (20 0 0 0 0 3u 5u)
(15 0 0 0 0 3u 5u)

(a) (b)
Figure 16.
Figure 16. (a)(a)
Proposed behavioural
Proposed modelmodel
behavioural for GaN
forHEMT;
GaN and (b) DPT
HEMT; andsimulation
(b) DPT of the proposed
simulation of the
model. model.
proposed

6.6.Comparison
Comparison of LT-Spice Simulationwith
Lt-Spice Simulation withDPT
DPT Output
Output
First, we
First, we integrated
integrated thethe parasitic
parasiticmodel
modelwith
withthetheexisting
existingmanufacturer
manufacturer models
modelsof the device.
of the device.
Then, an overlay of the simulation output from the manufacturer model, developed
Then, an overlay of the simulation output from the manufacturer model, developed behavioural model behavioural
model
and and experimental
experimental waveformswaveforms were compared
were compared for switching
for switching trajectories
trajectories at 15 Aatand
15 A500
andV.500
TheV.resulting
The
resulting switching
switching voltage,
voltage, gate voltagegateand
voltage andcomparisons
current current comparisons are presented
are presented in the subsequent
in the subsequent sections.
sections.
In Figure 17, Figure 18, Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, reasonable agreement is
noted In Figures
between the17–23, reasonable
simulated agreementwaveforms.
and experimental is noted between
The mostthesignificant
simulatedswitching
and experimental
characteristics
waveforms. The most significant switching characteristics of the waveforms
of the waveforms are reproduced in accordance with the experimental waveforms. Specifically, are reproduced in
accordance with the experimental waveforms. Specifically, the voltage switching transition rates
the voltage switching transition rates appear to be in good conformity. These results suggest that the
appear to be in good conformity. These results suggest that the critical parasitic impedances are
reasonably well-matched. The simulation current, on the other hand, is not always well matched to
experimental waveforms. As shown in the figures, the measurement of current was not accurate due
to noise interference. This makes the simulated current waveforms of the proposed model and
manufacturer model slightly different from the experimental values. Based on the waveform
simulation time, repeatability comparison and by measuring the distance between the voltage
Electronics 2020, 9, 2007 14 of 19

critical parasitic impedances are reasonably well-matched. The simulation current, on the other hand,
is not always2020,
Electronics well 9, xmatched
FOR PEER to experimental waveforms. As shown in the figures, the measurement
REVIEW
Electronics 2020, 9, x FOR PEER REVIEW
15 of 20 of
15 of 20
current was not accurate due to noise interference. This makes the simulated current waveforms of the
proposed model and manufacturer model slightly different from the experimental values. Based on
the waveform simulation time, repeatability comparison and by measuring the distance between
the voltage waveforms for devices, accuracy of the proposed model is determined. It is based on
the similarity of the proposed model switching waveforms to the expected experimental waveforms.
TheElectronics
difference 2020,in
9, the distance
x FOR is calculated and accuracy determined.
PEER REVIEW 15 of 20

Figure 17. Comparison of switching voltage waveforms of models with DPT results.
Figure 17. Comparison of switching voltage waveforms of models with DPT results.

The gate voltage in Figure 18 is relatively clean which is possibly because measurement of gate
The gate voltage in Figure 18 is relatively clean which is possibly because measurement of gate
voltage was not accurate. The manufacturer and proposed model showed more ideal characteristics.
voltage was not accurate. The manufacturer and proposed model showed more ideal characteristics.
The switching current measurement suffered from noise can be seen in Figure 19. However, the
The switching current measurement suffered from noise can be seen in Figure 19. However, the
overall proximity of the proposed model to the experimental waveforms shows that the behavioural
overall proximity of the proposed model to the experimental waveforms shows that the behavioural
model is nearly accurate.
model is nearly accurate.
Comparison
Figure 17.17.
Figure Comparisonofofswitching
switching voltage waveformsofofmodels
voltage waveforms models with
with DPT
DPT results.
results.

The gate voltage in Figure 18 is relatively clean which is possibly because measurement of gate
voltage was not accurate. The manufacturer and proposed model showed more ideal characteristics.
The switching current measurement suffered from noise can be seen in Figure 19. However, the
overall proximity of the proposed model to the experimental waveforms shows that the behavioural
model is nearly accurate.

Figure 18. Comparison ofgate

Comparison gate voltage waveforms
waveforms of models with DPT results.
Figure 18.18.
Figure Comparisonof
of gate voltage
voltage waveforms ofofmodels
models with
with DPT
DPT results.
results.

Figure 18. Comparison of gate voltage waveforms of models with DPT results.

Figure Comparison
19.19.
Figure Comparisonofofswitching
switchingcurrent waveformsofofmodels
current waveforms modelswith
with DPT
DPT results.
results.
Figure 19. Comparison of switching current waveforms of models with DPT results.
6.2. Panasonic
OFF and turnGaN ONGIT
instants. In addition, towards turn OFF, it follows the experimental voltage
waveform
For thevery closely.device, the switching voltages of the experimental model were in steps during
Panasonic
turn ON due to the influence of the switching current deviation and noise. As shown in Figure 20,
the proposed model was in good agreement with the experimental results, especially during turn
OFF and2020,
Electronics turn ON instants. In addition, towards turn OFF, it follows the experimental voltage
9, 2007 15 of 19
waveform very closely.

Figure 20. Comparison of switching voltage waveforms of models with DPT results.

The gate voltage shown in Figure 21 is noisier for this device due to customisation of the gate
circuitry. Using external elements in the PCB has caused it to oscillate due to the parasitic inductances
of the connections
Figure and the externalofboard.
20. Comparison switching voltage waveforms of models with DPT results.
Figure 20. Comparison of switching voltage waveforms of models with DPT results.

The gate voltage shown in Figure 21 is noisier for this device due to customisation of the gate
circuitry. Using external elements in the PCB has caused it to oscillate due to the parasitic inductances
of the connections and the external board.

Electronics 2020, 9, Figure

x FOR PEER
Figure REVIEW
Comparison
21. Comparison
21. ofgate
of gatevoltage
voltage waveforms
waveforms of
of models
models with
with DPT
DPT results.
results. 17 of 20

The switching current shown in Figure 22 is in close agreement and there was no significant
deviation from the experimental results. Furthermore, the behaviour of the proposed model is similar
to the experimental waveforms; however, during turn ON and turn OFF instants it is deviating from
Figure 21. Comparison of gate voltage waveforms of models with DPT results.
ideal.
The switching current shown in Figure 22 is in close agreement and there was no significant
deviation from the experimental results. Furthermore, the behaviour of the proposed model is similar
to the experimental waveforms; however, during turn ON and turn OFF instants it is deviating from
ideal.

Figure 22.
Figure Comparison of
22. Comparison of switching
switching current
current waveforms
waveforms of
of models
models with
with DPT
DPT results.
results.

6.3. Transphorm Cascode GaN HEMT

As shown in Figure 23, the gate voltage was very noisy for this device due to customisation of
the gate circuitry using external elements added to the PCB which has caused it to significantly
oscillate due to the parasitic inductances of the connections and the external board introduced to
increase the positive input voltage to +8 V as the gate circuitry was designed in the range of 4.5–5 V.

Comparison of Gate Voltage

10
6.3. Transphorm Cascode GaN HEMT
As shown in Figure 23, the gate voltage was very noisy for this device due to customisation of
the gate circuitry using external elements added to the PCB which has caused it to significantly
oscillate
Electronics due to2007
2020, 9, the parasitic inductances of the connections and the external board introduced
16 ofto
19
increase the positive input voltage to +8 V as the gate circuitry was designed in the range of 4.5–5 V.

Comparison of Gate Voltage

10

Experimental Gate Voltage

Voltage(Vgs) (V)
(Vgs)(V) 5
Proposed Model Gate Voltage

Manufacturer Model Gate Voltage

GateVoltage

0
Gate

-5
0 0.5 1 1.5 2
Time(s)
Time (x10-6
× 10-6µs)

Figure23.
Figure Comparisonofofgate
23.Comparison gatevoltage
voltagewaveforms
waveformsof
ofmodels
modelswith
withDPT
DPTresults.
results.

6.1. GaN Systems GaN HEMT

7. Discussion
For the GaN systems device, the switching voltages of the proposed model are in good agreement
1.
with the measurement
The experimental using
results,VNA is relatively
as seen in Figurestraightforward and doestrue
17. This is specifically notfor
require an accurate
the transient and
understanding
oscillations during of theOFF
turn packaging
instants.or structure of the
In addition, device.turn OFF, it follows the experimental
towards
2. It iswaveform
voltage noted that theclosely.
very measured package parasitics are as expected higher than the supplied
manufacturer model values18
The gate voltage in Figure specified in theclean
is relatively LT-spice
whichmodels.
is possibly because measurement of gate
3. Thewas
voltage demonstrated model
not accurate. The is simple, approximate
manufacturer and satisfactorily
and proposed model showed mimics
morethe actual
ideal switching
characteristics.
behaviour of the device. It can be seen from the results that the dynamic response
The switching current measurement suffered from noise can be seen in Figure 19. However, the overall of the
modelled GaN devices are very similar to the experimental ones.
proximity of the proposed model to the experimental waveforms shows that the behavioural model is
4. The fluctuation and abnormality in current is caused by the noise associated with the
nearly accurate.
measurement circuitry due to interference with the surrounding circuitry. This ringing is
considered
6.2. Panasonic to be
GaN GITa measurement error due to the rapid changes in voltage and current during
switching. This could not be replicated in the simulation properly and so there is a mismatch in
For the Panasonic device, the switching voltages of the experimental model were in steps during
turn ON due to the influence of the switching current deviation and noise. As shown in Figure 20,
the proposed model was in good agreement with the experimental results, especially during turn OFF
and turn ON instants. In addition, towards turn OFF, it follows the experimental voltage waveform
very closely.
The gate voltage shown in Figure 21 is noisier for this device due to customisation of the gate
circuitry. Using external elements in the PCB has caused it to oscillate due to the parasitic inductances
of the connections and the external board.
The switching current shown in Figure 22 is in close agreement and there was no significant
deviation from the experimental results. Furthermore, the behaviour of the proposed model is similar
to the experimental waveforms; however, during turn ON and turn OFF instants it is deviating
from ideal.

6.3. Transphorm Cascode GaN HEMT

As shown in Figure 23, the gate voltage was very noisy for this device due to customisation of the
gate circuitry using external elements added to the PCB which has caused it to significantly oscillate
due to the parasitic inductances of the connections and the external board introduced to increase the
positive input voltage to +8 V as the gate circuitry was designed in the range of 4.5–5 V.

7. Discussion
1. The measurement using VNA is relatively straightforward and does not require an accurate
understanding of the packaging or structure of the device.
Electronics 2020, 9, 2007 17 of 19

2. It is noted that the measured package parasitics are as expected higher than the supplied
manufacturer model values specified in the LT-Spice models.
3. The demonstrated model is simple, approximate and satisfactorily mimics the actual switching
behaviour of the device. It can be seen from the results that the dynamic response of the modelled
GaN devices are very similar to the experimental ones.
4. The fluctuation and abnormality in current is caused by the noise associated with the measurement
circuitry due to interference with the surrounding circuitry. This ringing is considered to be a
measurement error due to the rapid changes in voltage and current during switching. This could
not be replicated in the simulation properly and so there is a mismatch in the measured and
simulated device switching currents. The Transphorm gate voltage variation is noisy due to the
customised gate drive circuitry inductance.
5. From this work, it is concluded that a simple behavioural model for different GaN devices can be
built using extracted parasitics from the VNA measurements. The proposed behavioural model
shows very close characteristics to the actual working of the GaN device when employed in a
power circuit. The observed variation of the proposed model from the actual device is due to
the practical inability to precisely measure impedances and simulate parasitics. Nevertheless,
this model is a best approximation for a simple GaN behavioural model.
6. This proposed behavioural model is dependent on the measurement circuitry, PCB inductance,
calibration errors of the VNA and human errors. To further improve accuracy and capture the
response of the GaN power device more accurately, we explored the use of ML techniques to
build realistic GaN models. These models can mimic the switching performance of the GaN
power devices with great accuracy and fidelity.

8. Conclusions, Limitations and Future Work

Behavioural modelling, parasitic quantification and operation at higher switching frequencies
were identified as the major barriers to commercial adoption of GaN at application level. To solve this
issue, a simple behavioural model of GaN HEMT is developed by extracting impedances using a Vector
Network Analyser. This is a practical approach to GaN power device modelling using techniques
borrowed from RF space.
A comparison of the switching performance of the developed model, the manufacturer model
and experimental findings show that the proposed model is simple, practical and fast. However,
because of the time involved in parasitic extraction, the complexity of the analytical procedures and
the dependency on human and measurement errors, the proposed behavioural model is not suitable
to validate all applications. Hence, this cannot serve as a universal model for GaN. Thus, the need
for a unified GaN behavioural model which is an accurate replica of the actual device dynamics was
identified. An ML-based universal GaN model was developed as future work to solve the limitations
of this proposed model [37]. Nevertheless, the proposed GaN model based on RF techniques can serve
as the best candidate for a practical simulation design and can be used in conjunction with the existing
LT-Spice models.

Author Contributions: Conceptualisation, N.H.; methodology, N.H.; validation, N.H. and S.R.; formal analysis,
N.H., M.A., S.R., J.H. and E.M.G.R.; investigation, N.H.; resources, N.H. and S.R.; data curation, N.H. and S.R.;
writing—original draft preparation, N.H.; writing—review and editing, N.H.; M.A., S.R., J.H. and E.M.G.R.;
visualisation, N.H. and S.R.; supervision, N.H. and, S.R.; project administration, N.H. and S.R.; and funding
acquisition, N.H. All authors have read and agreed to the published version of the manuscript.
Funding: This research was funded by Cambridge University Nehru Trust and Dept of Engineering.
Acknowledgments: The authors would like to thank Edward Shelton Philip Garsed and Saikat Gosh at the
Department of Engineering, University of Cambridge, UK for providing technical support. Many thanks to GaN
Systems, Panasonic, Transphorm and Sanken for providing with the GaN device samples and necessary documentation.
Conflicts of Interest: The authors declare no conflict of interest.
Electronics 2020, 9, 2007 18 of 19

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