Ain Shams Engineering Journal 12 (2021) 3141–3155

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Engineering Physics and Mathematics

Identification of power PIN diode design parameters: Circuit and

device-based simulation approach
A. Shaker a,⇑, Marwa S. Salem b, A. Zekry c, M. El-Banna a, G.T. Sayah d, M. Abouelatta c
a
Engineering Physics and Mathematics Department, Faculty of Engineering, Ain Shams University, Cairo, Egypt
b
(Department of Computer Engineering, Computer Science and Engineering College, University of Ha’il, Ha’il, Saudi Arabia) and (Department of Electrical Communication
and Electronics Systems Engineering, Faculty of Engineering, Modern Science and Arts University, Cairo, Egypt)
c
Electronics and Communication Department, Faculty of Engineering, Ain Shams University, Cairo, Egypt
d
Electronics Department, Nuclear Science, Cairo, Egypt

a r t i c l e i n f o a b s t r a c t

Article history: This paper aims to present a detailed systematic approach to identify the main design parameters of PIN
Received 24 March 2020 power diodes. Firstly, the diode physical parameters are initialized using simple analytical equations. The
Revised 14 February 2021 second phase is the optimization of the diode parameters considering PSPICE circuit simulation where an
Accepted 20 February 2021
electro-thermal physically based circuit model is utilized depending on a series of dynamic and static
Available online 13 March 2021
measurements. The final optimization step is carried out by using TCAD simulations. First, the diode
extracted parameters are used to virtually fabricate the diode by using a process simulator. Then, using
Keywords:
the output of the process simulator, a device simulator is used to get the desired output that is validated
PIN power diode
Parameters extraction
against experimental data. Three case studies for different power diodes are presented showing a good
PSPICE agreement between circuit/device simulation results and measurements. The presented methodology
TCAD provides high accuracy like TCAD-based parameter extraction procedure with less time. In addition, it
gives higher accuracy than the widely used circuit-based parameter extraction technique.
Ó 2021 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Ain Shams Uni-
versity.d by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creative-
commons.org/licenses/by-nc-nd/4.0/).

1. Introduction line diodes, they are generally designed to be used in applications

The power PIN diode is one of the most popular semiconductor
power devices. It is widely used in automotive and power train
electronic systems [1]. Both the design and the technology of
power devices are progressing extensively. Thus, their perfor-
mance concerning conduction current, forward voltage and
switching losses are required to be evaluated appropriately. In gen-
eral, power diodes are classified into two broad classes. The first
class is the Line Diodes, whereas the second one is the Fast Recov-
ery Diodes (FRDs) [1]. Both types of power diodes are generally
designed as a PIN diode in which a middle intrinsic layer, called
i-layer, exists between two heavily doped emitters [2]. Concerning
⇑ Corresponding author.
E-mail address: Ahmed.shaker@eng.asu.edu.eg (A. Shaker).
Peer review under responsibility of Ain Shams University.
Production and hosting by Elsevier
where low forward conduction losses are required and switching
losses have a secondary role [2]. As the low forward conduction
losses are of major concern in line diodes, a high carrier lifetime
in the middle layer is required [2,3]. Regarding FRDs, on the con-
trarily, the switching losses play an important impact. FRDs have
a major role in power conversion applications as an auxiliary com-
ponent of the main switch. So, to improve the dynamic perfor-
mance of FRDs, the charge carrier lifetime in the middle layer
must be reduced [4].
To design a power electronic system, computer simulation is
mandatory to predict the behavior of the system. To simulate a
power electronic converter, circuit models of semiconductor power
devices are required [5]. The validity of a semiconductor device
model depends on the model parameters and equations. Such
parameters have to be extracted accurately to cope the device
behavior effectively although it is extremely difficult to obtain
the accurate technological parameters of the power diode, or any
power device, from manufacturers. Thus, the identification of the
design parameters of the power diode, as an essential part of the
converter design, is critical for circuit design issues. The optimum
circuit model parameters improve the simulation results accuracy

https://doi.org/10.1016/j.asej.2021.02.005
2090-4479/Ó 2021 THE AUTHORS. Published by Elsevier BV on behalf of Faculty of Engineering, Ain Shams University.d by Elsevier B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
A. Shaker, M.S. Salem, A. Zekry et al.
[5]. Thus, the choice of the circuit model is very important to get
satisfied simulation results.
To choose a suitable circuit model for the power diode, it must
satisfy certain requirements. One of the most important issues is
that the model should be physically based to take the effect of
device structure and its fabrication processes into consideration.
Also, simulation results using these model parameters should
replicate the terminal characteristics of the device accurately.
The main difficulty in designing such models is the distributed nat-
ure of the charge transport in semiconductor power devices which
could be designated by means of the ambipolar diffusion equation
(ADE) [6].
There are a lot of physically based models in the literature
which solves the ADE numerically under a variety of simulation
environments specially PSPICE. A model uses Laplace transform
to transform the ADE from the time domain into s-domain has
been developed [6,7]. Further, Fourier series is adopted as a
method to solve the ADE [8–10]. Furthermore, a model imple-
mented as a PSPICE sub-circuit using the finite difference method
(FDM) has been proposed in [11,12]. Moreover, the finite element
method (FEM) approach was utilized in a model, implemented in
PSPICE, that solves the ADE through a variational formulation
[13,14].
In all above models, the ADE is only solved at high-injection
level. Recently, a physically based model by solving the ADE is
developed under all injection levels [15–17]. The method of solving
the ADE under all injection levels reinforces the modeling tech-
nique and provides more accurate results [17]. This model is used
throughout the work in this paper.
There are many researches which focus on the issues of semi-
conductor power devices modeling [6–12]. However, regarding
semiconductor power devices parameter extraction or identifica-
tion issues, very few studies are carried out [5,10,18]. The param-
eter extraction performed by previous works either lacks the
simplicity of their implementation or the accuracy of the obtained
results. In [5], TCAD optimization is used to extract the power
diode design parameters. Although the high accuracy of this proce-
dure, it takes a lot of computational time; so, it cannot be used
extensively. In [10,18], PSPICE optimization routines are used to
extract the parameters based on reverse recovery processes. This
method is relatively effective regarding computational time; how-
ever, it lacks the accuracy as it is usually based on a single reverse
recovery measurement and does not take wide range of measure-
ments into consideration.
In this paper, a detailed systematic procedure to extract the
main design parameters of both types of power diodes, line and
fast recovery, is provided. There are three phases for extracting
the device main design parameters. The first phase of the proce-
dure is to relate the physical design parameters of the diode to cir-
cuit parameters which are considered design specifications. Simple
analytical equations are provided which take the main physical
behavior of the diode into account. The second phase is to fit the
circuit results considering a series of measurements using a
PSPICE-based electro-thermal model. The final phase comprises a
validity check performed by TCAD simulation. In this last phase,
the design parameters are trimmed in order to get more accurate
device simulation results compared to measurements. Three differ-
ent examples are provided to demonstrate the effectiveness of the
presented extraction method; one for the line diode and two for
FRDs.
2. Power diode basic parameters and modeling
Fig. 1 shows a typical power diode structure with its doping
profile and main parameters. Fig. 1(a) illustrates the basic structure
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Ain Shams Engineering Journal 12 (2021) 3141–3155
of the diode and Fig. 1(b) demonstrates an example of doping pro-
file along the diode width. As shown in Fig. 1(a), the power diode
structure consists of three regions, the cathode, the base region
and the anode. The cathode is a highly doped n region (n+), the base
region is a lightly doped n region (n-) and the anode is a highly
doped p region (p+). The base region width is denoted by WB and
its doping concentration is ND with a high-level lifetime sHL and
a low-level lifetime sLL. The power diode structure shown in
Fig. 1(a) is generated using Athena process simulator (version
5.22.3.R) of Silavco TCAD tool [19]. For the TCAD simulations, Atlas
device simulator (version 5.26.1.R) [20] is utilized considering the
following models. The device is described through the standard
drift diffusion physics-based transport model. Other models
include mobility doping dependent, carrier-carrier scattering, tem-
perature, and electric field, bandgap narrowing, Shockley-Read-
Hall (SRH) recombination and Auger recombination. The actual
doping profile is analyzed as shown in Fig. 1(b).
Further, Fig. 1(c) shows the carrier concentration and the possi-
ble depletion region (at the p+-n- side) and drift zone (at the n--n+
side) under a reverse recovery process. The figure also indicated
that the diode base region, according to the circuit model used, is
discretized into elements whose number is N and Dx is the width
between two adjacent elements. In addition, the corresponding
voltage drops are also illustrated.
Under steady state conditions, the hole concentration inside the
base is given by,
sinh½ðW B  xÞ=La  sinhðx=La Þ
pðxÞ ¼ px1 þ px2 ð1Þ
sinhðW B =La Þ sinhðW B =La Þ
Where px1 and px2 are the concentrations at the borders  = 0
and  = WB and La being the ambipolar diffusion length which is
given by,
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffiffi u
u2sSRH V T ln lp
La ¼ DsSRH ¼ t   ð2Þ
ln þ lp
Where D is the diffusion constant, VT is the thermal voltage and
ln and lp is the electron and hole mobility, respectively. Based on
the Shockley–Read–Hall model, the lifetime sSRH depends on the
level of injection where for high-level injection: sSRH = sHL while,
for low-level injection: sSRH = sLL [17]. To calculate the total voltage
drop, the diode is divided in several parts including the junctions,
base and depletion regions. The junction voltages are given by [21],
 
px1 ni
V j1 ¼ V T ln þ ð3aÞ
ni ND
 
px2 þ ND
V j2 ¼ V T ln ð3bÞ
ni
The voltage drop across the lightly doped drift region can be cal-
culated as follows,
ID XN
Dx
VB ¼ ð4Þ
qA i¼1 pi ðln þ lp Þ þ ln ND
Finally, the total diode voltage can be calculated by summing
the relevant voltages, (where Vd1 and Vd2 are the depletion regions
voltages),
V AK ¼ V j1 þ V j2 þ V B  V d1  V d2 ð5Þ
More details about the electrothermal model and its equations
can be found elsewhere [15–17,19].
A. Shaker, M.S. Salem, A. Zekry et al. Ain Shams Engineering Journal 12 (2021) 3141–3155

(a) (b)

(c)
Fig. 1. (a) Basic power diode Structure generated by Silvaco/Athena, (b) Absolute doping profile along the diode length and (c) Carrier concentration and depletion region
under a reverse recovery process showing the corresponding voltage drops and discretization used in the circuit model.

2.1. Power diode parameters Identification: Table 1

Main technological and physical parameters of the power diode including temper-
ature dependencies.
In this section, the relations between the PIN diode circuit
parameters and its physical design parameters are illustrated. Parameter Name/Unit Temperature Dependence
Firstly, a comprehensive review of the main physical and circuit Equation

design parameters involved in the parameter extraction methodol- A Area (cm2)

ogy is provided. Then, the relations between these parameters are WB Base width (lm)
ND Base doping (cm3)
presented. There are five main design and technological parame-  
sHL High lifetime (sec) sHL ¼ sHL300 T b
ters for the PIN power diodes. These parameters are its active die 300
3002:5
hn and hp Recombination h- hn;p ¼ hn;p300
area, A, its drift region width, WB, its impurity doping density in parameters
T

the base region, ND, its effective high-level lifetime, sHL and its ln Electron mobility 
ln ¼ 1350 300 2:5 
T
recombination h-parameters, hn and hp. The identification lp 3002:2
Hole mobility lp ¼ 495 T
approach of finding these physical parameters is accomplished 7000
ni Intrinsic concentration ni ¼ 3:88  1016 ðT Þ1:5 =exp
considering the circuit parameters which are: 1) Repetitive maxi- T

mum voltage, VRRM, 2) DC forward current, IF and 3) Reverse recov-

ery parameters: peak current (IRM), and time (trr).
Table 1 summarizes the main technological and physical
parameters of the power diode. Also, the temperature dependence
of these parameters is indicated. The exponent b (used in lifetime
calculation) appears in the table is a fitting parameter that could be
found from a reverse recovery measurement and its value is
around 1.5. It is worth mentioning here that our model is capable
in simulating circuits in a wide temperature range from – 150 °C to
150 °C.
Although the presented model captures most of the physical
behaviors of the diode under different operating conditions, there
are some limitations of the usage of this model in circuit simula-
tion. Some of these limitations are the lack of the model to capture
the snappy recovery that occurs in high voltage devices. Also, the
effects of local lifetime control are not included. Moreover,
punch-through and dynamic avalanche are not invoked. The inclu-
sion of these models could be done, and more work is needed to
expand the validity of the presented model.
Fig. 2 shows the flow chart which describes the procedure used
for the power diode parameters extraction. By using the value of
VRRM, both of WB and ND of the base region are predicted. From
the value of IF, the area A is estimated. Further, by using the rela-
tion between VF and sHL, the high lifetime is estimated. This value
is used to get a more corrected value using the reverse recovery
operation. The h-parameters are estimated according to the emit-
ter shape which is assumed to be nearly abrupt.
After obtaining an initialization of the design parameters from
the analytical expressions, an optimization is performed using

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A. Shaker, M.S. Salem, A. Zekry et al.
Fig. 2. A flow chart summarizes the extraction procedure.
the aforementioned physically based PSPICE model in circuit sim-
ulation. Then, the extracted parameters of the power diode are
used for virtually constructing a power diode device using Silvaco
TCAD process simulator. The results of some practical measure-
ments are compared with Silvaco device simulation results to trim
the extracted parameters and to verify the obtained parameters
extraction accuracy.
The presented method of parameter extraction used in this
paper does not involve the DC characteristics solely. The reason
is that, there are a lot of fitted parameters that could be used to
match the DC behavior of simulation and measurements or data-
sheet values. These parameters may not be physically based and
can affect the accuracy of the other physical parameters. So, in
addition to the DC characteristics, the reverse recovery processes
are used to extract the key physical parameters of the diode
because they reflect the internal physical processes occurring
inside the diode during the injection.
2.2. Power diode parameter initialization
2.2.1. Active die area
An appropriate value of the active die area A is obtained from
the forward current IF which is indicated in the device datasheet.
Since the maximum current density J for most power diodes ranges
from 100 A/cm2 to 150 A/cm2, so, the area A is initialized as,
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Ain Shams Engineering Journal 12 (2021) 3141–3155
IF
A¼ ð6Þ
J
Here, the circuit constraint (IF) is related to a design parameter
(A). The temperature effect is another parameter which has to be
considered in the extraction of A. When the power diode operates
at high temperatures, its area should be enlarged such that it can
sustain the heat effects [22]. In such case, a safety factor of about
50% has to be taken into consideration [10]. However, the larger
area causes the high cost of the device. Considering these con-
straints may affect the decision based on Equation (6). The real
value depends on the manufacture and the choice of safety factors.
So, a better estimation of the area could be done by measuring it
directly. The area can also be estimated by fitting the oscillation
of a reverse recovery process, a step that could complicate the
extraction technique but is essential in the case of unavailability
of the measured area [5].
2.2.2. Base width and doping
In normally designed power diodes, the breakdown voltage
(VBR) is related to the base width (WB) and base doping concentra-
tion (ND) [1]. Many design curves for the different breakdown volt-
age values are offered by simple theory methods [23–25].
In [5], simulations are carried out using the quasi-stationary
mode of Dessis-ISE TCAD [26] as the reverse-bias operation of
the diode is mainly governed by the Poisson equation. In the
A. Shaker, M.S. Salem, A. Zekry et al.
Fig. 3. Power PIN diode breakdown voltages versus base doping for different values
of base width: TCAD (symbols) vs analytical solution (lines). The p+n junction
behavior is shown as a reference.
approach used in this paper, an analytical expression that relates
the breakdown voltage with the base width and doping is chosen.
Then, a verification is done by Silvaco TCAD using the same tech-
nique as [5] to check the validity of the used equation. The analyt-
ical equation chosen to relate VBR is related to the base width and
doping concentration is given by [2],
 1=8
8qND 1 qN D 2
V BD ¼ WB  WB
eB 2 e
Where B = 2.11  1035 cm6/V7 and e is the dielectric permittiv-
ity of the Silicon material. Fig. 3 shows the breakdown voltages of
the power PIN diode versus base doping for different values of WB.
The regular pn junction behavior is drawn as a reference. The figure
compares between the power diode analytical model, drawn as
lines and TCAD results, drawn as symbols. It is obvious that both
results are too close to each other. Thus, the analytical model is
verified using TCAD simulations.
Now, a trade-off for low forward voltage drop and large break-
down voltage has to be obtained. In order to calculate the forward
(a)
Fig. 4. (a) Base width versus doping concentration for various values of breakdown voltages. (b) Behavior of VF w.r.t ND.
Ain Shams Engineering Journal 12 (2021) 3141–3155
bias VF, an analytical expression is used which is based on [16]. To
achieve the minimum possible forward bias, the analytical models,
breakdown and forward voltage drop at a certain current density
level (100 A/cm2), are used to determine the optimum value of
WB and ND. Fig. 4(a) shows the results of the optimum required
doping concentration of the lightly doped drift region and base
width for various values of breakdown voltage (BV). The optimum
of WB and ND are marked in Fig. 4(a). These points are extracted to
give the minimum forward voltage as can be depicted from Fig. 4
(b).
It should be pointed out here that the breakdown voltage of the
power diode is usually not specified in datasheets. Instead, the
repetitive maximum voltage VRRM is given and it is considered a
design specification. To get the breakdown, a safety factor has to
be taken. This factor is usually located between 20 and 50% [10].
This safety factor may differ from manufacturer to another. Based
on this factor, VBR can be related to VRRM by,
V BR  1:2 to 1:5 V RRM ð8Þ
Where VRRM is extracted from the power diode datasheet. As the
safety factor may not be taken by some manufacturers, it is pre-
ferred to measure the breakdown voltage to get an accurate value.
2.2.3. Recombination h-parameters
To be able to design the power diode emitter, an analytical
expression is used for calculating the Gummel number (GE) [27].
Thus, the emitter h-parameter can be found (where h = 1/GE). For
the case of n-type uniform distribution, the expression for the
emitter Gummel number is given by,
Z xj Ln
n2io NE ðxÞ
GE  dx ð9Þ
0 n2ie DE ðxÞ
ð7Þ Where xj is the emitter junction width, Ln is the electron diffu-
sion length, NE is the emitter doping concentration, DE is the diffu-
sion constant, nio is the intrinsic carrier concentration at thermal
equilibrium, nie is the effective intrinsic concentration which
appears as a result of Band Gap Narrowing (BGN) [28].
By applying Eq. (9) for different emitter properties, Fig. 5 shows
the variation of the emitter h-parameter with emitter doping for
different values of junction widths for boxed-type emitter profiles.
As indicated in the figure, when the emitter width increases, a min-
imum value is obtained for the h-parameter (hmin) at a certain con-
centration. As the emitter width increases, the concentration at
which hmin occur decreases. For a given value of emitter width,
(b)
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i(t)

ts
IF
t
IR

Fig. 7. Current waveform in a step recovery process.

chosen. It has to be suitably fits the required value of VF. In calcu-

Fig. 5. Variation of emitter h-parameter with emitter doping concentration for
boxed type profiles.
Fig. 6. Variations of VF with sHL at IF = 5 A.
the h-parameter firstly decreases with doping concentration until
it reaches a minimum value. Then, the h-parameter increases
lating VF, the Conwell-Weisskopf screening theory [31], with its
physical parameters kept unchanged, is found to be very suitable
for computing the DC characteristics considering the carrier-
carrier scattering [16]. Fig. 6 shows Silvaco simulations along with
the circuit model. Also, the results of Hall theory are included [32].
In this case study, a typical power diode is chosen whose parame-
ters are as follows. The area is taken to be A = 0.05 cm2 with a cur-
rent rating of IF = 5 A. The base width is WB = 85 lm, with base
doping of ND = 1.5  1014 cm3. The emitter surface doping concen-
tration is 1  1020 cm3 with Gaussian profile of depth about
15 lm for both the anode and the cathode. The analytical model
is used to predict the value of sHL which gives the maximum
required VF. A range of sHL which could be used is found. For
instance, if it is required to have VF(max) = 1.1 V, then sHL has to
be greater than 200 ns.
The value of sHL calculated above is taken as an estimate value.
To find a more accurate value of the high-level lifetime, the turn-
off design requirements should be taken into consideration. There
are two types of turn-off processes, namely the step and ramp
recovery according to the type of the power diode. In line diode,
step recovery is considered while, for the FRDs, ramp recovery is
utilized.
Regarding the step recovery process, the PIN diode starts in
steady state at forward bias current, IF. At time t = 0 it is put under
reverse bias, by means of a voltage VR in series with a resistance R.
Here, phase 1 ends at time ts as depicted from Fig. 7. Defining Ts = ts
/ sHL and W = WB / La, analytical expressions could be found from
which we can get relations between IF, IR, WB, and Ts [33]. The fol-
lowing design equation is used here to get the lifetime given WB
and the time parameters. In equation (10), b is the mobility ratio
and all other parameters are indicated in Fig. 7.
pffiffiffiffiffi
IR ERFð T s Þ Ts
¼ when 2 < 0:075
IF þ IR coth W þ b sinh
1
W
W

slowly again. The increase of the emitter h-parameter at lower

ð1þbÞeT s expðp2 T s =W 2 Þ
emitter doping concentrations is a result of the increase in mobility
IR
IF þIR
¼ bW½cothWþ  ½1 þ 2ðb1Þ 
1þ p
1  bþ1 2

and the diffusion constant. The increase of the emitter h-parameter

bsinhW
W2 ð10bÞ
at higher concentrations results from BGN [29]. when Ts
W2
> 0:075
The emitter is designed to be a good emitter. Thus, it has high
surface concentration and relatively small depth. So, the h-
parameters are chosen to be as small as possible [10,29]. A value i(t)
of 1  10-14 cm4/s is typical which could be used as an initial value. to trr

2.2.4. High-level lifetime tA tB

Many approaches are followed to find the high-level lifetime sHL IF
[30]. The difficulty of the lifetime extraction comes from that it has
to meet different specifications. Tradeoffs are done to choose sHL to t
meet most of the requirements. In the approach used in this paper, IRM 25% IRM
the first step to find an initial value for the high-level lifetime, sHL, diF/dt
which is done according to the constraint given about VF. There is a
certain maximum value for VF at a given current level. So, given VF
at IF, VF versus sHL can be drawn. The required value of sHL can be Fig. 8. Transient current waveform of a reverse recovery process.

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Fig. 9. Variation IRM and trr with sHL both Silvaco and PSPICE simulations.

For ramp recovery, the design equations provided in [34] are 3.1. Line diode 12FR100
used, where a method relying on a charge control model and
assuming a triangular current waveform is presented. The reverse The 12FR100 is a standard recovery diode that is recommended
recovery process is shown in Fig. 8 assuming a triangular current for use in converters, power supplies and battery chargers [35].
waveform. By using this approach, a relation between sHL and Some design specifications from its datasheet are presented in
the current waveform parameters; to, tB, and tA (all parameters Table 2. Its main DC constraints are VRRM, IF, and VF. In the data
are indicated in Fig. 8) is given, sheet of this power diode, there are no constraints for trr.
The die active area is initialized by assuming a forward current
tB ðt o þ t A Þ density of 100 A/cm2. This gives an area of A = 0.12 cm2. The break-
expð Þ ¼ 1 þ S  S  expð Þ ð11Þ
sHL sHL down voltage VBR is assumed to be about 1200 V, taking a margin of
Where S (=tB/tA) is the softness factor. Further, we can get to 200 V (which is 20% of VRRM). Then, ND is found to be 1.1  1014
approximately by, cm3 and WB equals to 85 mm, referring to the aforementioned
analysis.
IF To extract the high-level lifetime sHL, firstly, the DC I-V charac-
to  ð12Þ
diF =dt teristics for IF = 12 A is examined. Fig. 10 shows VF for different val-

Table 2
Main design specifications of 12FR100
2.3. Circuit-Device simulation power diode.

VRRM 1000 V
In the first phase, the usefulness of the analytical expressions to
trace the behavior is indicted. The second phase of design is carried IF (average) at 144 °C 12 A
out to verify and refine the power diode design parameters. This VF (maximum) at 25 °C 1V

phase is done via circuit simulation of the device. In this phase,

the model developed in [17] is used to get more insight about
the device and try to optimize its design parameters to fit measure-
ments. As a validation for the previous analysis; an example using
PSPICE to see how the model could characterize the circuit param-
eters is carried out. In this example, the same diode parameters in
subsection (3.1.4) is used. In addition, diF/dt is taken to equal to be
100 A/ls. As can be seen from Fig. 9, the agreement is good enough
between Silvaco (device) and PSPICE (circuit) simulations for both
trr and IRM. (taking S  1 on the average).

3. Case studies

In this section, three case studies for the two different types of
the power diodes are presented. The main objective of introducing
these case studies is to demonstrate the procedure of the presented
design parameter extraction. The first case study considers a line
diode 12FR100. The second and third case consider fast diodes
BYT12PI600 and CS240610. In all cases, the extraction of the design
parameters is presented in detail. A comparison between the cir-
cuit model simulation results and the practical measured results
is carried out. Finally, some practical measurements are verified Fig. 10. Voltage forward drop variation with sHL taking IF = 12 A for the line diode
using Silvaco TCAD simulator. 12FR100.

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A. Shaker, M.S. Salem, A. Zekry et al.
ues of sHL ranging from 200 to 800 ns. As VF(max) = 1 V from the
datasheet given in Table 2; so, sHL is predicted to be about
500 ns or higher. A higher value is desirable for lower forward volt-
age. Also, a higher value of lifetime is not a problem because the
main concern of this diode is not its recovery time as it is a stan-
dard slow recovery power diode. So, sHL can be predicted to be
even higher than 1 ms to minimize VF.
In addition, a dynamic performance measurement of the diode
under investigation is carried out. A proposed circuit which simu-
lates a step recovery process is shown in Fig. 11 [15]. The NMOS
and PMOS in Fig. 11 are n-channel and p-channel power MOSFETs
rated at 40 A. The two supplies VDD and –VDD are varied from a DC
power supply. The switching frequency should be increased for the
storage effects to be visible. So, the frequency of the pulse genera-
tor is kept at 25 kHz. Two measurement cases are considered. In
case 1, R2 = 10.1 X, R1 = 1.2 X, VDD = 5 V and -VDD = -5 V. In case
2, R2 = 5.0 X, R1 = 1.2 X, VDD = 10 V and -VDD = -8 V. A pulse gen-
erator is used for exciting both of NMOS and PMOS transistors. For
case 1, the pulse heights are at ± 5 V, while for case 2, they
are ± 10 V.
Fig. 11. A proposed circuit for measuring the dynamic performance of the line diode 12FR100.
(a)
Fig. 12. Case 1: Measured and simulated waveforms: (a) current ID through, and (b) voltage VD across the diode.
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Ain Shams Engineering Journal 12 (2021) 3141–3155
A set of values for IF, IR, and ts are taken from measurements of
the two cases. Following Equation (10), an estimated value of sHL. it
is found to be about 7.5 ms for WB = 85 mm. Here, it should be
emphasized that this sHL value is typical for standard recovery
power diodes as the main concern, in this case, is the low forward
voltage drop which results in minimizing the losses.
Regarding case 1, the measured and simulated current wave-
forms are given in Fig. 12(a), while the measured and simulated
voltage waveforms are shown in Fig. 12(b). The corresponding cur-
rent and voltage waveforms for case 2 are also shown in Fig. 13(a)
and (b), respectively. To account for the parasitic effects resulting
in measurements, the wiring inductance is taken into considera-
tion for the simulation to give the best fit vs measurements as
can be depicted from the figures. A parasitic inductance whose
value is about 2 mH is put in series to R2 to account for the wiring
inductance. Besides, the simulation without parasitic effects is
illustrated in case 2 as parasitic effects are effective for higher cur-
rents. A good agreement between measurements and simulations
could be observed. An optimization routine is performed to get
the best fit by varying the values of ND and WB. The final values
(b)
A. Shaker, M.S. Salem, A. Zekry et al. Ain Shams Engineering Journal 12 (2021) 3141–3155

(a) (b)
Fig. 13. Case 2: Measured and simulated waveforms (a) current ID through, and (b) voltage VD across the diode.

Table 3
Experimental and simulation results of the dynamic performance of the line diode 12FR100 at f = 25 kHz.

ts (ms) IF (A) IR (A) VF (V) VR (V)

Case Meas. Sim. Meas. Sim. Meas. Sim. Meas. Sim. Meas. Sim.
1 3.4 2.8 0.333 0.326 0.61 0.61 1.20 1.16 5 5
2 4.0 4.1 0.680 0.720 0.91 0.85 1.90 1.71 8 8

for these two parameters are ND = 1  1014 cm3 and WB = 90 mm V Y Z d þ Rm

¼ ¼ Re þ jIm ð13Þ
which are so close to the initial values. VX Rm
Moreover, Table 3 illustrates the experimental and simulation
Where
results of the dynamic performance of the line diode 12FR100 at
Zd = Rd + jXc (14)
f = 25 kHz for the two cases. Matched values for the performance
Then,
parameters ts, IF, IR, VF and VR are observed to a high extend. Some
differences in parameters values between model and measure- Rd
Re ¼ 1 þ ð15Þ
ments are found which are accounted for by parasitic effects espe- Rm
cially for ts in case 1 where we have not taken the parasitic effect
into account. Xc
Finally, some additional experiments are carried out to confirm
Im ¼ ð16Þ
Rm
the validity of the design parameters extraction. The C-V character-
A typical ellipse is seen in Fig. 14(b) resulting when X-Y mode is
istic of the diode is measured. Fig. 14(a) shows the circuit used in
active. The magnitude of Rm is approximately equal that of Xc when
measuring the capacitance for different values of applied reverse
the following condition is fulfilled:
voltages.
The diode is represented as impedance with Rd and Xc. To mea- Peak 1
sure the capacitance, two voltages VX and VY are connected to X- ¼ ð17Þ
Intercept 0:707
and Y-channel of an oscilloscope and adjusting it in X-Y mode. Then
the relation between VX and VY is found to be, Fig. 15 shows the corresponding capacitance of the diode versus
the reverse voltage. Now, both design and technological parame-
ters could be used to fabricate the device virtually using Athena

Intercept Peak

(a) (b)
Fig. 14. (a) The circuit used for measuring C-V characteristics. (b) Oscilloscope output for X-Y mode of the circuit.

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of Silvaco TCAD tool. This is the second phase for trimming the Table 4
design parameters. In Fig. 15, the C–V characteristics using Silvaco Comparison of the three phases of parameter identification of 12FR100 diode.

is also shown in comparison with measurements. Good agreement Initial Circuit Optimization TCAD Optimization
is observed by trimming the area to be 0.1 cm2. A (cm )2
0.12 0.12 0.1
As a final validation of the extracted parameters, the capaci- WB (lm) 85 90 100
tance behavior using an analytical equation which is valid for a ND (cm3) 1.1  1014 1  1014 1  1014
p+ n junction and can be applied for our PIN diode to extract the sHL (ls) 1–7.5 7.5 7.5

area given base doping is checked. The junction capacitance can

be approximated by the usual formula,
2
1 slope ¼ ð19Þ
Cj ¼  1=2 ð18Þ qer eo ND A2
1  uV
The area A is found to be 0.1 cm2 from Equation (19) which
By plotting 1/C2, the built-in potential u can be found. As can be meets the value of the TCAD simulation, and it is not far from
depicted from Fig. 16; u  0.5 V. Then, the diode area from the the value specified by the design equation. Further, the value of
slope of the line (knowing the doping of the base ND = 1  1014 WB has been adjusted to get the best fit from 90 to 100 lm. Finally,
cm3) as, Table 4 presents the four diode parameters (A, WB, ND and sHL) for
the three phases: initial phase by design equations, circuit and
TCAD device optimizations. It is evident from the table that very
little trimming is applied when using TCAD. In addition, a practical
doping profile, like the one shown in Fig. 1(b), is utilized when vir-
tually fabricating the power diode under investigation. That is why
the base width is different from the circuit analysis value. Also, it
can be concluded here that the design equations used can fulfill
satisfactorily the estimation of design parameters. This is always
true for any kind of Line diodes.

3.2. Fast diode BYT12PI600

The BYT12PI600 is a fast recovery diode that is recommended

for use in converters, motor control circuits, and as a rectifier in
Switched Mode Power Supply (SMPS) [36]. Some selected design
specifications from its datasheet are presented in Table 5. The main
DC constraints are VRRM, IF, and VF. The main reverse recovery con-
straint is trr at certain conditions.

Table 5
Main design specifications of BYT12PI600 power diode.

VRRM 600 V
Fig. 15. Plot of C versus reverse voltage: Silvaco simulation vs. measurements. IF (average) 12 A
VF (maximum) at 25 °C 1.9 V
trr (maximum) at diF/dt = 15 A/ms and IF = 1 A 120 ns

Fig. 16. Plot of 1/C2 vs. reverse voltage. Fig. 17. Voltage forward drop variation with sHL taking IF = 12 A for BYT12PI600.

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A. Shaker, M.S. Salem, A. Zekry et al.
The die active area could be found by assuming a forward cur-
rent density of 100 A/cm2. This gives an area of A = 0.12 cm2. Next,
the breakdown voltage is VBR is initialized to be about 700 V
assuming a margin of about 100 V. So, the initial value of ND is
1.5  1014 cm3 and that of WB is 40 mm.
To extract the high-level lifetime sHL, the DC I-V characteristics
is firstly examined for IF = 12 A. Fig. 17 shows VF for different values
of sHL ranging from 50 to 500 ns. Knowing that VF(max) = 1.9 V, sHL is
predicted to be about 90 ns or higher. Concerning the constraint
about trr, to is firstly calculated for the given condition. Then, sHL
is estimated to be about 120 ns to 150 ns according to an estimated
value of S = 1 using Equation (11). Finally, the h-parameters are ini-
tialized to be 1  10-14 cm4/s.
To begin the second phase, the circuit model is used within a
reverse recovery circuit (Giving: forward current IF = 2 A, reverse
voltage VR = 40 V and main inductance LD = 80 nH). The experimen-
tal results are extracted from Ref. [37]. Taking the initial values just
calculated, an optimization routine is applied to match the exper-
imental voltage waveform with that of the model by varying some
design parameters and obtaining the best fit. The optimization is
done as follows: first, a search for a suitable value for sHL starting
from 90 ns and ranging to about 150 ns is carried out. Then, the
(a)
Fig. 18. Circuit simulation vs measurements: (a) current, and (b) voltage waveforms of a reverse recovery process of BYT12PI600.
(a)
Fig. 19. Silvaco simulation vs measurements: (a) current, and (b) voltage waveforms of a reverse recovery process of BYT12PI600.
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Ain Shams Engineering Journal 12 (2021) 3141–3155
estimation of the base width WB can be improved by matching
the diode voltage waveform. The doping ND is refined according
to the peak of the voltage waveform. The effect of sHL is found to
be the most dominant effect. Also, WB and ND are found to have
minor effects on the current waveform.
The optimized values of the design parameters are: sHL = 115 ns,
WB = 52 mm, ND = 2.2  1014 cm3 and A = 0.12 cm2. The h-
parameters are adjusted at hp = hn = 1  10-14 cm4/s. It is noticed
that the base width and doping are not optimized according to
the design approach used in this paper as the safety factor taken
for breakdown calculation is not that taken by the manufacturer.
This can be checked by measuring the breakdown voltage. The
measured VBR, for this power diode, is found to be 630 V [38].
Fig. 18(a) shows the current and Fig. 18(b) shows the voltage ()
waveforms of the experimental and the circuit model used in this
paper. As can be depicted from the figure, the model values of VRM,
IRM and trr are very close to measurements. An error of about 5% is
found in VRM, and 4% error in trr, and no error in IRM.
It is emphasized here that the extraction method presented in
this paper is based on a comparison between the simulations of
VRM, IRM, and trr and the corresponding measured values of these
circuit parameters. Hence, it is not practically to try to fit the whole
(b)
(b)
A. Shaker, M.S. Salem, A. Zekry et al. Ain Shams Engineering Journal 12 (2021) 3141–3155

Table 6 Moreover, a comparison between the measured and Silvaco

Comparison of the three phases of parameter identification of BYT12PI600 diode. results is carried out. The circuit used in measurements has the fol-
Initial PSPICE optimization TCAD lowing parameters: forward current IF = 2 A, reverse voltage
VR = 150 V and main inductance LD = 130 nH [39]. Fig. 19 shows
A (cm2) 0.12 0.12 0.12
WB (lm) 40 52 56 the comparison between the two results. It is obvious that the val-
ND (cm3) 1.5  1014 2.2  1014 2.3  1014 ues of IRM, trr and VRM are very close. Thus, there is a good agree-
sHL (ns) 90 115 100 ment concerning the validation of the measured results in
comparison with the TCAD simulator results.
Further, the values of the power diode parameters are listed in
Table 7 Table 6 for the various cases; namely, initialization, circuit and
Main design specifications of CS240610 power diode. TCAD optimization.
VRRM 600 V
IF (average) 100 A 3.3. Fast diode CS240610
VF (maximum) at 25 °C 1.5 V
trr (maximum) at T = 150 °C, diF/dt = 200 A/ms VR = 300 and IF = 100 A 800 ns As a second case study for a FRD, a Powerex device (CS240610)
Qrr at T = 150 °C, diF/dt = 200 A/ms VR = 300 and IF = 100 A 60 lC rated at 600 V/100 A is considered. This diode has been optimized
to be used in IGBTs circuits [40]. Some selected design specifica-
tions from its datasheet are presented in Table 7.
region of simulation particularly in the end phase of the transient The die active area could be found by assuming a forward cur-
waveforms. Many authors declared that a usual disagreement after rent density of 100 A/cm2. This gives an area of A = 1 cm2. However,
the first oscillation current and voltage waveforms is usually found the diode area is measured and found to be 0.5 cm2 [40]. This
[38]. This is related mainly to a complete circuit behavior due to shows that the diode parameters could be unoptimized and special
parasitic inductances. designed by the manufacturer. Moreover, although VRRM is listed in

(a) (b)
Fig. 20. Measured and simulated current and voltage waveforms at T = 27 °C.

(a) (b)
Fig. 21. Measured and simulated current and voltage waveforms at T = 150 °C.

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A. Shaker, M.S. Salem, A. Zekry et al.
(a)
Fig. 22. Measured and Silvaco simulated current and voltage waveforms at T = 27 °C.
Fig. 23. Measured and Silvaco simulated reverse biased characteristics.
datasheet as 600 V. the blocking capability of this diode is 900 V as
measured in Ref. [41]. So, a safety factor of 50% is taken into con-
sideration. Based on this measured VBR, the initial value of ND is
1.2  1014 cm3, and that of WB is 65 mm. it should be mentioned
here that the measured values of VBR (=900 V) and A (0.5 cm2) are
considered to obtain more accurate parameter identification and
less time. Concerning the constraint about trr, to is firstly calculated
for the given condition. Then, sHL is estimated to be about 120 ns to
150 ns according to an estimated value of S = 1.
Next, some simulations are carried out in which the CS240610
model is put in a chopper cell whose parameters gives IF = 70 A,
reverse voltage VR = 350 V and main inductance LD = 330 nH. These
circuit parameters are measurements are extracted from [41].
Measurements and simulations are compared at two different tem-
peratures: 27 °C and 150 °C. Fig. 20 shows both current and voltage
recovery waveforms for the case of T = 27 °C, while Fig. 21 shows
the case of 150 °C. The small inductive voltage drop in the simu-
lated voltage waveforms is due to a stray inductance of 7 nH. Very
good agreement is seen between measurements and simulation
using the extracted parameters. This proves the success of the
parameter extraction and the model accuracy to trace the temper-
ature dependence of the parameters accurately.
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Ain Shams Engineering Journal 12 (2021) 3141–3155
(b)
Table 8
Comparison of the three phases of parameter identification of CS240610 diode.
Initial PSPICE optimization TCAD
A (cm2) 0.5 0.5 0.5
WB (lm) 65 70 75
ND (cm3) 1.2  1014 1  1014 1  1014
sHL (ns) 120 300 340
Further, a comparison between the measured and Silvaco
results using the extracted parameters from PSPICE is carried out.
The circuit parameters, in this case, are: IF = 100 A and reverse volt-
age VR = 300 V with the same main inductance LD = 330 nH. It can
be depicted from Fig. 22 that the values of IRM, trr and VRM are very
close. Thus, there is a good agreement concerning the validation of
the measured results in comparison with the TCAD simulator
results.
Moreover, Silvaco TCAD is used to simulate the DC reverse char-
acteristics. The results are shown in Fig. 23 where the reverse cur-
rent vs. the reverse voltage at 25 °C for both measurements [39]
and simulation are illustrated. Finally, the values of the power
diode parameters are recorded in Table 8 for the various cases;
namely, initialization, circuit and TCAD optimization. It is obvious
that both the circuit and TCAD optimization give relatively
matched values for the power diode parameters, A, WB, ND and
sHL. The differences in parameters values between model and TCAD
optimization are accounted for by mainly doping profiles. In TCAD,
actual Gaussian profiles are considered by using a process simula-
tor; however, regarding our model, abrupt profiles are applied for
simplicity.
4. Conclusion
In this paper, a comprehensive extraction procedure for the
design parameters of the power PIN diodes is presented. Firstly,
the main design and technological parameters are related to the
circuit parameters. The first phase of the parameter extraction pro-
cedure is to establish some analytical expressions as simple as pos-
sible to find initial values for these parameters. This phase is
followed by a series of measurements and comparing the circuit
PSPICE simulation results, based on a physically based model, with
these experimental results. In this phase, a refinement of parame-
ters is applied to fit the experimental data. Finally, the design
parameters are inputted to TCAD device mixed mode simulation
A. Shaker, M.S. Salem, A. Zekry et al.
to check the validity of the extraction procedure. Three case studies
are given and comparison against measurements are provided
showing good agreement. It was demonstrated that the design of
line diodes is easier than FRDs because their design is straightfor-
ward. On the other hand, the design of FRDs is more complicated
and the extraction of their parameters needs a lot of work.
The simulation and the matched results vs measurements verify
the validity and reliability of the presented method and shed a
light on the discrepancy between manufacturers and power elec-
tronics designers as some manufacturers put their design rules
which may not give the optimum performance. A lack of coopera-
tion between manufacturers and device design engineers is proba-
bly partially responsible for the delay in advancement of device
modelling in the power devices field because of the difficulties
faced in identification of the technological parameters.
The advantage of the presented methodology over the circuit
approach is that it gives the design parameters required for manu-
facturing the device. On the other hand, the circuit technique gives
only the model parameters which are not the same as the design
parameters as many simplifications are utilized in the circuit model.
Further, another advantage of the presented methodology is that the
steps could be done in reasonable times, while the TCAD approach is
computationally cumbersome. Overall, the advantage in this hybrid
approach is to provide a quicker way to obtain the main design
parameters although many steps are required. Moreover, we intend
to extend our work to obtain the parameters automatically by an
optimization technique based by genetic algorithms.
Declaration of Competing Interest
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared
to influence the work reported in this paper.
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Ahmed Shaker was born in Cairo, Egypt. He received the
M.Sc. and Ph.D. degrees in 2003 and 2010, respectively,
from Ain Shams University, Cairo, Egypt. He has been
with Engineering Physics Department, Faculty of Engi-
neering, Ain Shams University, since 1997, where he is
currently an Associate Professor. His fields of research
include simulation and modeling of semiconductor
power devices, solar cells, 3D detectors and nanoscale
devices including TFETs and CNTFETs.
A. Shaker, M.S. Salem, A. Zekry et al. Ain Shams Engineering Journal 12 (2021) 3141–3155

Marwa Sayed Salem Basyoni was born in Gedda, KSA in
1979. She received her Bs.C degree from Electronics and
Communications engineering department, Faculty of
engineering, Ain Shams University, Cairo Egypt in 2002.
She owned her master degree from the same university
in the field of renewable energy in 2006. Also, she
owned her Ph.D degree from the same university in the
field of renewable energy especially in solar cells in
2013. She worked as a research assistant in Ain Shams
University, faculty of engineering since 2003 till 2013.
Currently, she is the Vice Dean of the Computer College,
University Ha’il, Ha’il, Saudi Arabia. Her fields of
research interests includes VLSI design, MEMS technology, Nano technology,
Renewable energy, Solar Cell, PV systems, Semiconductor physics, simulation and
modelling of power devices.
Abdelhalim Zekry is a professor of electronics at fac-
ulty of Engineering, Ain Shams University, Egypt. He
worked as a staff member on several universities. He
published more than 250 papers. He also supervised
more than 104 Master thesis and 28 Doctorate. Prof.
Zekry focuses his research programs on the field of
microelectronics and electronic applications including
communications and photovoltaics. He got several pri-
zes for his outstanding research and teaching perfor-
mance.
G.T. Sayah is Associate Professor, Electronic Engineering
Department, Nuclear Materials Authority, Cairo, Egypt.
She received PhD and MSc from Ain Shams University,
Faculty of Engineering, Electronics and Communications
Engineering Department, Cairo, Egypt. Her area of
interest is Simulation and modeling of semiconductor
power devices, photovoltaic, and radiation detectors.
Mohamed Abouelatta was born in Cairo, Egypt. He
received the B.Sc., M.Sc. degrees in 1996 and 2001,
respectively, in Electronics and Communication engi-
neering from Ain Shams University (ASU). He received
PhD degrees from Ain Shams University and from the
National Institute of Applied Sciences (INSA) of Lyon,
France in 2010. He is now an Associate professor in the
Faculty of Engineering, ASU. His fields of research are
modeling, design and characterization of Power devices,
designing of Smart Power Integrated circuits, Nanode-
vices, Photovoltaic and 3D CMOS Heterogeneous Inte-
grated Circuits.

Mohammed M. El-Banna is Assosiate Professor, Engi-

neering Physics & Mathematics Department, Faculty of
Engineering (FE), Ain Shams University (ASU), Cairo,
Egypt. He received the B.Sc. degree in Electronics and
Communication engineering from ASU. He received the
M.Sc. and PhD degrees in 2006 and 2011, respectively,
from ASU, FE, Engineering Physics Department, Cairo,
Egypt. His fields of research includes Semiconductor
physics, characterization, simulation and modeling of
nanoscale devices, semiconductor power devices, solar
cells, 3D detectors. Spin dependence transport in
Semiconducting nanowires.

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