Nirma University

Institute of Technologr
Semester End Examination (IR), December - 2Ol9
B. Tech. in Electronics and Communication Engineering, Semester-Vll
E.C714 High Performance VLSI Design

Roll no/ Supervisor's initial

Exam No: with date:
Time: 3 Hours Max Marks: lOO
Instructions: 1. Attempt all questions.
2. Figures to rlght indicate full marks.
3. Draw neat sketches wherever necessary.
4. Assume Necessary data if required.
SECTION I
Q.1 Answer the following. (161
co2 (a) Give classification of small geometry effects in MOS transistor and explain each (8)
LL effect with necessary detaiis.

c'o2 (b) State the benefits of device enhancement and hence explain each method (8)
LL briefly.

Q.2 Answer the following. (161

col (a) Identify which interconnect design criteria are associated with Figure 1 and (4)
L1 discuss the significance of each in detail.

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(a)
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Figure 1
OR
col (a) Identify Figure 2 given below and write a short note on it. (4)
L1
Short circuit N
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Mid-197o3 ro mid-leaos
#
ffi It
Drivq gatc Lpad (driveo) gate
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Figure 2

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co1 (b) rnterconnectnoisecoupringrromaswitchinf, ?#*1X::'fiIffi",]:i:?T1t; (4)
L3 Figure 3. What will be the amount of capacitive coupling noise produced
considering all possible cases?
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Figure 3
co1 (c) In which condition, on-chip inductance is important? Give the range of (8)
L3 interconnect length where interconnect exhibits inductive behavior.
Q.3 Answer the following. (18)
co1 (a) Why accurate signal propagation analysis is required? Calculate delay (9)
L3 associated with the lumped interconnect model.
co1 (b) Define the electrical size of interconnect and derive the expression of complex (9)
L1 propagation constant, characteristic impedance for distributed transmission
line model.
OR
co1 (b) Why the Elmore delay model is used in interconnect synthesis? Draw and (9)
L1 signify the response of interconnect in case of step and impulse excitation is
given at the input for the sarne.
SECTION II
Q.4 Answer the following. (161
c04 (a) Give complete classification of noise in electrical circuits causes of generation (8)
L3 of each in brief.
co4 (b) Explain briefly the following keywords with necessary details. (8)
L2 1.Glitch power consumption
2.Delay uncertainty
3.Static noise margin
4.Dynamic noise Margin
Q.s Answer the following. (161
co5 (a) The Tapered buffered structure proposed by Lin and Linholm is shown in (8)
L2 Figure 4 below. Show that the overall propagation delay of a tapered buffer is
given as tp = tpo (tog nM)F also derive expression of Tapering factor F (ratio of
widths of the consecutive inverter) and prove that in case of exponential
tapering the value of F6p1 is 2.72.
Wo mN-rWo

ffi l-**-,Co Tn,*-rco T"""

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Figure 4

Page 2 of 3
 EC7 1 4-High Performance VLSI Design
cos (b) State importance of global interconnect and explain the effect of Wire sizing, (4)
L2 Spacing and Shaping on the performance of global interconnect.
cos (c) What is the purpose of using shield insertion" and uGate sizrn{? (4)
LL
OR
co5 (c) Write short notes on "signal Rerouting and wire reordering". (4)
L1
Q.6 Answer the following. (18)
co3 (a) Describe Components and scaling trends of Power supply noise. (e)
L1
co3 (b) Draw and Explain the concept of tl:e low dropout voltage regulator (e)
L3
OR
co3 (b) Draw the neat circuit diagram of switch capacitor converter and derive (9)
L3 Difference in Enerry Eain before and after the switch is closed.

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