library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sr is
generic (
bits:integer:=8;
addrs:integer:=16
);
Port (
WR_EN : in STD_LOGIC;
CLK : in STD_LOGIC;
ADD_R : in integer range 0 to addrs-1;
D_in : in STD_LOGIC_vector(bits-1 downto 0);
D_out : out STD_LOGIC_vector(bits-1 downto 0));

end sr;
architecture Behavioral of sr is
type memory is array (0 to addrs-1) of STD_LOGIC_vector(bits-1 downto 0);
signal sr : memory;
signal addr: integer range 0 to addrs-1;
begin
process(WR_EN, CLK)
begin
if(CLK'event and CLK='1')then
if(WR_EN='1') then
sr(addr)<=D_in;
end if;
addr<=ADD_R
end if;
end process;
D_out<=memory(addr);

end Behavioral;