DESCRIPTION OF 8085A PINS

A15 – A8 : Address Bus 

The most significant 8 bits of the memory address Or the 8 Bit of I/O address

ADO – AD7  Multiplexed Address / Data Bus:

Lower 8 bits the memory address ( or I/O address) appears on the bus during the first cycle (T state) of
the machine cycle. It then become the data bus during the second and third cycle.

ALE :  Address Latch Enable:

It occurs during the first clock state of a machine cycle and enables the address to get latched into the
on chip latch of peripherals.

𝑅𝐷 :  Read Control

A low level on 𝑅𝐷 indicates the selected memory OR I/O device is to be read (not write) and that the bus
is available for data transfer.

𝑊𝑅:  Write Control:

A low level on 𝑊𝑅 indicate that data on the data bus is to be written into the selected memory OR I/O
location. Data is setup at the trailing edge of 𝑊𝑅.

SI, SO and IO/𝑴 : Machine Cycle Status : 

IO/𝑀 SI SO Status

0 0 1 Memory Write

0 1 0 Memory Read

1 0 1 I/O Write

1 1 0 I/O Read

0 1 1 Opcode Fetch

1 1 1 Interrupt Acknowledge

Bus Idle

SI and SO can be used as Advance Read / Write (R/W) Status.

IO/ 𝑴, SI and SO become valid at the beginning of a machine cycle and remain stable throughout
the cycle.
X1 & X 2  :

X1 & X2 are connected to a crystal, LC or RC network device the internal clock generator.

X1 can also be an external clock input from a logic gate. The input frequency is divided by 2 to give the
processor’s internal operating frequency.

Clk (Out) : 

Clock output for use as a system clock. The period of clock is twice the X 1 & X2 input period.

VCC : Power +5 V supply

VSS : Ground Reference Point

SOD :  Serial Output Data

SID :  Serial Input Data

Ready  : High (Normal Process)

Low (Wait: Status unchanged)

𝑹𝑬𝑺𝑬𝑻 𝑰𝑵 : To reset microprocessor

HOLD  : from some external block to gain control of System Bus.

HLDA  : Hold Acknowledgement