ECE467: Introduction to VLSI Design

Lecture-6

CMOS Combinational Logic and Static CMOS

Inverter

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 CMOS Logic
Defining Characteristics:
• These logic circuits are built using both NMOS and
VDD
PMOS devices
• Consist of a pull-down network and a pull-up network
• Normally pull-down network is made of NMOS
Pull-up
device and pull-up network is made of PMOS device network Iup

• The pull-down network connects the gate output to

GND (‘0’) and the pull-up network connects the Vin
Vout

output to Vdd (‘1’)

• That’s why these type of logic is called
complementary MOS logic Pull-down
network
Idown CL

Selection of Device:
• Pull-down network: NMOS
– NMOS is a very good pull-down device
• Pull-up network: PMOS
– PMOS is very good pull-up device

2
 CMOS Logic
Working Principle:
• The two networks are arranged such that one is ON and
the other is OFF for any input pattern VDD

• When pull-down network is ON for a particular input

pattern, the pull-up is OFF and the output gets connection
to GND. Pull-down network can bring down the out to Pull-up
network Iup
perfect ‘0’ since it is made of NMOS device.
• When pull-up network is ON for a particular input Vout
pattern, the pull-down is OFF and the output gets Vin

connection to Vdd. Pull-up network can raise the output to

perfect ‘1’ since it is made of PMOS device. Pull-down Idown CL
network
• At steady-state only one network is ON providing the
appropriate connection to the output. Therefore, there will
no direct path from Vdd to GND in steady-state condition.
• Ideally almost no current flows in the steady-state
condition resulting in almost zero power consumption
• That’s why CMOS logic has become most popular in
implementing digital integrated circuits
3
 CMOS Logic
Selection of CMOS for most IC application:
– Able to produce perfect logic ‘0’ and logic ‘1’
VDD
– Very high noise margin
– Almost zero static power consumption
Behavior of CMOS Logic Pull-up
Iup
– Dynamic or transient behavior: As long as I up ≠ I down
network

– Static or steady-state behavior: When I up = I down Vout

Vin

Pull-down Idown
network
CL

4
 Static CMOS Inverter
Definition:
• The inverter is the most fundamental logic gate that performs the Boolean
operation of inversion on a single input variable
Symbol and Logic Function:
Truth Table
A B
A B= A 0 1
1 0

Inverter From Electrical Point View:

• Both input and output variables are represented by node voltages, referenced to
ground potential
• Positive logic convention:
– Logic value of “1” or “high” is presented by VDD or supply level
– Logic value of “0” or “low” is represented by 0 or ground potential

5
 Static CMOS Inverter
Ideal Inverter:
• For any input between 0 to VDD/2, the output is equal to VDD (logic “1”)
• The output switches from VDD to 0 when the input is VDD/2 and for any voltage
above VDD/2, the output is equal to 0 (logic “0”)
• An input voltage 0< Vin < VDD/2 is interpreted by ideal inverter as logic “0”
• An input voltage VDD/2 < Vin < VDD is interpreted as logic “1”

Vin Vout

6
 Static CMOS Inverter
VDD VDD
The Static CMOS Inverter:
Rp

Vout Vout
CL CL
Rn

Vin = 0 Vin=VDD
Low-to-high High-to-low
Switch Models of CMOS inverter:
• A MOS transistor can be considered a switch that yields the above equivalent circuit
V <V
– Infinite off-resistance for: GS T
– Finite on-resistance (Rn,Rp) for: V GS > VT
• With Vin = Vdd : NMOS is ON and PMOS is OFF. The NMOS builds a direct path
between Vout and the ground node, while the PMOS acts like an open circuit. This
results in a steady-state value of 0 volt or logic low output.
• With Vin = 0 : PMOS is ON and NMOS is OFF. The PMOS transistor builds a direct
path between Vout and the Vdd node, while the NMOS transistor acts like an open
circuit. This situation results in a steady-state high output.
7
 Properties of Static CMOS inverter:
Perfect Logic Level and Full Voltage Swing:
• The high and low output voltage levels are equal to Vdd and GND respectively,
which results in full voltage swing or Vswing = Vdd
– Voltage swing: the difference of voltage level between logic “0” and logic “1”
is called voltage swing or logic swing
– Full voltage swing results in high noise margin
Ratioless Design:
• Static CMOS inverter is ratioless, which means the logic levels do not depend on
the relative sizes of the transistors.
– The transistors can be minimum sized in ratioless design
– Ratioed logic: In this type of design the logic levels depend on the relative size
of the transistors in pull-up and pull-down network
Zero Static Power Consumption:
• Since there is no direct path between the Vdd and GND at steady-state operating
conditions, the static power consumption is virtually zero for CMOS inverter due to
absence of any current flow.
– Only power consumption is during the transition, that is, dynamic power
– There is a very small static power components due to leakage

8
 Properties of Static CMOS inverter:
Low Output Impedance:
• Output impedance of a static CMOS inverter is low, since there always exists a low
resistive path between the output and either VDD or GND.
– Low output impedance makes CMOS inverter less sensitive to noise and
interferences
– Typical value of output impedance is in the kΩ range.
Very High Input Impedance:
• The input impedance is very high, since the gate is insulated from the channel and
draws no dc input current.
– Since the input node of the inverter is connected to the gates of the transistors, at
steady state input current is almost zero.
– Keeping input currents of the load gates small (corresponds to high input
impedance) and output current of the driving gate high (corresponds to low
output impedance) is important.
– A single inverter virtually can drive infinite number of gates, and still can be
functionally operational.
• But increasing fan-out degrades the propagation delay

9
 Properties of Static CMOS inverter:
• Fan-out: The fan-out denotes the number of load gates N that are connected to the
output of a driving gate.
– Generally increasing fan-out affects the logic output levels
– With higher fan-out the driving gate sees more capacitive load and suffers from
higher propagation delay
• Fan-in: The fan-in of a gate is the number of inputs to the gate from static
perspective
– Gates with large fan-in tend to be more complex, which results in poor static and
dynamic properties.

10
 Voltage Transfer Characteristics (VTC):
• The VTC describes the relation between Vout and V-in under DC condition

ƒ Here, VGSn = Vin and VSGp = Vdd - Vin

Vout
NMOS off ƒWhen Vin ≤ VTn the transistor Mn is OFF. The output
PMOS res is high with a value of Vout = Vdd. PMOS is linear. Any
input in this range labeled as “0” can be interpreted as a
2.5

NMOS s at
logic 0 input.
PMOS res
ƒ Increasing Vin beyond this range causes a downward
2

transition in VTC, since at this Vin NMOS is turned ON

NMOS sat while PMOS is still conducting. Here NMOS is saturated
1.5

PMOS sat and PMOS is linear.

ƒ Increasing Vin decreases VSGp and PMOS becomes
less efficient conductor and the output falls. When
1

NMOS res output and input voltages are equal both transistors are
PMOS sat NMOS res saturated. Beyond that point NMOS is linear.
0.5

PMOS off ƒ Mp goes into cut-off when Vin = Vdd - │VTp│. For
Vin greater than this value, Vout = 0 V, since only
0.5 1 1.5 2 2.5 V in NMOS is ON. This shows the range of input voltage that
act as logic 1 input values as indicated by the “1” on11the
VTC.
 Various Points on VTC

• Nominal high and low output voltages (VOH and VOL):

– The end points of VTC are VOH and VOL
• If Vin = 0 volt, Mn is OFF while Mp is ON. Since the PMOS is ON, it
connects the output to VDD and gives Vout = VDD. This defines the output
high voltage VOH:
– VOH = VDD …. highest output value is the value of power supply
• If Vin = VDD, Mn is ON while Mp is OFF. Since the NMOS is ON, it
connects the output to ground and gives Vout = 0. This defines the output
low voltage VOL
– VOL = 0 V…. lowest output value is the value of GND
• The logic swing:
• VL = VOH – VOL = VDD. Since this is equal to full value of the power
supply, this is called a full-rail output
12
 Various Points on VTC

• Input low and input high voltages (VIL and VIH):

– VIL is the maximum input voltage that can be considered an input low or logic 0
input.
– VIH is the minimum input voltage that can be considered as input high or logic 1
input.
– Point ‘a’ in the figure has a slope of -1, and defines input low voltage VIL. This is
used to define logic 0 input range as: 0 ≤ Vin ≤ VIL
– Point ‘b’ also has a slope of -1, and defines the input high voltage VIH. This is
used to define logic 1 input range as: VIH ≤ Vin ≤ Vdd
dV
– By definition VIH and VIL are the operational point where gain = out = −1
dVin

13
 Various Points on VTC

• Inverter Switching Threshold Voltage (VM):

– The inverter switching threshold voltage is defined as the point where Vin = Vout.
Its value can be obtained graphically from the intersection of the VTC with the
unity gain line given by Vin = Vout = VM
– It is the center point of the transition
– To calculate VM we set Vin = Vout = VM as shown in figure above. At this
condition both transistors are in saturation region of operation. Equating the drain
currents of the NMOS and PMOS transistors in saturation region gives IDn = IDp
• Symmetrical inverter:
– Inverter that has a VTC with equal “0” and “1” input voltage ranges. This can be
achieved by choosing VM = (1/2)VDD

14
 Derivation of VIL, VIH and VM

Mathematical expressions will be derived in class

* Please add those derivations after this slide to maintain continuity

15
 In Class Problem
• For the Static CMOS inverter find the following:
– Output high and low voltages (VOH and VOL)
– Inverter switching threshold voltage (VM)
– Condition for the inverter to be symmetrical
– Input high and low voltages (VIH and VIL)
– Logic swing and Transition width
– Noise margins (NMH and NML)
VDD = 5V

(W/L)p = 2, VTp = -0.7V

kp’ = 5.4x10-6 A/V2
IDp
Vout = VDSn
IDn

(W/L)n =1, VTn = 0.7V

Vin = VGSn CL
kn’ = 19.6x10-6 A/V2

16
 Various Points on VTC
"1"
VOH
NMH Noise margin high
VIH
Transition width (TW)
Undefined Region
NML VIL
VOL Noise margin low
"0"
Gate Output Gate Input
Noise Margins:
• For a gate to be robust and insensitive to noise, it is essential that the “0” and “1”
intervals be as large as possible.
• A measure of the sensitivity of a gate is given by noise margins NML (noise margin
low) and NMH (noise margin high), which quantasize the size of “0” and “1”
respectively. The noise margins represent the levels of noise that can be sustained
when gates are cascaded as illustrated in figure below
• NML = VIL - VOL
• NMH = VOH - VIH
Transition Width:
• The region between VIH and VIL is called undefined region or transition width (TW).
– Steady-state signals should avoid this region
– Therefore it is desirable to have TW = VIH – VIL as small as possible.
17
 Dynamic Behavior of Inverter

• Propagation Delay
• Transition Time:
– Rise Time
– Fall Time

18
 Propagation Delay and Transition Time
Propagation delay:
• The propagation delay defines how quickly a gate
responds to a change at its input. That is, the delay
experienced by a signal passing through the gate.
• Generally propagation delay is defined as the time
between 50% points of input and output transition.
• Propagation delay of a CMOS gate is determined by the
time it takes to charge and discharge the load capacitor CL
through its PUN and PDN.
• Since a gate displays different response times for rising
and falling input waveforms, two definitions of the
propagation delay are necessary. t pLH + t pHL
• The tpHL defines response time for high-to-low output tp =
transition and the tpLH defines the response time for low- 2
to-high output transition. The propagation delay is defined
as the average of the two
Rise and Fall time (tr and tf):
• These two times express how fast a signal transits
between different levels. Therefore, rise and fall times are
the slopes of signal waveforms during low-to-high and
high-to-low transitions respectively
– These are metrics that apply to the individual signal
waveforms rather than to the gate
– They are defined as the time between the 10% and
90% points of waveforms 19
 Propagation Delay

V DD V DD

tpLH = f(Rp .CL ) tpHL = f(Rn .CL )

Rp

V out V out
CL CL
Rn

V in = 0 V in = V DD
Low-to-high High-to-low

20
 Calculation of tpHL for a CMOS inverter
• Consider: at t = 0 input Vin switches from 0 to VDD.
• At t=0, VGS = VDD & Vout = VDS = VDD and NMOS is in saturation.
• When Vout = VDS = VDD – VTn, NMOS enters into linear region of operation
2
• k
Here, I 1 = I n = (V DD − VTn ) V
n 2
I 2 = I n = k n [(VDD − VTn )Vout − out
]
2 2
• The current, that is discharging the capacitor can be given by
dVout
I n (t ) = −C L
dt
⇒ −C L .dVout = I n (t ).dt
inegrating between 50% transitions of input and output
V DD / 2 t pHL
⇒ −C L ∫ dVout = ∫ I n (t ).dt
V DD 0
V I +I
⇒ C L DD ≈ I avn .t pHL , here I avn = 1 2 ....1st assumption
2 2
C V
⇒ t pHL = L DD
2.I avn
• 2nd assumption: Between VDD and VDD/2 it can be assumed that Iavn = I1
C L .VDD C L .VDD
t pHL = =
2. I 1 k n (VDD − VTn ) 2
CL
• 3rd assumption: Since VDD >> VTn we can further simplify: t pHL =
k nV DD 21
 Calculation of tpLH for a CMOS inverter
• Similarly it can be proved that
C .V
t pLH = L DD ......... 1 st approximat ion
2 . I avp
C L .V DD
= ....... 2 nd approximat ion
k p (V DD − V Tp ) 2

CL
= .......... ........ 3 rd approximat ion
k p .V DD t pLH +t pHL CL 1 1
The propagation delay is given by: t p = = ( + )
2 2.VDD k p kn
Underestimation of Propagation Delay:
– The average current approximation to estimate the area under the current curve
is an overestimation of actual current. Therefore, the expression gives a lower
value of propagation delay
– Each successive approximation uses an even higher current, resulting in even
lower propagation delay
– Therefore, the approximate expressions used for manual calculation always
underestimates the propagation delay
22
 Symmetrical Inverter
• Symmetrical Propagation delay: t pHL = t pLH
• To make t pHL = t pLH we have to make : k n = k p

⎛W ⎞ ⎛W ⎞
⇒ k n' ⎜ ⎟ = k 'p ⎜ ⎟
⎝ L ⎠n ⎝ L ⎠p

kn ' ( )
W
Lp
⇒
k 'p
=
( )
W
Ln
• Symmetrical inverter also has a VTC with equal input voltage ranges for
logic “0” and “1”, which means VM = (1/2)VDD. This condition is met when

kn = k p
• Therefore, the condition for symmetrical inverter is
kn = k p

23
 Fall Time Calculation for a CMOS inverter
• Consider that Vin changes from 0 to VDD at time t = 0. The initial condition at the
output is Vout(t=0) = VDD.
• As Vin switches from 0 to V-DD the NFET becomes ON with finite ON-resistance
Rn while PFET becomes OFF and acts as open switch.
• The capacitor CL is initially charged to VDD, and is allowed to discharge to 0V
through NMOS resistance Rn. The current leaving the capacitor is given by

dVout Vout
I n (t ) = −C L =
dt Rn
dVout dt
⇒ =−
Vout C L .R n

• By solving for time interval 0 to t (interval Vout(0) to Vout(t) we obtain

⎛V ⎞
Vout (t ) = VDD .e −t /τ n ..... here,τ n = Rn .C L ⇒ t = τ n . ln⎜⎜ DD ⎟⎟
⎝ Vout ⎠
• The fall time is traditionally defined as the time interval from V0 = 0.1VDD to V1 =
0.9VDD. Using this definition from the figure we can write
•
⎛ VDD ⎞ ⎛ VDD ⎞
t f = t y − tx =τ n.ln⎜⎜ ⎟⎟ −τ n.ln⎜⎜ ⎟⎟ = τ n.ln(9) = 2.2τ n
⎝ 0.1VDD ⎠ ⎝ 0.9VDD ⎠ 24
 Rise time calculation for a CMOS inverter
• Consider that Vin changes from VDD to 0 at time t = 0. Therefore, Vout(t=0) = 0.
• At t = 0 NFET becomes OFF and PFET becomes ON with finite ON-resistance Rp
• The capacitor CL is initially charged to 0, and is allowed to charge to VDD through
PFET resistance Rp. The current charging the capacitor is given by

dVout VDD − Vout

I n (t ) = C L =
dt Rp

• Again the rise time is the time interval between V1 = 0.9VDD and V0 = 0.1VDD
• Similarly it can be shown that rise time tf can be given by:
t r = 2.2τ p ....... where τ p = R p .C L
Minimum Signal Period: Tmin = tf + tr
1
Maximum obtainable signal frequency: f max =
t f + tr

25
 Power Consumption in CMOS Inverter
• Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Static Power due to Leakage

Leaking diodes and transistors

26
 Power Consumption
Vdd
in CMOS Inverter

Vin Vout

CL

• The gate is connected between the power supplies: VDD and GND. If the gate draws
a current IDD from the supply, it will give rise to a power dissipation of P = VDD.IDD
• Since the value of the VDD is constant for a gate, the value and the nature of the
power depends on the nature of the current flow. Normally the current can be
divided into two components: (i) Steady-state or DC or static current, and (ii)
Dynamic or transient current. Accordingly dissipated power can be divided into two
components: P = Pstat + Pdyn
• For ideal inverter it is assumed that Vin switches between logic levels
instantaneously with zero rise/fall time. Two transistors never remain ON
simultaneously.
• Practically all signal have finite rise/fall times or slopes. Consequently, both
transistors simultaneously remain ON for a brief period during switching, when a
short circuit or direct path exists between VDD and GND. This introduces another
component of power consumption Pdp or Psc. Therefore, the total power
27
consumption will be: P = Pstat + Pdp + Pdyn
 Static or DC power dissipation
• Ideally at steady-state when there is no switching activity one of PMOS and NMOS
devices of inverter or PUN and PDN of any CMOS gates is OFF; and no static
current flows between supply lines.
• But practically leakage currents are always there, since the devices are not
completely OFF or open.
• This leakages come from two major sources:
– Subthreshold conduction - Reverse biased PN junction current
Source Gate Drain B Al A
SiO 2
Polysilicon
SiO 2
p

n
n+ n+
bulk Si
p
Cross-section of a pn junction in an IC process

• Therefore, there will be a static power consumption given by Pstat = Vdd.Ileak

• This contribution is small and usually ignored. However, the junction leakage
currents are functions of the temperature, and the currents increase exponentially
with temperature. Therefore, keeping the operating temperature low is an important
design goal
• In very high performance design this power component can not be ignored, since
28
margin of tolerance has become very low
 Static Power Due to Leakage
Vout Mn off
Mp on
Mp ON
Mn ON

Mp off
Mn on

Vin VM Vin

Vdd
Vdd - VT

Idd

VT

Idd t

Ipeak

Leakage current Ileak gives rise to a DC

power consumption at steady-state condition

Ileak
29
tsc t
 Short Circuit Power
Vout Mn off
Mp on
Mp ON
Mn ON • When Vin is being switched, a short circuit current
between VDD and GND for a short period of time when
both transistors are conducting
Mp off • The short circuit current reaches a peak value Ipeak at VM
Mn on when both transistors are in saturation.
Vin VM Vin

Vdd
Vdd - VT

Idd

VT

Idd t

Ipeak

Ileak
30
tsc t
 Vdd
Short Circuit Power
Vdd - VT
Idd
V
T
Idd t
Ipeak

Ileak

t
tsc
• Under reasonable approximation we can assume the resulting short circuit current as
triangle, and we can also assume a symmetric inverter.
• The total energy consumed due to short circuit current per switching event (cycle T) can
be given by
Esc = (VDD.Ipeak.tsc/2).2 = VDD.Ipeak.tsc
• The average power can be given by
Psc = Esc/T = Esc.f = VDD.Ipeak.tsc.f = VDD.Qsc.f = Csc.VDD2.f
Here Csc = short circuit capacitance = Qsc/VDD, where Qsc = Ipeak.tsc
• Therefore Psc depends on the switching activity
• Ipeak is determined by the saturation current and the ratio between input and output sloes
31
 Dynamic Power
V DD Energy taken from supply VDD can be given by
∞ ∞ VDD
dV
EVDD = ∫ iDD (t ).VDD .dt = VDD ∫ C L out .dt = C L .VDD ∫ dV out = C L .VDD
2

dt
ID(t) 0 0 0

V in = 0 Energy stored on the capacitor

∞ ∞ V 2
dVout DD
C L .VDD
V out ECL = ∫ iD (t ).Vout (t ).dt = ∫ C L Vout = C L ∫ Vout (t ) =
0 0
dt 0
2

CL Energy consumed by the PMOS transistor:

2
C L .VDD
E PMOS = EVDD − ECL =
2

Energy stored in load capacitor CL is dissipated by NMOS transistor during

high-to-low transition 2
C L .VDD
Energy dissipated by NMOS: E NMOS =
2
Total Energy dissipated by the inverter for low-to-high and high-to-low
transition is Edyn = CL .VDD
2

Dynamic Power is given by Pdyn = Edyn / T = C L .VDD2

f
32
 Total Power

Total power is given by

P = Pstat + Psc + Pdyn

= I leak .VDD + C V 2
sc DD f + C L .V
2
DD f

33