ECE467: Introduction to VLSI Design

Lecture-9: Dynamic Combinational Logic Circuits

This lecture includes:
Definition and Operating Principle of Dynamic Logic
Precharge and Evaluation Phases
Pros. & Cons. Of Dynamic Circuits
Speed and Power Consumption in Dynamic Logic
Floating Node Problem
Signal Integrity Issues in Dynamic Circuits
Cascading Dynamic Gates
Domino Logic
NP Logic

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 Dynamic Logic Gates
Concept and Characteristic Features:
• Dynamic gate uses charge storage properties of MOSFET to implement
logic operations. Logic values are maintained as a voltage across a load
capacitor
• The integrity of the logic value depends on how long the capacitor can hold
the stored value within a certain range
• The result of calculation is thus valid for a short period of time
• As opposed to static circuit family there is no steady state connection to
VDD or GND to maintain logic 1 or 0
• At some time during their operation dynamic gates can have floating output
nodes
• Dynamic gate uses clocking, which provides a synchronized data flow
which makes it suitable for designing sequential networks
• The operation of this gate is divided into two major phases – precharge and
evaluation – with the mode of operation determined by the clock signal

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 CMOS Dynamic Logic Circuits
Circuit Construction:
• The basic construction of an n-type dynamic
gate is as in the figure
Clk Mp • The PDN is constructed exactly as in
Out complementary CMOS.
• The design of dynamic gate is similar to
In1 CL
pseudo NMOS logic gate, while avoiding the
In2 PDN static power consumption of pseudo NMOS
In3 gate.
• Similarly a p-type dynamic gate can also be
Clk Me
constructed with PUN constructed as in
complementary CMOS

Operation of a Dynamic Circuit:

• Two phases of operation – precharge and evaluation
• The circuit operation is based on first precharging the output node capacitance and
subsequently, evaluating the output level according to the applied inputs.
• Both of the operations are scheduled by a single clock signal, which drives one
NMOS and one PMOS transistor in each dynamic stage
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 CMOS Dynamic Logic Circuits
Example 1: ((AB)+C)

Clk off
Mp
on 1
Out
Two phase operation
A Precharge (Clk = 0)
C Evaluate (Clk = 1)
B

off
Clk Me
on
Conditions on Output:
• Once the output of a dynamic gate is discharged, it cannot be charged again until
the next precharge operation.
• Inputs to the gate can make at most one transition during evaluation.
• Output can be in the high impedance state (floating) during and after evaluation
(PDN off), state is stored on CL
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 CMOS Dynamic Logic Circuits
Example 2: ((A1A2A3)+(B1B2))
Precharge:
• In this phase the clock signal is low,
Ψ
and the PMOS precharge transistor Mp
is conducting, while transistor Me is
off.
• The parasitic output capacitor is
charged to logic high level VDD
through conducting PMOS transistor.
• The input voltages are also applied
during this phase, but they have no
influence yet upon the output level
since Me is turned off.
Evaluation:
• While clock is high, the precharge Mp turns off and the evaluation Me turns on
• The output node may remain at logic high or discharge to logic low level,
depending on the combination of the applied inputs. That is, the logic gate the
evaluates the inputs and produces expected output at this phase.
• If the input signals do not turn on the PDN network, then the output remains at its
precharged value of VDD; again if the input signals creates a conducting path
through PDN the output capacitance get discharged toward VOL = 0 volt. The final
discharged output level depends on the time span of the evaluation phase 5
 Pros. & Cons. Of Dynamic Logic
• Logic function is implemented by the PDN only
– number of transistors for fan-in N in dynamic CMOS gate is N + 2
– fan-in of N requires 2N (N n-type + N p-type) devices for static
complementary CMOS
• Less area due to lower transistor count
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not affect the logic levels
• Faster switching speeds
• Possibility of having floating output node makes it very vulnerable to noise
• Overall power dissipation usually higher than static CMOS
• PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and
VIL equal to VTn
• Low noise margin (NML)
• Highly asymmetrical design
• Needs a precharge/evaluate clock

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 Floating Node Problem in Dynamic Gate
• Consider the following circuit:
– When the clock Ψ=0, the output is precharged to VDD
– When the clock Ψ=1, the precharge transistor Mp is OFF and the evaluation
transistor Mn is ON.
– The output node will be connected to ground if the input combination turns
ON the PDN network, otherwise the output will be floating
– For example, an input combination A1=B1=B2=0 & A2=A3=1 the PDN is
OFF, and the output node is disconnected from VDD and ground. That is, the
node is in high impedance state or floating state.
– Due to this floating node situation dynamic nodes are very vulnerable to noise,
since there is no way to restore the logic level in case of any noise disturbance.

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 Speed of Dynamic Gate:
• The switching speed of the dynamic gate is faster due to
following two reasons:
– Reduced load capacitance due to lower input
capacitance (Cin)
– Reduced load capacitance due to smaller output
loading (Cout)
– No Isc, so all the current provided by PDN goes into Clk Mp
discharging CL
– Zero tpLH: After the precharge phase the output is Out
high. Therefore, for a low input signal, no additional In1 CL
switching is required. As a result tpLH is 0!
In2 PDN
• Higher tpHL: The high-to-low transition requires the
discharging of load capacitance through PDN and the In3
NMOS evaluation transistor, which presents extra series Me
resistance. Therefore, tpHL is proportional to CL and Clk
current drive capabilities of PDN and the evaluation
transistor, which slows down the gate to some degree.
Omitting this transistor is possible logically, but it will
introduce static power consumption.
• Precharge time: The precharge time is the time it takes
to charge CL through PMOS device. During this time the
logic in the gate can not be utilized. The designers must
be aware of this dead zone. Often designers try to design
the system in such a way that the precharge time
overlaps with other system function 8
 Power dissipation in Dynamic Gate:
Positive Aspect from Power Perspective:
• It would appear that the dynamic logic has significant advantages from power
perspective due to following prospects of dynamic logic:
– There is no static power consumption. It only consumes dynamic power.
– No short circuit dissipation.
– Lower load capacitance due to reduced transistor count.
– Decreased fan-out load seen by the driver gate.
– The dynamic logic has only one transition per clock cycle
– No glitching
Overall power dissipation usually higher than static CMOS
• While the above positive observations are true, there are other power factors that
offset all the positive factors:
– Power consumed by the clock lines is significant, which is absent in static
logic
– Due to the presence of the clock there will be one guaranteed transition in
every clock cycle, which will cause great amount dynamic power consumption
– Dynamic logic in general shows higher switching activities due to periodic
precharge and discharge operation
– Number of transistors is greater than the minimal set required for
implementing the logic
– Leakages contribute significant power consumption
– Short circuit power may exist in presence of the leakage combating devices.
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 Signal Integrity Issues in Dynamic Circuits
Charge leakage:
• The operation of the dynamic circuits relies on the dynamic storage of output value
on a capacitor. If PDN is off, the output should remain at the precharged value
during the evaluation phase. However this stored charge gradually leaks away due
to leakage.
• The are two major sources of leakage in dynamic gates
– Reverse biased diode current
– Subthreshold current of the MOSFET devices
– Dominant component is subthreshold current
• Due to this leakage sources the stored charge in dynamic logic need to be refreshed
at a certain interval. Therefore, dynamic gates require a minimal clock rate. It is
important to note that leakage through PMOS precharge device counteracts the
leakage through PDN
CLK
Clk Mp
Out

A CL
VOut Evaluate
Clk Me
Precharge
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Leakage sources
 Signal Integrity Issues in Dynamic Circuits
Solution to Charge Leakage:
ƒ Since leakage is caused due to the high-impedance state of output node during
evaluation, when PDN is turned off, this problem can be counterbalanced by
reducing the output impedance on the output node. According to this principle
often dynamic nodes are protected by a keeper or bleeder transistor, whose
function is to restore any deviation of output voltage due to leakage.

ƒ But the design of the keeper transistor is ratioed, which causes extra static power
consumption. To ensure less area penalty the keeper transistor is kept as small as
possible, which makes it very slow. Often the keeper is implemented in a feedback
configuration (shown in the figure on the right) to eliminate the static power
dissipation. 11
 Signal Integrity Issues in Dynamic Circuits
Charge Sharing:
ƒ Charge redistribution among internal nodes is another serious concern
ƒ Consider the circuit below. With low clock the output is precharged to VDD.
Assume that all the capacitors Ca and Cb were discharged. If the input B = 0 , but
input A = 1, the dynamic gate should produce a dynamic high output equal to
VDD during evaluation phase. But by applying A = 1 the corresponding transistor
Ma is turned on , and the stored charge on CL gets redistributed between CL and
Ca. This causes a drop in output voltage, which can not be recovered due to the
dynamic nature of the output node.

Clk Mp Clk Mp Mkp Clk

Out
Out
A CL A

B=0 CA Charge stored originally on CL B Precharge internal nodes using a

is redistributed over CL and CA clock-driven transistor (at the
Clk Me leading to reduced robustness Mecost of increased area and power)
CB Clk

Preventing charge sharing: The most effective way of preventing the charge sharing
is to precharge all the critical internal nodes along with the output node as shown
in figure on the right. The technique is effective, but at the cost of increased area
and capacitance.
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 Signal Integrity Issues in Dynamic Circuits
Capacitive Coupling:
ƒ The high impedance state of output node makes it very sensitive to crosstalk.
ƒ Switching activity on a neighboring wire may destroy the state of the floating
node through capacitive coupling
ƒ Backgate coupling or output-to-input coupling is another form of capacitive
coupling.
ƒ Consider a dynamic gate driving a static gate
ƒ A low-to-high transition in In may cause the output of static gate Out2 to go low
ƒ This output transition may capacitively couple with the other input of the static
gate, which is connected to the output (Out1) of the dynamic gate through the gate-
source and gate-drain capacitance of transistor M4.
ƒ This coupling may cause significant drop in dynamic output if it is in floating state

Clk Mp Out1 =1
Out2 =0
A=0 M4 In
CL1 CL2

B=0

Clk Me
Dynamic NAND Static NAND
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 Signal Integrity Issues in Dynamic Circuits
Clock Feedthrough:
ƒ It is a special case of capacitive coupling between clock input and the dynamic
output
ƒ This coupling between Out and Clk input of the precharge device is due to the
gate to drain capacitance of the precharge device
ƒ The fast rising (and falling edges) of the clock couple to Out, and causes the
voltage of Out to rise above VDD.
ƒ The danger of clock feedthrough is that it may cause the normally reverse-
biased junction diodes of the precharge transistor to become forward biased.
This may destroy logic information on a dynamic node.
Clock feedthrough
2.5
Clk Mp
Out
1.5
In1
Voltage

CL
In &
In2 0.5 Clk
Out
Clk Me -0.5
0 0.5
Time, ns 1
Clock feedthrough14
 Cascading Dynamic Gates
• Straightforward cascading of dynamic gates to create multi-level logic
structure is not possible
– During precharge phase (Clk=0) both Out1 and Out2 are precharged to VDD.
– During the evaluation phase (Clk=1), with a 0-to-1 transition at In, the output
Out1 should make a 1-to-0 transition and the output Out2 should remain at VDD
or logic 1
– But Out1 takes a finite time to be discharged, as long as Out1>VTn2, a conducting
path exists between Out2 and GND. Consequently Out2 is discharged to a
intermediate voltage level, which can not be recovered.

V
Clk Clk Clk
Mp Mp
Out2
Out1 In
In VTn
Out1
Clk Me Clk Me ΔV
Out2
t
• The problem of cascading can be resolved by turning off all transistors in pull-down
network after precharge. Correct operation can be guaranteed as long as the inputs
can only make a single 0-to-1 transition during evaluation period
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 Domino Logic
Concept:
ƒ A domino logic circuit consists of an n-type dynamic gate followed by a static
inverter.
ƒ During precharge the output of the dynamic gate is precharged to VDD, and
correspondingly the output of the domino gate is set to 0 by the inverter
ƒ During evaluation, the dynamic gate conditionally discharges, and the output of
the inverter makes a conditional transition 0-to-1, otherwise the inverter output
remains at 0. This ensures that during evaluation only one 0-to-1 transition is
possible at the input of the domino gate driven by the another domino gate

Mp Mp Mkp
Clk Clk
1→1 Out1 Out2
1→0 0→0
In1 0→1
In2 PDN In4 PDN
In3 In5
Me Me
Clk Clk

Advantage of having the inverter after the dynamic gate

ƒ The fan-out of the gate is driven by a static inverter with low output impedance
and high noise immunity
ƒ The inverter acts as buffer and reduces the capacitances of dynamic output node
ƒ The inverter can be used to drive a keeper transistor to restore logic level at
dynamic node 16
 Why Domino?
• During precharge all inputs are set to 0
• During evaluation the output of first domino gate is either stays 0 or makes a transition
to 1, affecting the second gate. The second gate affects the third, and so on.
• For specific input combination at other inputs, this effect may ripple through the whole
chain one after another, similar to a line of falling domino. That’s why this gate is called
domino gate

Clk

Ini PDN Ini PDN Ini PDN Ini PDN Like falling dominos!
Inj Inj Inj Inj
Clk

Properties of Domino Gate:

• Only noninverting logic can be implemented
• Very high speed can be achieved
• only rising edge delay exists, while tpHL equals zero
• The inverter can be sized to match fan-out. Fan-out is already much smaller: 17
• only a single gate capacitance has to be accounted for per fan-out gate
 np-CMOS

Clk Mp Clk Me
1→1
Out1
1→0
In1 In4 PUN
In2 PDN In5
0→0
In3 0→1
Out2
(to PDN)
Clk Me Clk Mp

Only 0 → 1 transitions allowed at inputs of PDN

Only 1 → 0 transitions allowed at inputs of PUN
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