VLSI Design (19EC401)

Unit-5
CMOS SUBSYSTEM DESIGN

Dr. M.Sarada
Professor
ECE

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 Course Outcomes
• Students will be able to
– CO1: analyze the operation and Electrical Behavior of
MOS transistors.(Unit-1)
– CO2: understand the fabrication process of different MOS
technologies. (Unit-2)
– CO3: design VLSI circuits and Layouts of simple MOS
circuit using Lambda based design rules. (unit-3)
– CO4: Analyze the circuit concepts of MOS circuits along
with scaling .( unit-4)
– CO5: Develop subsystems (digital circuits) using
various logic methods. (unit-5)
Unit-5 :CMOS SUBSYSTEM DESIGN
 Syllabus:
Logic Design: Pass Transistor, Transmission Gate, Alternate forms of CMOS –
pseudo nmos, dynamic,clocked cmos, domino cmos and DCVSL logics
DESIGN CMOS SUBSYSTEM DESIGN:Combinational circuit design - Adders,
Multipliers, Parity generators, Comparators, Zero and one detectors,
sequential design – design of latches and flipflops.
 Objectives:
– To learn alternate logic gates
– To design arithmetic circuits (like adder, multiplier etc) using CMOS
logic

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Alternate gate circuits

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 Contents
• Recap of
– Switch logic ,CMOS logic, nMOS Logic, BiCMOS
Logic
• Alternative CMOS logics
– Pseudo NMOS Logic
• Block Diagram
– Clocked CMOS Logic
• Example circuits
– Dynamic logic
• Advantages & Disadvantages
– Domino Logic
– DCVSL Logic

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Switch Logic

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CMOS Transistors Viewed as switches-A
CMOS Inverter

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CMOS Logic: Two input NAND Gate

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CMOS Logic: Two input NOR Gate

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Gate Circuits: Inverter

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Gate Circuits: NAND Gate

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Gate Circuits: NOR Gate

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Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 PDN
…

NMOS only
InN

PUN and PDN are dual logic networks

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 Alternative CMOS Logic Circuits
• Pseudo NMOS Logic
• Clocked CMOS(C2MOS)
• Dynamic CMOS
• Domino CMOS etc
• n-p CMOS Logic
• DCVSL Logic

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Pseudo NMOS Logic

Block Diagram

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 Examples
• Draw Pseudo nMOS logic
– Inverter
– NAND gate
– NOR Gate
– Y= (AB+CD)’

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Pseudo NMOS Logic Inverter

Pseudo nMOS Inverter

Block Diagram

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 Pseudo NMOS Logic:
Pseudo NMOS logic Gates

Pseudo nMOS Inverter

Why it is called as Pseudo nMOS? 18

 Pseudo NMOS Logic
• Transistor is QN driven by input voltage whereas gate of
transistor QN is grounded. Transistor QN acts as driver and QP
act as load, hence the name Pseudo NMOS. The number of
transistors required in Pseudo NMOS is less than complementary
CMOS.
• The advantage of Pseudo NMOS over CMOS is, each input must
be connected to the gate of only one transistor or alternatively
only one transistor (NMOS) will be needed for each gate input.
• A common application of Pseudo NMOS is in design of address
decoders for memory chips and in ROMs.

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 Pseudo NMOS Logic
• Advantages:
– Less area when compared to CMOS logic
– Zpu/Zpd = 3/1 compared to nMOS device
– More ON resistance compared to nMOS device
– Less static power dissipation compared to nMOS device
– For ‘n’ i/p circuit, (n+1) transistors are required.
• Disadvantages:
– Delay Increased when compared to nMOS logic
– Dealy decreased when compared to CMOS logic
– More Static power dissipation when compared to
CMOS logic
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Clocked CMOS Logic (C MOS)
2

Block Diagram

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 Example
• Draw
– Inverter
– NAND gate
– NOR Gate
– Y’= (AB+C(D+E))

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 Clocked CMOS Logic (C MOS)
2

CLKb

CLK

Inverter 2 input NOR Gate

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Y’= (AB+C(D+E))

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 Clocked CMOS Logic (C MOS) 2

• Advantages:
– Control Signal ( Clock) is applied
– The logic is evaluated only during period of the
Clock.
• Disadvantages:
– Delay Increased because extra transistors are
used.
– Area is increased. For ‘n’ i/p circuit, (2n+2)
transistors are required.
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 Dynamic CMOS Logic
Block Diagram

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Dynamic CMOS Logic

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 Example
• Draw
– Inverter
– NAND gate
– NOR Gate
– Y’= A.(B+C)

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Dynamic CMOS Inverter

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 Dynamic CMOS Logic
3 input NAND Gate 2 input NOR Gate

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Y’= A.(B+C)

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 Dynamic CMOS Logic
• Dynamic CMOS Logic circuits require a clock to precharge the
output node and then to pull down the logic tree (assuming the
logic inputs provide a path for current to flow)
– Precharge Phase: clock is low, turning ON the PMoS precharge
transistor; NMoS pull-down transistor is off. Output
capacitance CN charges to Vdd.
– Evaluation Phase: clock goes high turning ON the NMOS pull
down transistor and turning OFF the PMOS precharge transistor.
The output capacitance CN discharges to ground depending on
logic inputs.
– No dc current flows during either the precharge or the evaluate
phase.
– Power is dynamic and is given by P = CN Vdd2 f  where CN
represents an equivalent total capacitance on the output, f =
clock frequency,  =logic repetition rate 32
 Dynamic CMOS Logic
• Advantages:
– Area is reduced than Clocked CMOS. For ‘n’ i/p circuit,
(n+2) transistors are required.
– n+2 transistors for n-input function – Better than 2n
transistors for complementary static CMOS
– No static power dissipation
– Less power Dissipation
– Large Noise margin.

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 Dynamic CMOS Logic

• Disadvantages:
– Careful design, clock signal Φ needed
– Charge sharing may be a problem unless the inputs are
constrained not to change during the ON period of the clock.
– Single phase dynamic logic structures can not be cascaded
since, owing to circuit delays, an incorrect input to the next
stage may be present when evaluation begins, so that its output
is inadvertently discharged and the wrong output results.
– Remedy: One remedy is to employ a four phase clock in which
the actual signals used are derived clocks, Φ12, Φ23, Φ34 and
Φ41.
– Domino logic 34
Disadvantage of Dynamic Logic:
Charge Sharing Problem

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Disadvantage of Dynamic Logic:
Charge Sharing Problem

CL VDD = (CL + Ca) Vout

Vout = [CL / (CL + Ca)] VDD

Vout < VDD

Vout
b a L

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Disadvantage of Dynamic Logic:
Cascading Problem

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Cascading Problem

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 Cascading Problem

High

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Remedy : Domino CMOS Logic

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Four phase clocking

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Domino CMOS Logic

Block Diagram
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Example

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Domino CMOS Logic

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 Domino CMOS Logic
• Remarks:
– Such logic structures can have smaller areas than
a conventional CMOS logic
– Parasitic capacitances are smaller so that higher
operating speeds are possible
– Only non- inverting structures are possible
because of the presence of the inverting buffer
– Charge distribution may be a problem and must
be considered.
– Operation is free of glitches since each gate can
make only ‘1’ to ‘0’ transition 45
Charge Sharing Problem

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Glitch Error
Vout

IN

Operation is free of
glitches since each gate
can make only ‘1’ to ‘0’
transition
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n-p CMOS Logic

Block Diagram 48
49
 n-p CMOS Logic
• It is also called as NORA logic
• NORA- No Race
• Modified version of Domino CMOS logic
• Advantages:
– The static CMOS inverter is not required in this
logic, which saves the chip area
– NORA logic circuits can be connected in cascaded
with alternative clock and Clock bar.
DisAdvantages:
Low Noise margin because of floating output.
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NORA

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No Race

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 DCVSL CMOS Logic
DCVSL: Differential Cascode Voltage switch logic

Block Diagram
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 DCVSL CMOS Logic

OR/NOR Gate AND/NAND Gate

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 Differential Cascode Voltage
Switch Logic (DCVSL)
• Advantages
• Compute both true and complementary outputs
using a pair of complementary NMOS pull-down
network
• The PMOS transistors are driven by the output of
the complementary network
• Have no static current so No static power consumption
• Fast response
• Disadvantage
• More Transistors are required

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 Power dissipation in CMOS
•  There are three types of power dissipation in CMOS
1. Dynamic power is dissipated only when switching
2. Leakage current is permanent and results in a continuous loss
3. Short circuit

Ptotal = Pswitching + Pshort-circuit + PLeakage

Where,
Pswitching = CLoad  * (VDD ^2)  * f
Pshort-circuit = tsc * VDD * Isc 
PLeakage = VDD * Ileakage

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 Question-1
1.For a psuedo nMOS logic, the pull up device
is__________
a)Single, normally on load
b)Multiple loads
c)Normally OFF Loads
d)Depletion Mode NMOSFET

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 Question-2
2.For an n-input dynamic logic the number of
gates for full functionality is given
as__________
a)n
b)n+2
c)n+4
d)2n

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 Question-3
3. The static power dissipation of an ideal N-gate
dynamic logic is___________
a) 1 Watt
b) 0 Watt
c) N Watt
d) 2N Watt

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 Question-4
4. For a pseudo NMOS logic working such that
pull up PMOS is connected supply voltage of
VDD and the pull down network is connected
to ground. In such a scenario, the value of the
nominal pull down voltage is_________
a) VDD
b) Zero
c) Just larger than zero volt
d) cannot be predicted with the information
provided 60
 Question-5
In a DCVSL style of sequential design, two pull-
down networks should be
a) Matched
b)Complementary
c)Mutually Exclusive
d) Supplementary

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 Question-5

AND gate (B) OR gate (C) XOR gate (D) NAND gate

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 Question-6
Which statement is not related to Pseudo-nMOS
logic?
(A) N+1 transistors are needed for an N input
gate
(B) Low input gate-load capacitance
(C) Non-zero static power dissipation
(D) A pseudo-NMOS logic gate having a “0”
output has no static (DC) power dissipation.
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 Question-7
Which statement of dynamic CMOS logic is true?
(A) To eliminate the static power dissipation of
pseudo-NMOS logic.
(B) Area is reduced than Clocked CMOS.

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 Question-8
Find the name of the circuit shown in below?
(A) Dynamic CMOS (B) Domino CMOS (C)
C2MOS (D) Pseudo NMOS

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 Question-9
• Find the output voltage when C1=C2=0.5C?

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Pass Transistor
 Transmission Gate Symbols

C
C

A B A B

C
C
Arithmetic Circuits
Adders
Half Adder
 Static CMOS Full Adder
Co = AB + BCi + ACi S = A  B  Ci
= (A + B)Ci + AB = ABCi + C’o (A+B+Ci )
 Single bit subtraction
Half Subtractor Full Subtractor
 CMOS Full Subtractor

Home work
 Ripple carry adder
• Ripple-carry adder: n-bit adder built from full adders.
• Delay of ripple-carry adder goes through all carry bits.
 Ripple carry adder
Co = (A + B)Ci + AB
S = ABCi + C’o (A+B+Ci )
4 bit Subtractor
4 bit Subtractor: CMOS
Implementation

or

CMOS Versions
4 bit Adder/Subtractor
4 bit Adder/Subtractor: CMOS
Implementation
 Carry Lookahead Ci+1 = Gi + Pi.Ci

• Given Stage i from a Full

Adder, we know that there Gi = Ai.Bi
will be a carry generated
when Ai = Bi = "1", whether or
Pi= (Ai Å Bi)
not there is a carry-in.
• Alternately, there will b a
carry propagated if the
“half-sum” is
"1" and a carry-in, Ci occurs.
• These two signal conditions
are called generate, denoted
as Gi, and propagate, denoted
as Pi respectively and are

identified
Chapter 5 84 in the circuit:
 4-bit Carry-Lookahead Adder
c4 = g3 + g2 p3 + g1 p2p3 + g0p1p2p3 + c0p0p1p2p3

c3 = g2 + g1 p2 + g0 p1p2 + c0p0p1p2

c2 = g1 + g0 p1 + c0p0p1

c1 = g0 + c0 p0

s0 = x0  y0  c0 = p0  c0 s1 = p1  c1
s2 = p2  c2 s3 = p3  c3
4-bit Carry Network with Full Lookahead
4-bit Carry-Look Ahead Adder
 CMOS Implementation
• AND Gate: 2 i/p , 3 i/p and 4 i/p
• Ex-OR Gate: 2 i/p
• OR Gate: 2 i/p ,3 i/p and 4 i/p
k-bit Carry-Select Adder
Carry-Skip Adders/carry bypass Adder
 Simple Carry-Skip Adders
c16 4-bit block c12 4-bit block c8 4-bit block c4 c0
3 2 1 0

Ripple-carry stages
(a) Ripple-carry adder
p[12,15] p[8,11] p[4,7] p[0,3]

c16 4-bit block c12 4-bit block c8 4-bit block c4

3 2 1 0
c0

0 0 0 0
1 1 1 1

(b) Simple carry-skip adder

One-way street

Freeway

Street/freeway analogy for carry-skip adder.

Carry-Save Adder

Co S Co S Co S
Co
Array Multiplier: Multiplication
CMOS Circuit:
AND Gate: 2 i/p
FA: 28 Tr
4 bit Braun Multiplier

CMOS Circuit:
AND Gate: 2 i/p
FA: 28 Tr
Parity Generator
Static 2i/p and 4 i/p XOR Gates
Magnitude Comparator
1 BIT COMPARATOR
2-BIT COMPARATOR
4-BIT COMPARATOR
Equality Comparator
Zero Detector
One Detector: Tree Structure
One Detector: Ripple Structure
Latches : SR Latch
Clocked SR latch
D Latch
Clocked JK latch
 Flip - Flops

Use latches to create flip-flops that can respond (update) only

on specific times (instead of any time).

Types Of Flip flops

• Master-Slave Flipflop
• Edge triggered flip flops
– S-R Flipflop
– D-Flipflop
– J-K Flip flop
– T Flip flop
Master-Slave Flip-FloP
configuration
Master-Slave D Flip-FloP
D Flipflop
T Flipflop
JK Flipflop
SR Flipflop