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CMOS NAND Gate Overview and Benefits

CMOS NAND and NOR gates use 2n transistors for an n-input gate. CMOS NAND gates are preferred over NOR gates due to the weaker drive of PMOS transistors. The number of inputs per gate is limited, with 8-inputs as an example. CMOS gates have digital-level analysis but also require analog analysis to ensure circuits operate within specifications like voltage, temperature, loading, and timing. Output voltage can drop under load and exceed noise margins. Fanout and input loading specifications must be followed.

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109 views22 pages

CMOS NAND Gate Overview and Benefits

CMOS NAND and NOR gates use 2n transistors for an n-input gate. CMOS NAND gates are preferred over NOR gates due to the weaker drive of PMOS transistors. The number of inputs per gate is limited, with 8-inputs as an example. CMOS gates have digital-level analysis but also require analog analysis to ensure circuits operate within specifications like voltage, temperature, loading, and timing. Output voltage can drop under load and exceed noise margins. Fanout and input loading specifications must be followed.

Uploaded by

Yunus Torun
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd

CMOS NAND Gates

• Use 2n transistors for n-input gate

1
• CMOS NAND -- switch model

2
• CMOS NAND -- more inputs (3)

3
• Inherent inversion.
• Non-inverting buffer:

4
• 2-input AND gate:

5
CMOS NOR Gates
• Like NAND -- 2n transistors for n-input gate

6
NAND vs. NOR
• For a given silicon area, PMOS transistors are
“weaker” than NMOS transistors.
NAND NOR

• Result: NAND gates are preferred in CMOS.


7
Limited # of inputs in one gate
• 8-input CMOS NAND

8
Fancy stuff

• CMOS AND-OR-
INVERT gate

9
CMOS Electrical Characteristics
• Digital analysis works only if circuits are
operated in spec:
– Power supply voltage
– Temperature
– Input-signal quality
– Output loading
• Must do some “analog” analysis to prove that
circuits are operated in spec.
– Fanout specs
– Timing analysis (setup and hold times)

10
Output-voltage drops
• Resistance of “off” transistor is > 1 Megohm,
but resistance of “on” transistor is nonzero,
– Voltage drops across “on” transistor, V = IR
• For “CMOS” loads, current and voltage drop
are negligible.
• For TTL inputs, LEDs, terminations, or other
resistive loads, current and voltage drop are
significant and must be calculated.

11
Limitation on DC load
• If too much load, output voltage will go outside
of valid logic-voltage range.

• VOHmin, VIHmin
• VOLmax, VILmax
12
Input-loading specs
• Each gate input requires a certain amount of
current to drive it in the LOW state and in the
HIGH state.
– IIL and IIH
– These amounts are specified by the manufacturer.
• Fanout calculation
– (LOW state) The sum of the IIL values of the driven
inputs may not exceed IOLmax of the driving output.
– (HIGH state) The sum of the IIH values of the driven
inputs may not exceed IOHmax of the driving output.
– Need to do Thevenin-equivalent calculation for non-
gate loads (LEDs, termination resistors, etc.)
13
Manufacturer’s data sheet

14
TTL Logic Levels and Noise Margins
• Asymmetric, unlike CMOS

• CMOS can be made compatible with TTL


– “T” CMOS logic families

15
CMOS vs. TTL Levels

CMOS levels TTL levels

CMOS with TTL Levels


-- HCT, FCT, VHCT, etc.

16
TTL differences from CMOS
• Asymmetric input and output characteristics.
• Inputs source significant current in the LOW
state, leakage current in the HIGH state.
• Output can handle much more current in the
LOW state (saturated transistor).
• Output can source only limited current in the
HIGH state (resistor plus partially-on transistor).
• TTL has difficulty driving “pure” CMOS inputs
because VOH = 2.4 V (except “T” CMOS).

17
Transition times

18
Transition-time considerations
• Higher capacitance ==> more delay
• Higher on-resistance ==> more delay
• Lower on-resistance requires bigger
transistors
• Slower transition times ==> more power
dissipation (output stage partially shorted)
• Faster transition times ==> worse
transmission-line effects (Chapter 11)
• Higher capacitance ==> more power
dissipation (CV2f power), regardless of rise
and fall time
19
CMOS transmission gates

• 2-input multiplexer

20
Open-drain outputs
• No PMOS transistor, use resistor pull-up

21
What good is it?
• Open-drain bus

• Problem -- really bad rise time

22

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