VLSI Digital Circuits

Lecture 11: Dynamic

CMOS

[Adapted from Prof. Mary Jane Irwin Slides, Rabaey’s Digital Integrated Circuits,
Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Dynamic CMOS
 In static circuits at every point in time (except when
switching) the output is connected to either GND or VDD
via a low resistance path.
 fan-in of N requires 2N devices

 Dynamic circuits rely on the temporary storage of signal

values on the capacitance of high impedance nodes.
 requires only N + 2 transistors
 takes a sequence of precharge and conditional evaluation
phases to realize logic functions
Dynamic Gate

off
CLK Mp CLK Mp on
1
Out Out
!((A&B)|C)
In1 CL
A
In2 PDN
C
In3
B
CLK Me
off
CLK Me on

Two phase operation

Precharge (CLK = 0)
Evaluate (CLK = 1)
Conditions on Output
 Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
 Inputs to the gate can make at most one transition
during evaluation.

 Output can be in the high impedance state during and

after evaluation (PDN off), state is stored on CL
Properties of Dynamic Gates
 Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static
complementary CMOS)
 should be smaller in area than static complementary CMOS

 Full swing outputs (VOL = GND and VOH = VDD)

 Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)
 Faster switching speeds
 reduced load capacitance due to lower number of transistors per
gate (Cint) so a reduced logical effort
 reduced load capacitance due to smaller fan-out (C ext)
 no Isc, so all the current provided by PDN goes into discharging C L
 Ignoring the influence of precharge time on the switching speed of
the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
Properties of Dynamic Gates, con’t
 Power dissipation should be better
 consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
 lower CL- both Cint (since there are fewer transistors connected to
the drain output) and Cext (since there the output load is one per
connected gate, not two)
 by construction can have at most one transition per cycle – no
glitching

 But power dissipation can be significantly higher due to

 higher transition probabilities
 extra load on CLK

 PDN starts to work as soon as the input signals exceed

VTn, so set VM, VIH and VIL all equal to VTn
 low noise margin (NML)

 Needs a precharge clock

Dynamic Behavior

CLK
2.5
Out Evaluate
In1
In2 1.5

In3 Voltage
0.5 In &
In4 CLK
Out Precharge
CLK -0.5
0 0.5 1
Time, ns

#Trns VOH VOL VM NMH NML tpHL tpLH tp

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps
Gate Parameters are Time Independent
 The amount by which the output voltage drops is a
strong function of the input voltage and the available
evaluation time.
 Noise needed to corrupt the signal has to be larger if the
evaluation time is short – i.e., the switching threshold is truly
time independent.

CLK
2.5
Vout (VG=0.45)
Voltage (V)

1.5
Vout (VG=0.55)
Vout (VG=0.5)
0.5
VG

-0.5
0 20 40 60 80 100
Time (ns)
Power Consumption of Dynamic Gate

CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

Dynamic Power Consumption is Data Dependent

Dynamic 2-input NOR Gate

Assume signal probabilities

A B Out
PA=1 = 1/2
0 0 1 PB=1 = 1/2
0 1 0

1 0 0
Then transition probability
P01 = Pout=0 x Pout=1
1 1 0

= 3/4 x 1 = 3/4

Switching activity can be higher in dynamic gates!

P01 = Pout=0
Issues in Dynamic Design 1: Charge Leakage

CLK
4
3
CLK Mp
Out
1

A=0 CL
2
VOut Evaluate
CLK Me
Precharge

Leakage sources

Minimum clock rate of a few kHz

Impact of Charge Leakage
 Output settles to an intermediate voltage determined by
a resistive divider of the pull-up and pull-down networks
 Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.

CLK
2.5
Voltage (V)

1.5 Out

0.5

-0.5
0 20 40
Time (ms)
A Solution to Charge Leakage
 Keeper compensates for the charge lost due to the pull-
down leakage paths.
Keeper

CLK Mp Mkp

!Out
A
CL
B

CLK Me

Same approach as level restorer for pass

transistor logic
Issues in Dynamic Design 2: Charge Sharing

Charge stored originally on

CLK Mp CL is redistributed (shared)
Out
over CL and CA leading to
A CL
static power consumption by
B=0 Ca downstream gates and
possible circuit malfunction.
CLK Me Cb

When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is

large enough to be below the switching threshold of
the gate it drives causing a malfunction.
 Charge Sharing Example
What is the worst case voltage drop on y? (Assume all inputs are low
during precharge and that all internal nodes are initially at 0V.)
Load
CLK inverter
y=ABC

A !A Cy=50fF
a

B b
Ca=15fF !B B !B
c d Cb=15fF

Cc=15fF !C C Cd=10fF

CLK

Vout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy))

= - 2.5V*(30/(30+50)) = -0.94V
Solution to Charge Redistribution

CLK Mp Mkp CLK

Out
A

CLK Me

Precharge internal nodes using a clock-

driven transistor (at the cost of increased
area and power)
Issues in Dynamic Design 3: Backgate Coupling
 Susceptible to crosstalk due to 1) high impedance of the
output node and 2) backgate capacitive coupling
 Out2 capacitively couples with Out1 through the gate-source
and gate-drain capacitances of M4

CLK Mp M6 M5
Out1 =1
Out2 =0
A=0 M1 M4
CL1 CL2

B=0 M2 M3 In

CLK Me

Dynamic NAND Static NAND

Backgate Coupling Effect
 Capacitive coupling means Out1 drops significantly so
Out2 doesn’t go all the way to ground

2
Out1
Voltage

1
CLK

0
In Out2

-1
0 2 Time, ns 4 6
Issues in Dynamic Design 4: Clock Feedthrough
 A special case of backgate capacitive coupling between
the clock input of the precharge transistor and the
dynamic output node

CLK Mp
Coupling between Out and
Out CLK input of the precharge
A CL
device due to the gate-
drain capacitance. So
B voltage of Out can rise
above VDD. The fast rising
CLK Me
(and falling edges) of the
clock couple to Out.
Clock Feedthrough

CLK Clock feedthrough

Out
In1 2.5

In2
1.5
In3
Voltage

In &
In4 0.5 CLK
CLK Out
-0.5
0 0.5 Time, ns 1

Clock feedthrough
Issues in Dynamic Design 5: Cascading Gates
V

CLK
CLK Mp
CLK Mp
Out2
Out1 In
In
VTn
Out1
CLK Me CLK Me
V
Out2

Only a single 0  1 transition allowed at the

inputs during the evaluation period!
Domino Logic

CLK Mp CLK Mp Mkp

11 Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

CLK Me CLK Me
Why Domino?

CLK

In1
Ini PDN Ini PDN Ini PDN Ini PDN
Inj Inj Inj Inj
CLK

Like falling dominos!

Domino Manchester Carry Chain

CLK 3 3 3 3 3
P0 P1 P2 P3

4 3 2 1 Ci,4
Ci,0 5 G0 4 G1 3 G2 2 G3 1

CLK 6 5 4 3 2

!(G0 + P0 Ci,0) !(G1 + P1G0 + P1P0 Ci,0)

Domino Zero Detector

In7 In6 In5 In4 In3 In2 In1 In0

not zero

CLK
Properties of Domino Logic

 Only non-inverting logic can be implemented, fixes

include
 can reorganize the logic using Boolean transformations
 use differential logic (dual rail)
 use np-CMOS (zipper)

 Very high speed

 tpHL = 0
 static inverter can be optimized to match fan-out (separation of
fan-in and fan-out capacitances)
 Differential (Dual Rail) Domino

off on
CLK Mp Mkp Mkp Mp CLK

Out = AB 1 0 1 0 !Out = !(AB)

A
!A !B
B

CLK Me

Due to its high-performance, differential domino is

very popular and is used in several commercial
microprocessors!
Other Domino Variations
 Multiple output domino logic – exploits the fact that
certain outputs are subsets of other outputs to generate
a number of logic functions in a single gate.
 Compound domino
CLK Mp CLK Mp Mp

A D

B E G

C F H

CLK Me CLK Me Me
np-CMOS (Zipper)

CLK Mp !CLK Me
11 Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
Mp
(to PDN)
CLK Me !CLK

to other to other
PDN’s PUN’s

Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN
np-CMOS Adder Circuit

!CLK CLK 1x

0x Sum1
!A1 !B1 !B1 !C1
1x !A1
!A1 !A1 !B1 !C1
0  xC !B1
!CLK 2
CLK

!CLK
CLK 1  x !C1 B0
0x
A0 A0 B0 C0 A0
A0 B0 B0 1x C0
!Sum0
0x
C0 CLK !CLK
DCVS Logic

on  off off  on
10 01
Out !Out
In1
!In1
PDN1 PDN2
In2
off on on off
!In2

PDN1 and PDN2 are mutually exclusive

DCVSL Example

!Out
Out
B !B
!B B

A !A
 How to Choose a Logic Style
 Must consider ease of design, robustness (noise immunity),
area, speed, power, system clocking requirements, fan-out,
functionality, ease of testing
4-input NAND
Style # Trans Ease Ratioed? Delay Power
Comp Static 8 1 no 3 1
CPL* 12 + 2 2 no 4 3
domino 6+2 4 no 2 2 + clk
DCVSL* 10 3 yes 1 4
* Dual Rail

 Current trend is towards an increased use of

complementary static CMOS: design support through DA
tools, robust, more amenable to voltage scaling.
Next Lecture and Reminders
 Next lecture
 Timing metrics, static sequential circuits
- Reading assignment – Rabaey, et al, 7.1-7.2

 Reminders
 Project prototypes due on-line by 5:00pm on Oct 30th
 HW#4 due November 11th (not Nov 4th as on outline)
 HW#5 will be optional (due November 20th)
 Final exam scheduled
- Tuesday, December 16th from 10:10 to noon in TBD