High-Speed Serial Interface

Circuits and Systems

Lect. 5 – Phase-Locked Loop (PLL) 2
 Limitation of Type I PLL
K PD KVCO p
H (s) 
s 2   p s  K PD KVCO p

- Locking range is very narrow

Step response simulations:

f in  1Hz , K PD  5V / rad , KVCO  2  0.01rad / s / V , and f p  0.032 Hz

fin  0.01Hz f  0.05 Hz

 Limitation of Type I PLL
Problem lies in the very narrow linear phase detection range

With a large frequency difference,

phase difference can become too large
to be reliably detected
 Phase and Frequency Detector (PFD)
Vin

Vout

UP

DOWN

UP-DOWN

D Flip-flop:
Q becomes D at the rising clock edge
Q resets when R is HIGH UP-DOWN

-2π
2π 
 Charge Pump
Subtraction and integration Subtraction Integration

Voltage mode
using OP amplifiers

Subtraction

Integration
Current mode
using charge pump
 Charge Pump PLL
Charge Pump PLL

IC

- Linear continuous-time model for charge-pump PLL?

- Charge pump operation is not continuous but discrete
- But make an approximation Transfer function for PFD + Charge Pump:
1
Max :   VC (s): CP sC I
1
 1
For any : VC ( s )  I CP
2 sC1
VC I CP 1
T ( s)  ( s ) 
 2 sC1
 Charge Pump PLL

IC

Linear continuous-time model for charge-pump PLL

 Stability

G (s)
-40dB/decade

0 dB ω

G ( s )
ω
Open loop gain:
-180
1 1
G (s)  I CP KVCO 2
2 s C1 No phase margin  Unstable
 Stability
1 1
G (s)  I CP KVCO 2
2 s C1

G (s) -40dB/decade
G (s)
-40dB/decade
-20dB/decade
0 dB zero ω
0 dB ω
G ( s )
G ( s ) ω
ω -90
-180
-180

How to improve phase margin?

Introduce a zero
 Stability
G (s) -40dB/decade

-20dB/decade
0 dB zero ω
G ( s )
ω
-90
-180
Open loop gain:

1 sRC1  1
G (s)  I CP KVCO
2 s 2C1
However, there are ripples during transients for the step response

Qualitatively,
changes in charge pump currents
directly affect VC
 Charge Pump PLL
Solution
Ripple reduction with small C2 ( < C1/10)

 3rd order system

For dynamics analysis, 2nd-order PLL without C2 is often used
 Charge Pump PLL
Solution

1 sRC1  1
G (s)  I CP KVCO
2 s 2C1

I CP KVCO
( RC1s  1)
2 C1
H ( s) 
I I
s 2  CP KVCO Rs  CP KVCO
2 2 C1

2n s  n 2 I CP KVCO 
R I CP C1 KVCO
H (s)  2 n  2
s  2n s  n 2 2 C1 2

C2 does affect PLL dynamics:

It introduces an additional pole, which reduces the phase margin

Careful simulation is required for real PLL design

 CP PLL Step Responses
f in  f out  200 Hz f in  f out  200 Hz
I CP  100 A I CP  100 A
KVCO  2 100rad / s / V KVCO  2  100rad / s / V
f n  1Hz   0.7

f n  4 Hz
  0.36
f n  2 Hz
  0.7 f n  1Hz
  1.4

( dependence) (n dependence)

 Optimization for desired performance!

 Charge Pump PLL with a Divider
I CP KVCO
( RC1s  1)
2 C1 2n s  n 2 I CP KVCO R I CP C1 KVCO
H (s)   2 n  
I I s  2n s  n 2 2 C1 2 2
s 
2 CP
KVCO Rs  CP
KVCO
2 2 C1

What if the feedback loop has a divider?

1 sRC1  1
Forward loop gain? G ( s)  I CP KVCO
2 s 2C1
1
Feedback loop gain?
M Division
by M
I CP KVCO
( RC1s  1)
H (s) 
G (s) 2  C
G ( s) 
1 I CP KVCO R I CP C1 KVCO
n  
1 s 2

1 I CP
K Rs 
1 I CP
KVCO 2 C1M 2 2 M
M M 2
VCO
M 2 C1

(2n s  n 2 ) M
 2
s  2n s  n 2
 PLL Phase Errors
(2n s  n 2 ) M I CP KVCO R I CP C1 KVCO
H (s)  2 n  
s  2n s  n 2 2 C1M 2 2 M

   H (s)
H e ( s )   in  out  in
/   1 
 M  M

s2

Division
s 2  2n s  n2
by M

  
- Phase error due to phase step? e (t  )  lim  sH e ( s )
s 0
 s 

- Phase error due to frequency step?  (t  )  lim  sH ( s )  

e  e 2 
s 0
 s 
Input-Noise Transfer Function
• Input noise
ϕnoise PFD + Voltage
Loop
Charge Controlled ϕout
Filter
pump Oscillator

Main
Divider

out (2n s  n 2 ) M
H ( s)   2
noise s  2n s  n 2
VCO-Noise Transfer Function
• VCO phase noise
ϕnoise

ϕref PFD + Voltage

Loop
Charge Controlled ϕout
Filter
pump Oscillator

Main
Divider

out
out   G ( s )  noise I CP KVCO
M n 
2 C1M
out  1

1 s2
H ( s)   2
noise 1  G ( s ) / M 1  G ( s ) / M s  2n s  n 2 R I CP C1 KVCO

2 2 M
 High pass filter
 Optimal PLL Bandwidth
ϕnoise

PFD + Voltage
ϕnoise Loop
Charge Controlled ϕout
Filter
pump Oscillator

Main
Divider

- Optimal PLL bandwidth depends on characteristics of each noise source

 Design Project 1