ECE 612

Design of Digital Integrated Circuits

Spring 2014
Lecture 4
Dynamic Combinational Logic

S. A. Ibrahim
Ain Shams University
ICL
 Outline

 Dynamic Vs. Static Logic

 Basic Concept of Dynamic Logic
 Cascading Dynamic Logic Gates
 Dynamic Logic Design Issues
 Dynamic Gates Styles

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 Dynamic CMOS

 In static circuits at every point in time (except

when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type) devices

 Dynamic circuits rely on the temporary storage

of signal values on the capacitance of high
impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type) transistors

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 Dynamic Gate Example

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
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 Conditions on Output

 Once the output of a dynamic gate is

discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.
 Output can be in the high impedance state
during and after evaluation (PDN off), state is
stored on CL.

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 Properties of Dynamic Gates (1)

 Logic function is implemented by the PDN only.

 Number of transistors is N + 2 (versus 2N for static complementary
CMOS).
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed
 Faster switching speeds
 Reduced load capacitance due to lower input capacitance (Cin)
 Reduced load capacitance due to smaller output loading (Cout)
 No Isc, so all the current provided by PDN goes into discharging CL

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 Properties of Dynamic Gates (2)
 Overall power dissipation usually higher than
static CMOS.
 No static current path ever exists between VDD and
GND (including Psc).
 No glitching
 Higher transition probabilities 01  P( Out  0 )
 Extra load on Clk
 PDN starts to work as soon as the input
signals exceed VTn, so VM, VIH and VIL equal to
VTn.
 Low noise margin (NML)
 Needs a precharge/evaluate clock.

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Logical Effort of Dynamic Gates

Clk Mp Clk Mp
Out Out
A 3
IN 2
B 3

Clk Me 2 Clk Me 3

Cgate,IN= 2 Cgate,A= 3
LEIN= 2/3 LEA= 1

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 P-type Dynamic Gates

off
Clk Me Clk Me on

In1
A
In2 PUN
C
In3
Out B
0
Clk Mp Out
CL off
Clk Mp on ((A+B)C)
Two phase operation
Pre-discharge (Clk = 1)
Evaluate (Clk = 0) OK but Slower
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 Example
 Implement the logic function F=AB+C using n-type
dynamic logic.
 Repeat using p-type dynamic logic.

Clk Mp Clk Me
Out
A

B
A B C
C
Out
Clk Me Clk Mp

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 Cascading Dynamic Gates

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0  1 transitions allowed at inputs!

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 Clock Delaying (1)
• Input has to be stable during evaluate.
• Use an appropriately-delayed clock.
• Note that there is a “race” during pre-charge.
• Not a functional problem but wastes power.
• May limit the maximum delay permitted.

In
Clk2
Clk1 Mp delay Mp Clk1
Out2
Out1
Clk2
In
Out1
Clk Me Clk Me
Out2
Possible race
t
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 Clock Delaying (2)
• Delay the clock for each stage so that the inputs are “levelized”
before the stage EVALUATES.
• Must use the longest delay.
• Or match each element independently.
• Goal is to track the delay of the circuit.
• Under environmental variations.
• Use dummy logic gates that look like the circuit.

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 Domino Logic

Clk Mp Clk Mp
11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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 Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Clk

Like falling dominos!

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 Properties of Domino Logic

 Only non-inverting logic can be implemented.

 Very high speed
 Static inverter can be skewed. (Only L-H transition)
 Input capacitance reduced. (Smaller logical effort)

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 Designing with Domino Logic

• To convert to Domino-style design, we need to create

schematic that uses non-inverting gates:
1. Look for CMOS gates followed by inverter.
2. Use De Morgan’s Law to create non-inverting gates.
• Not always possible

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 Logical Effort of Domino Gates
AND Gate OR Gate

Clk Mp 2 Clk Mp 2
Out Out
A 3 1 B 2A 2 1

B 3
Clk Me 2

Clk Me 3

LENAND= 3/3=1 LENOR= 2/3

LEINV= 1 LEINV= 1
𝐿𝐸 = 1 𝐿𝐸 = 2/3

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LE of Domino Gates with Skewed Inverters
AND Gate OR Gate

Clk Mp
Why not larger? Clk
4 Mp 4
Out Out
A 3 1 B 2A 2 1

B 3
Clk Me 2

Clk Me 3

LENAND= 3/3=1 LENOR= 2/3

LEINV,LH=((1/2)*5)/(1*3)=5/6 LEINV,LH=5/6
𝐿𝐸 = 5/6 𝐿𝐸 = 5/9

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 Average Logical Effort

• When sizing a chain, a domino gate is actually two gates.

• The relative sizing of the two gates is fixed.
• We need an equivalent model with average LE to be used in the chain.

Clk Mp 2
Out
A 3 1
LEavg LEavg
B 3

Clk Me 3 𝐿𝐸𝑎𝑣𝑔 = 𝐿𝐸

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 Footless Domino
VDD VDD
VDD

Clk Mp Clk Mp Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!

Clk Me Clk Me

Inputs = 0
during precharge
• The first gate in the chain needs a foot switch, others don’t.
• Precharge is rippling.  short-circuit current
• A solution is to delay the clock for each stage.
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 LE of Footless Domino
AND Gate OR Gate

Clk Mp 4 Clk Mp 4
Out Out
A 2 1 B 1A 1 1

B 2

LENAND= 2/3 LENOR= 1/3

LEINV,LH=5/6 LEINV,LH=5/6
𝐿𝐸 = 5/9 𝐿𝐸 = 5/18

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 Parasitic Delay

LE LE LE

LE LE LE

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 Pre-Charge Properties
 Many domino gates can evaluate in one half-cycle, so it should be
easy to pre-charge a single domino gate in the other half-cycle. But…
 The domino gate must pre-charge enough to flip the high skew gate,
then the high skew gate must fall below Vt by sufficient noise margin
before evaluation starts again.
 To speed up domino evaluation, we want a small pre-charge transistor
(small diffusion parasitic capacitances).
• Makes pre-charge slow.
• High skew gate falls very slowly.
 Delaying the clock to avoid pre-charge contention in un-clocked pull-
down stacks reduces pre-charge time for domino gates with delayed
clocks.
 Cycles are getting shorter.
 Advanced domino methodologies are stretching the length of
evaluation phase at the expense of pre-charge time.
 Bottom line: pre-charge time is becoming an important issue. Size for
roughly equal pre-charge and evaluate times.
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 Outline

 Dynamic Vs. Static Logic

 Basic Concept of Dynamic Logic
 Cascading Dynamic Logic Gates
 Dynamic Logic Design Issues
 Dynamic Gates Styles

S. A. Ibrahim
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 Design Issues: Charge Leakage

CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current.

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Design Issues: Coupling & Ground Bounce

 The output of a dynamic gate is a floating node.

 Coupling on the dynamic node can cause the static gate
to glitch.
 Input glitches can discharge dynamic node.
 Ground bounce can cause a glitch or turn on the NMOS
pull down.
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 Adding Keepers
Keeper

 Same approach as level restorer for pass-transistor logic

 Keepers degrade evaluation speed.
 Prefer separate inverter for keeper
 Allows complex static gates, minimizes noise coupled onto
keeper.
 “Dual-gate” keeper Dual gate minimizes load on tiny gates.

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 Delayed Keepers
 Weakened keepers are not as effective at restoring the degraded
voltage.
 To avoid fighting, we can turn on a stronger keeper after a small
delay.
 Can make it only work for HIGH output. [Alvandpour, JSSC02]
 Key is to not delay by too much.
 Restore before too much charge is gone.
 But not start the keeper before all the inputs have arrived.

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 Design Issues: Charge Sharing

Charge stored originally on CL

Clk Mp is redistributed (shared) over
Out CL and CA leading to reduced
A CL robustness.
B=0 CA

Clk Me CB

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 Charge Sharing
Two cases:
VDD • Ma turns off – incomplete charge sharing
• Ma stays on – complete charge sharing
Clk Mp
VDD case 1) if Vout < VTn C < C VTn Vx
a L
Out VDD − VTn Vx
 Mp CL CLVDD = CLVout  t  + Ca VDD – VTn VX 
A Ma Out
or
X
CL Ca
A Ma Ca Vout = Vout  t  – VDD = – --------  VDD – VTn VX 
CL
B0 Mb X

Ca VTn Vx
B=0 Mb case 2) if Vout > VTn Ca > CL
Cb VDD − VTn Vx
Clk Me
Ca 
 ---------------------
Cb Vout = –VDD -
 Me C
 a + C L
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 Charge Sharing Example
 What is the worst case drop?

Clk
Out
A A CL=50fF

Ca=15fF B B B B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

30
ABC or ABC with ∆𝑉𝑜𝑢𝑡 = × 2.5 = 0.94 𝑉
30+50
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 Solution to Charge Redistribution

Clk Mp Mkp Clk

Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor (at

the cost of increased area and power).

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 Pre-Charging Internal Nodes
 Normally, internal nodes are pre-charged with small PMOS
devices.
 Not crucial to get node to 100% of Vdd, just reduce noise.
 Gates actually run faster when some charge sharing occurs.
 Less capacitance needs to be pulled all the way down.
 Sometimes pre-charge an internal node to Vdd-Vt with an NMOS
device.
 Maybe even pre-discharge an internal node to speed it up.
 Worst case for speed is with node high, worst case for noise is with
node low.
 If we can tolerate the noise with node low, we might improve the
speed by guaranteeing the node is low.
 Use small NMOS device (make sure it is off during evaluation)
 Only can pre-discharge a node if no path to Vdd possibly exists.
 Must be sure that noise is tolerable for all cases when doing
this.
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 Outline

 Dynamic Vs. Static Logic

 Basic Concept of Dynamic Logic
 Cascading Dynamic Logic Gates
 Dynamic Logic Design Issues
 Dynamic Gates Styles

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 Differential (Dual Rail) Domino
off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
A B
B

Clk Me

• Solves the problem of non-inverting logic.

• Similar to DCSVL.
• Generating both output and complement of
output can be costly at high fan-in.
• Keepers make it static.

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 Other Forms of Domino Logic

Multiple-Output Domino Compound Domino

• Some outputs are subsets of other • Complex static gates used rather than
outputs. inverters.
• Internal nodes have to be precharged. • Outputs are combined reducing
• Evaluate transistors are shared. transistor count.
• Usually used in adders. • Large fan-in gates can be implemented
by parallel smaller ones.
• Back-gate coupling is an issue.
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 np-CMOS

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN
• Very susceptible to noise (only dynamic gates with low noise margin)
• P-stages have worse LE than skewed inverters.
• 2 clock phases are needed.
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 NORA Logic

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDN’s PUN’s

NORA = NO RAce
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 Dynamic CML (DyCML)

 DyCML circuits combine the advantages of MOS current mode logic (MCML)
circuits with those of dynamic logic families to achieve high performance at
a low-supply voltage with low-power dissipation. [Allam, JSSC01]
 Q2, Q3, and Q4 are ON during pre-charge phase, pre-charging outputs to VDD,
and discharging C1.
 During Evaluation, Q1 acts as a current source. Q5 and Q6 amplifies the
difference between a and b.
 Size C1 so that the dynamic charge is sufficient to discharge output
capacitance.
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 Combinational Logic Summary
Static Dynamic
 Robust in the presence  Fast and small complex
of noise gates
 Ease of design  Suffers from parasitic
 No static power effects
consumption
 Large area and bad
performance for large
fan-in
 PT logic is attractive for
multiplexers and XOR-
dominated logic.

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 Reading
 Rabaey: Sections 6.3
 Weste: Sections 9.2.4
 A. Alvandpour, R. Krishnamurthy, K. Soumyanath, and
S. Borkar, "A sub-130-nm conditional keeper
technique," JSSC, vol. 37, no. 5, May 2002, pp. 633-638.
 M. Allam and M. Elmasry, "Dynamic current mode logic
(DyCML): a new low-power high-performance logic
style," JSSC, vol. 36, no. 3, March 2001, pp. 550-558.

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