Dynamic Sequential Circuits

Review: Sequential Definitions

 Static versus dynamic storage
 static uses a bistable element with feedback (regeneration) and
thus preserves its state as long as the power is on
 static is preferred when updates are infrequent
 dynamic stores state on parasitic capacitors so only holds the
state for a period of time (milliseconds) and requires periodic
refresh
 dynamic is usually simpler (fewer transistors), higher speed, lower
power

 Latch versus flipflop

 latches are level sensitive with two modes: transparent - inputs
are passed to Q and hold - output stable
 fliplflops are edge sensitive that only sample the inputs on a clock
transition
Review: Timing Metrics
In D Q Out

clock
clock

tsu thold time

In data
stable
tc-q time

Out output output

stable stable
time
Review: System Timing Constraints

Inputs Outputs
Combinational
Logic

Current Next

Registers
State State

State
T (clock period)
clock

tcdreg + tcdlogic  thold T  tc-q + tplogic + tsu

Dynamic Flipflop
master slave

!clk clk

QM
D T1 I1 T2 I2 Q

C1 C2
clk !clk
tsu = tpd_tx
thold = zero
master transparent
tc-q = 2 tpd_inv + tpd_tx
slave hold
clk

!clk master hold

slave transparent
Pseudostatic Dynamic Latch
 Robustness considerations limit the use of dynamic FF’s
 coupling between signal nets and internal storage nodes can
inject significant noise and destroy the FF state
 leakage currents cause state to leak away with time

 A simple fix is to make the circuit pseudostatic

clk

QM
Q

!clk

 Add above logic to all dynamic latches

Dynamic FF Race Conditions

!clk clk

QM
D T1 I1 T2 I2 Q

C1 C2
clk !clk

0-0 overlap race condition

clk toverlap0-0 < tT1 + tI1 + tT2
!clk
1-1 overlap race condition
toverlap1-1 < thold
Fix 1: Dynamic Two-Phase FF

clk1 clk2

QM
D T1 I1 T2 I2 Q

C1 C2
!clk1 !clk2
master transparent
slave hold

clk1
tnon_overlap
clk2
master hold
slave transparent
C2MOS (Clocked CMOS) Flipflop
 A clock-skew insensitive FF
Master Slave

M2 M6

clk Mon
4
!clk Moff
8
off QM on
D Q
!clk Mon
3
C1 clk Moff
7
C2
off on
M1 M5

master transparent
slave hold
clk

!clk master hold

slave transparent
C2MOS FF 0-0 Overlap Case
 Clock-skew insensitive

M2 M6

0 M4 0 M8
QM
D Q
C1 C2

M1 M5

clk
!clk
C2MOS FF 1-1 Overlap Case

M2 M6

QM
D Q
1 M3 C1 1 M7 C2

M1 M5

clk
!clk

1-1 overlap constraint

toverlap1-1 < thold
 Pipelining using C2MOS

clk !clk clk

F G Out
In
!clk C1 clk C2 !clk C3

NORA (No Race) Logic

What are the constraints on F and G?

Only Non-Inverting Logic Allowed

clk on !clk (off)

In = 1
on clk (on)
!clk

The number of static inversions should be even.

Fix 3: True Single Phase Clocked (TSPC) Latches

Negative Latch Positive Latch

clk clk Q
In In clk clk
Q

hold when clk = 1 transparent when clk = 1

transparent when clk = 0 hold when clk = 0
 Embedding Logic in TSPC Latch

PUN A B

Q Q
In clk clk clk clk

A
PDN
B
TSPC FF
Master Slave

clk on clk on on on Q
D
off off QM clk off clk off

master transparent
slave hold
master hold
clk slave transparent
Simplified TSPC FF

off
M3 clk on
M 6 M9
QM 1 D
QD
D clk Mon
off 2 X !D M5 clk Moff
on 8
M1 clk Moff
4 M7
on

master transparent
slave hold
master hold
clk slave transparent
 Split-Output TSPC Latches
Positive Latch Negative Latch

Q A
In clk In clk
A Q

transparent when clk = 1 hold when clk = 1

hold when clk = 0 transparent when clk = 0

When In = 0, A = VDD - VTn When In = 1, A = | VTp |

Split-Output TSPC FF

clk
D clk QM
Q

clk
Choosing a Clocking Strategy
 Choosing the right clocking scheme affects the
functionality, speed, and power of a circuit
 Two-phase designs
 + robust and conceptually simple
 - need to generate and route two clock signals
 - have to design to accommodate possible skew between the
two clock signals

 Single phase designs

 + only need to generate and route one clock signal
 + supported by most automated design methodologies
 + don’t have to worry about skew between the two clocks
 - have to have guaranteed slopes on the clock edges