Typical Timing Specifications: Positive Edge-Triggered D Flip-Flop

Typical Timing Specifications
 Positive edge-triggered D flip-flop

 Setup and hold times
 Minimum clock width
 Propagation delays (low to high, high to low, max and typical)
D Tsu Th Tsu Th
20ns 5ns 20ns 5ns
CLK Tw 25ns
Tplh Tphl
Q 25ns 40ns
13ns 25ns
all measurements are made from the clocking event that is,
the rising edge of the clock
CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 2
Cascading Edge-triggered Flip-Flops
 Shift register
 New value goes into first stage
 While previous value of first stage goes into second stage
 Consider setup/hold/propagation delays (prop must be > hold)
Q0 Q1
IN D Q D Q OUT
CLK
100
IN
Q0
Q1
CLK

 Shift register
 New value goes into first stage
 While previous value of first stage goes into second stage
 Consider setup/hold/propagation delays (prop must be > hold)
Q0 Q1
IN D Q D Q OUT
Clk1
CLK Delay
100
IN
Q0
Q1
CLK
Clk1
(cont’d)
 Why this works

 Propagation delays exceed hold times
 Clock width constraint exceeds setup time
 This guarantees following stage will latch current value
before it changes to new value
In
Tsu Tsu
4ns 4ns timing constraints
guarantee proper
Q0 operation of
Tp Tp
3ns 3ns cascaded components
Q1
assumes infinitely fast
CLK distribution of the clock
Th Th
2ns 2ns
Clock Skew
 The problem
 Correct behavior assumes next state of all storage elements
determined by all storage elements at the same time
 Difficult in high-performance systems because time for clock
to arrive at flip-flop is comparable to delays through logic
(and will soon become greater than logic delay)
 Effect of skew on cascaded flip-flops:
100
In
CLK1 is a delayed
Q0 version of CLK0
Q1
CLK0
CLK1
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1
Registers
 Collections of flip-flops with similar controls and logic

 Stored values somehow related (e.g., form binary value)
 Share clock, reset, and set lines
 Similar logic at each stage
 Examples
 Shift registers
 Counters
OUT1 OUT2 OUT3 OUT4

"0"
R S R S R S R S
D Q D Q D Q D Q
CLK
IN1 IN2 IN3 IN4

Shift Register
 Holds samples of input

 Store last 4 input values in sequence
 4-bit shift register:
OUT1 OUT2 OUT3 OUT4
IN D Q D Q D Q D Q
CLK

Shift Register Verilog
module shift_reg (out4, out3, out2, out1, in, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;
always @(posedge clk)

begin
out4 <= out3;
out3 <= out2;
out2 <= out1;
out1 <= in;
end
endmodule

Shift Register Verilog
module shift_reg (out, in, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;

begin
out <= {out[3:1], in};
end
endmodule

Universal Shift Register
 Holds 4 values
 Serial or parallel inputs
 Serial or parallel outputs
 Permits shift left or right
 Shift in new values from left or right
output
clear sets the register contents
and output to 0
left_in right_out
left_out right_in s1 and s0 determine the shift function
clear
s0 clock s0 s1 function
s1 0 0 hold state
0 1 shift right
1 0 shift left
1 1 load new input
input

Design of Universal Shift Register
 Consider one of the four flip-flops

 New value at next clock cycle:
Nth cell
to N-1th to N+1th
cell Q cell
D
CLK
clear s0 s1 new value CLEAR

1 – – 0 s0 and s1
0 0 0 output 0 1 2 3
control mux
0 0 1 output value of FF to left (shift right)
0 1 0 output value of FF to right (shift left) Q[N-1] Q[N+1]
0 1 1 input (left) (right)
Input[N]

Universal Shift Register Verilog
module univ_shift (out, lo, ro, in, li, ri, s, clr, clk);
output [3:0] out;
output lo, ro;
input [3:0] in;
input [1:0] s;
input li, ri, clr, clk;
reg [3:0] out;
assign lo = out[3];
assign ro = out[0];
always @(posedge clk or clr)

begin
if (clr) out <= 0;
else
case (s)
3: out <= in;
2: out <= {out[2:0], ri};
1: out <= {li, out[3:1]};
0: out <= out;
endcase
end
endmodule
Counters
 Sequences through a fixed set of patterns

 In this case, 1000, 0100, 0010, 0001
 If one of the patterns is its initial state (by loading or
set/reset) OUT1 OUT2 OUT3 OUT4
IN D Q D Q D Q D Q
CLK
 Mobius (or Johnson) counter

 In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000
OUT1 OUT2 OUT3 OUT4
IN D Q D Q D Q D Q
CLK

Binary Counter
 Logic between registers (not just multiplexer)

 XOR decides when bit should be toggled
 Always for low-order bit, only when first bit is true for
second bit, and so on
OUT1 OUT2 OUT3 OUT4
D Q D Q D Q D Q
CLK
"1"
=

Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output out4, out3, out2, out1;
input in, clk;
reg out4, out3, out2, out1;

begin
out4 <= (out1 & out2 & out3) ^ out4;
out3 <= (out1 & out2) ^ out3;
out2 <= out1 ^ out2;
out1 <= out1 ^ 1b’1;
end
endmodule

Binary Counter Verilog
module shift_reg (out4, out3, out2, out1, clk);
output [4:1] out;
input in, clk;
reg [4:1] out;

out <= out + 1;
endmodule

Sequential Logic Summary
 Fundamental building block of circuits with state
 Latch and flip-flop
 R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
 Timing methodologies
 Use of clocks
 Cascaded FFs work because prop delays exceed hold times
 Beware of clock skew
 Basic registers
 Shift registers
 Pattern detectors
 Counters

Sequential Logic Implementation
 Models for representing sequential circuits

 Finite-state machines (Moore and Mealy)
 Representation of memory (states)
 Changes in state (transitions)
 Design procedure
 State diagrams
 State transition table
 Next state functions

Abstraction of State Elements
 Divide circuit into combinational logic and state

 Localize feedback loops and make it easy to break cycles
 Implementation of storage elements leads to various
forms of sequential logic
Inputs Outputs
Combinational
Logic
State Inputs State Outputs
Storage Elements

Forms of Sequential Logic
 Asynchronous sequential logic – state changes occur

whenever state inputs change (elements may be simple
wires or delay elements)
 Synchronous sequential logic – state changes occur in
lock step across all storage elements (using a periodic
waveform - the clock)
Clock
Finite State Machine Representations
 States: determined by possible values in sequential
storage elements
 Transitions: change of state
 Clock: controls when state can change by controlling
storage elements
001 010 111
In = 1 In = 0
In = 0
100 110
 Sequential Logic In = 1
 Sequences through a series of states
 Based on sequence of values on input signals
 Clock period defines elements of sequence

Example Finite State Machine Diagram
 Combination lock
ERR
closed
not equal not equal

& new not equal
& new & new
S1 S2 S3 OPEN
reset closed closed closed
open
mux=C1 equal mux=C2 equal mux=C3 equal
& new & new & new
not new not new not new

Can Any Sequential System be
Represented with a State Diagram?
 Shift Register OUT1 OUT2 OUT3

 Input value shown
on transition arcs D Q D Q D Q
IN
 Output values shown
within state node CLK
1
100 110
1 0 1 1
1
0 000 1 010 101 0 111 1
0
0 0 1 0
001 011
0

Counters are Simple Finite State Machines
 Counters
 Proceed thru well-defined state sequence in response to enable
 Many types of counters: binary, BCD, Gray-code
 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...
001 010 011
000 3-bit up-counter 100
111 110 101

Verilog Upcounter
module binary_cntr (q, clk)
inputs clk;
outputs [2:0] q;
reg [2:0] q;
reg [2:0] p;
always @(q) //Calculate next state

case (q)
3’b000: p = 3’b001;
3’b001: p = 3’b010;
…
3’b111: p = 3’b000;
endcase
always @(posedge clk) //next becomes current state

q <= p;
endmodule
How Do We Turn a State Diagram into Logic?
 Counter
 Three flip-flops to hold state
 Logic to compute next state
 Clock signal controls when flip-flop memory can change
 Wait long enough for combinational logic to compute new value
 Don't wait too long as that is low performance
OUT1 OUT2 OUT3
D Q D Q D Q
CLK
"1"

FSM Design Procedure
 Start with counters
 Simple because output is just state
 Simple because no choice of next state based on input
 State diagram to state transition table
 Tabular form of state diagram
 Like a truth-table
 State encoding
 Decide on representation of states
 For counters it is simple: just its value
 Implementation
 Flip-flop for each state bit
 Combinational logic based on encoding

FSM Design Procedure: State Diagram
to Encoded State Transition Table
 Tabular form of state diagram

 Like a truth-table (specify output for all input
combinations)
 Encoding of states: easy for counters – just use value
current state next state

001 010 011 0 000 001 1
1 001 010 2
2 010 011 3
000 3-bit up-counter 100
3 011 100 4
4 100 101 5
111 110 101 5 101 110 6
6 110 111 7
7 111 000 0

Implementation
 D flip-flop for each state bit
 Combinational logic based on encoding
notation to show
function represent
C3 C2 C1 N3 N2 N1 input to D-FF
0 0 0 0 0 1
0 0 1 0 1 0 N1 := C1'
0 1 0 0 1 1 N2 := C1C2' + C1'C2
:= C1 xor C2
0 1 1 1 0 0
N3 := C1C2C3' + C1'C3 + C2'C3
1 0 0 1 0 1 := C1C2C3' + (C1' + C2')C3
1 0 1 1 1 0 := (C1C2) xor C3
1 1 0 1 1 1
1 1 1 0 0 0
N3 C3 N2 C3 N1 C3
0 0 1 1 0 1 1 0 1 1 1 1
C1 0 1 0 1 C1 1 0 0 1 C1 0 0 0 0
C2 C2 C2
Implementation (cont'd)
 Programmable Logic Building Block for Sequential Logic

 Macro-cell: FF + logic
 D-FF
 Two-level logic capability like PAL (e.g., 8 product terms)
DQ
Q

State Machine Model
 Values stored in registers represent the state of the

circuit
 Combinational logic computes:
 Next state
 Function of current state and inputs
 Outputs
 Function of current state and inputs (Mealy machine)
 Function of current state only (Moore machine)
output Outputs
logic
Inputs
next state Next State
logic
Current State
State Machine Model (cont’d)
output Outputs
logic
 States: S1, S2, ..., Sk Inputs
next state Next State
 Inputs: I1, I2, ..., Im logic
 Outputs: O1, O2, ..., On

Current State
 Transition function: Fs(Si, Ij)
 Output function: Fo(Si) or Fo(Si, Ij)
Next State
State
Clock 0 1 2 3 4 5

Example: Ant Brain (Ward, MIT)
 Sensors: L and R antennae, 1 if in touching wall
 Actuators: F - forward step, TL/TR - turn
left/right slightly
 Goal: find way out of maze
 Strategy: keep the wall on the right

Ant Brain

Ant Behavior
A: Following wall, touching B: Following wall, not touching
Go forward, turning Go forward, turning right
left slightly. slightly
If R and not L, go to A if R, go to A
If R and L , go to E if not R, go to C
else go to B
C: Break in wall
Go forward, turning E: Wall in front or on left
right slightly Turn left
if R, go to A If L or R, stay in E
if not R, stay in C Otherwise, go to B
LOST: Forward until we

touch something

Designing an Ant Brain
 State Diagram
L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’

Synthesizing the Ant Brain Circuit
 Encode States Using a Set of State Variables
 Arbitrary choice - may affect cost, speed
 Use Transition Truth Table
 Define next state function for each state variable
 Define output function for each output
 Implement next state and output functions using
combinational logic
 2-level logic (ROM/PLA/PAL)
 Multi-level logic
 Next state and output functions can be optimized together

Transition Truth Table
 Using symbolic states

and outputs L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
state L R next state outputs B C
LOST 0 0 LOST F (TR, F) (TR, F) R’
LOST – 1 E/G F R’
LOST 1 – E/G F
A 0 0 B TL, F
A 0 1 A TL, F
A 1 – E/G TL, F
B – 0 C TR, F
B – 1 A TR, F
... ... ... ... ...
Synthesis
 5 states : at least 3 state variables required (X, Y, Z)

 State assignment (in this case, arbitrarily chosen) LOST - 000
E - 001
A - 010
B - 011
C - 100
state L R next state outputs it now remains
X,Y,Z X', Y', Z' F TR TL to synthesize
000 0 0 000 1 0 0 these 6 functions
000 0 1 001 1 0 0
... ... ... ... ...
010 0 0 011 1 0 1
010 0 1 010 1 0 1
010 1 0 001 1 0 1
010 1 1 001 1 0 1
011 0 0 100 1 1 0
011 0 1 010 1 1 0
... ... ... ... ...

Synthesis of Next State and Output
Functions
state inputs next state outputs
X,Y,Z L R X+,Y+,Z+ F TR TL
000 0 0 000 1 0 0
000 - 1 001 1 0 0
000 1 - 001 1 0 0
001 0 0 011 0 0 1
001 - 1 010 0 0 1 e.g.
001 1 - 010 0 0 1
010 0 0 011 1 0 1 TR = X + Y Z
010 0 1 010 1 0 1 X+ = X R’ + Y Z R’ = R’ TR
010 1 - 001 1 0 1
011 - 0 100 1 1 0
011 - 1 010 1 1 0
100 - 0 100 1 1 0
100 - 1 010 1 1 0

Circuit Implementation
 Outputs are a function of the current state only - Moore machine
output F
TR
logic
TL
L next state Next State
R logic
X+ Y+ Z+
Current State
X Y Z

Verilog Sketch
module ant_brain (F, TR, TL, L, R)
inputs L, R;
outputs F, TR, TL;
reg X, Y, Z;
assign F = function(X, Y, Z, L, R);

assign TR = function(X, Y, Z, L, R);
assign TL = function(X, Y, Z, L, R);

begin
X <= function (X, Y, Z, L, R);
Y <= function (X, Y, Z, L, R);
Z <= function (X, Y, Z, L, R);
end
endmodule

Don’t Cares in FSM Synthesis
 What happens to the "unused" states (101, 110, 111)?

 Exploited as don't cares to minimize the logic
 If states can't happen, then don't care what the functions do
 if states do happen, we may be in trouble
L’ R’
L+R L’ R
000 L+R 001 L 010
(F) (TL) (TL, F)
101
L’ R’ R
R
L’ R’
011 100
110 (TR, F) (TR, F) R’
R’
111
Ant is in deep trouble
if it gets in this state
State Minimization
 Fewer states may mean fewer state variables
 High-level synthesis may generate many redundant states
 Two state are equivalent if they are impossible to distinguish
from the outputs of the FSM, i. e., for any input sequence the
outputs are the same
 Two conditions for two states to be equivalent:

 1) Output must be the same in both states
 2) Must transition to equivalent states for all input combinations

Ant Brain Revisited
 Any equivalent states?
L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’

Ant Brain Revisited
Inequivalent since actions differ
L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’
Potentially Equivalent (actions equivalent)

Equivalence Proof
Equivalent Behavior under R
L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
R
L’ R’
B C
R’
(TR, F) (TR, F)
R’
Equivalent Behavior under R’

New Improved Brain
 Merge equivalent B and C states

 Behavior is exactly the same as the 5-state brain
 We now need only 2 state variables rather than 3
L+R L’ R
LOST L+R E L A
(F) (TL) (TL, F)
L’ R’ L’ R’ R
L’ R’
B/C
R’
(TR, F)

New Brain Implementation
state inputs next state outputs

X+ X Y+ X
X,Y L R X',Y' F TR TL
0 1 1 1 0 1 1 1
00 0 0 00 1 0 0
0 0 1 1 1 0 0 0
00 - 1 01 1 0 0 R R
L 0 0 1 0 L 1 0 0 1
00 1 - 01 1 0 0 0 0 1 0 1 0 1 1
01 0 0 11 0 0 1
Y Y
01 - 1 01 0 0 1
01 1 - 01 0 0 1
10 0 0 11 1 0 1 F X TR X TL X
10 0 1 10 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1
10 1 - 01 1 0 1 1 0 1 1 0 0 1 0 0 1 0 1
R R R
L 1 0 1 1 L 0 0 1 0 L 0 1 0 1
11 - 0 11 1 1 0
1 0 1 1 0 0 1 0 0 1 0 1
11 - 1 10 1 1 0
Y Y Y

Sequential Logic Implementation Summary
 Models for representing sequential circuits

 Abstraction of sequential elements
 Finite state machines and their state diagrams
 Inputs/outputs
 Mealy, Moore, and synchronous Mealy machines
 Finite state machine design procedure
 Deriving state diagram
 Deriving state transition table
 Determining next state and output functions
 Implementing combinational logic

Typical Timing Specifications: Positive Edge-Triggered D Flip-Flop

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Typical Timing Specifications: Positive Edge-Triggered D Flip-Flop

Uploaded by

Copyright:

Available Formats

Typical Timing Specifications

 Positive edge-triggered D flip-flop

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 3

 Why this works

 Collections of flip-flops with similar controls and logic

OUT1 OUT2 OUT3 OUT4

IN1 IN2 IN3 IN4

 Holds samples of input

OUT1 OUT2 OUT3 OUT4

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 10

always @(posedge clk)

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 11

always @(posedge clk)

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 12

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 13

 Consider one of the four flip-flops

clear s0 s1 new value CLEAR

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 14

always @(posedge clk or clr)

 Sequences through a fixed set of patterns

 Mobius (or Johnson) counter

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 18

 Logic between registers (not just multiplexer)

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 19

always @(posedge clk)

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 20

always @(posedge clk)

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 21

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 24

 Models for representing sequential circuits

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 25

 Divide circuit into combinational logic and state

State Inputs State Outputs

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 26

 Asynchronous sequential logic – state changes occur

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 28

not equal not equal

not new not new not new

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 29

 Shift Register OUT1 OUT2 OUT3

0 000 1 010 101 0 111 1

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 30

001 010 011

000 3-bit up-counter 100

111 110 101

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 31

always @(q) //Calculate next state

always @(posedge clk) //next becomes current state

OUT1 OUT2 OUT3

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 33

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 34

 Tabular form of state diagram

current state next state

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 35

 Programmable Logic Building Block for Sequential Logic

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 37

 Values stored in registers represent the state of the

 Outputs: O1, O2, ..., On

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 44

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 45

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 46

LOST: Forward until we

CS 150 - Spring 2008 – Lec #6: Moore and Mealy Machines - 47